diff options
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2012-11-05 21:30:38 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-11-06 03:54:42 -0500 |
| commit | ab6f6d85210c4d0265cf48e9958c04e08595055a (patch) | |
| tree | 95a3371ac6700bc5b7d351b93a2190ec48e65416 /include | |
| parent | 80b4addc9c697c8d515afdaf671b948b3de6801c (diff) | |
ASoC: fsi: add master clock control functions
Current FSI driver required set_rate() platform callback function
to set audio clock if it was master mode,
because it seemed that CPG/FSI-DIV clocks calculation depend on
platform/board/cpu.
But it was calculable regardless of platform.
This patch supports audio clock calculation method,
but the sampling rate under 32kHz is not supported at this point.
Old type set_rate() is still supported now,
but it will be deleted on next version
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sound/sh_fsi.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/sound/sh_fsi.h b/include/sound/sh_fsi.h index 906010344dd7..27ee1dcc3e2e 100644 --- a/include/sound/sh_fsi.h +++ b/include/sound/sh_fsi.h | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | * A: inversion | 26 | * A: inversion |
| 27 | * B: format mode | 27 | * B: format mode |
| 28 | * C: chip specific | 28 | * C: chip specific |
| 29 | * D: clock selecter if master mode | ||
| 29 | */ | 30 | */ |
| 30 | 31 | ||
| 31 | /* A: clock inversion */ | 32 | /* A: clock inversion */ |
| @@ -44,6 +45,11 @@ | |||
| 44 | #define SH_FSI_OPTION_MASK 0x00000F00 | 45 | #define SH_FSI_OPTION_MASK 0x00000F00 |
| 45 | #define SH_FSI_ENABLE_STREAM_MODE (1 << 8) /* for 16bit data */ | 46 | #define SH_FSI_ENABLE_STREAM_MODE (1 << 8) /* for 16bit data */ |
| 46 | 47 | ||
| 48 | /* D: clock selecter if master mode */ | ||
| 49 | #define SH_FSI_CLK_MASK 0x0000F000 | ||
| 50 | #define SH_FSI_CLK_EXTERNAL (1 << 12) | ||
| 51 | #define SH_FSI_CLK_CPG (2 << 12) /* FSIxCK + FSI-DIV */ | ||
| 52 | |||
| 47 | /* | 53 | /* |
| 48 | * set_rate return value | 54 | * set_rate return value |
| 49 | * | 55 | * |
