Merge tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx into next/dt

From Michal Simek:

arm: Xilinx Zynq dt changes for v3.11

The branch contains:
- DT uart handling cleanup
- Support for zc706 and zed board
- Removal of board compatible string

* tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx:
  arm: dt: zynq: Add support for the zed platform
  arm: dt: zynq: Add support for the zc706 platform
  arm: dt: zynq: Use 'status' property for UART nodes
  arm: zynq: Remove board specific compatibility string
  clk: zynq: Remove deprecated clock code
  arm: zynq: Migrate platform to clock controller
  clk: zynq: Add clock controller driver
  clk: zynq: Factor out PLL driver

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 7 insertions, 1 deletions

diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index 56be7cd9aa8b..e062d317ccce 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2013 Xilinx Inc.
  * Copyright (C) 2012 National Instruments
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,6 +20,11 @@
 #ifndef __LINUX_CLK_ZYNQ_H_
 #define __LINUX_CLK_ZYNQ_H_
 
-void __init xilinx_zynq_clocks_init(void __iomem *slcr);
+#include <linux/spinlock.h>
 
+void zynq_clock_init(void __iomem *slcr);
+
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+                spinlock_t *lock);
 #endif