[ARM] 3500/1: fix PXA27x DMA allocation priority

Patch from Nicolas Pitre

Intel PXA27x developers manual section 5.4.1.1 lists a priority
distribution for the DMA channels differently than what the code
currently assumes.  This patch fixes that.

Noticed by Simon Vogl <vogl@soft.uni-linz.ac.at>

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 14 insertions, 12 deletions

diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index 3e88a2a02a0f..a008150abc59 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -24,27 +24,29 @@ typedef struct pxa_dma_desc {
         volatile u32 dcmd;      /* DCMD value for the current transfer */
 } pxa_dma_desc;
 
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+} pxa_dma_prio;
+
 #if defined(CONFIG_PXA27x)
 
 #define PXA_DMA_CHANNELS        32
-#define PXA_DMA_NBCH(prio)      ((prio == DMA_PRIO_LOW) ? 16 : 8)
 
-typedef enum {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 8,
-        DMA_PRIO_LOW = 16
-} pxa_dma_prio;
+#define pxa_for_each_dma_prio(ch, prio)                                 \
+for (                                                                   \
+        ch = prio * 4;                                                  \
+        ch != (4 << prio) + 16;                                         \
+        ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1)       \
+)
 
 #elif defined(CONFIG_PXA25x)
 
 #define PXA_DMA_CHANNELS        16
-#define PXA_DMA_NBCH(prio)      ((prio == DMA_PRIO_LOW) ? 8 : 4)
 
-typedef enum {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 4,
-        DMA_PRIO_LOW = 8
-} pxa_dma_prio;
+#define pxa_for_each_dma_prio(ch, prio)                                 \
+        for (ch = prio * 4; ch != (4 << prio); ch++)
 
 #endif