diff options
author | Olof Johansson <olof@lixom.net> | 2007-11-28 21:56:20 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-28 18:04:21 -0500 |
commit | 8ee9d85779356c1dc2ba87aca27fbf9414f2d82b (patch) | |
tree | 8054bf7c755e47a41af33b59f344c237b5b20282 /include | |
parent | 40afa5315823761b174926235dc38be24dc3ea63 (diff) |
pasemi: DMA engine management library
pasemi: DMA engine management library
Introduce a DMA management library to manage the various DMA resources
on the PA Semi SoCs. Since several drivers need to allocate these shared
resources, provide some abstractions as well as allocation/free functions
for channels, etc.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-powerpc/pasemi_dma.h | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/include/asm-powerpc/pasemi_dma.h b/include/asm-powerpc/pasemi_dma.h index 8ef80d8bdecd..b4526ff3a50d 100644 --- a/include/asm-powerpc/pasemi_dma.h +++ b/include/asm-powerpc/pasemi_dma.h | |||
@@ -33,11 +33,27 @@ struct pasdma_status { | |||
33 | * device. Use the normal PCI config access functions for them. | 33 | * device. Use the normal PCI config access functions for them. |
34 | */ | 34 | */ |
35 | enum { | 35 | enum { |
36 | PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */ | ||
37 | PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */ | ||
38 | PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */ | ||
36 | PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ | 39 | PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ |
37 | PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ | 40 | PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ |
38 | PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ | 41 | PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ |
39 | PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ | 42 | PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ |
40 | }; | 43 | }; |
44 | |||
45 | |||
46 | #define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */ | ||
47 | #define PAS_DMA_CAP_TXCH_TCHN_S 16 | ||
48 | |||
49 | #define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */ | ||
50 | #define PAS_DMA_CAP_RXCH_RCHN_S 16 | ||
51 | |||
52 | #define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */ | ||
53 | #define PAS_DMA_CAP_IFI_IOFF_S 24 | ||
54 | #define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */ | ||
55 | #define PAS_DMA_CAP_IFI_NIN_S 16 | ||
56 | |||
41 | #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ | 57 | #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ |
42 | #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ | 58 | #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ |
43 | #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ | 59 | #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ |
@@ -388,4 +404,64 @@ enum { | |||
388 | CTRL_CMD_REG_M) | 404 | CTRL_CMD_REG_M) |
389 | 405 | ||
390 | 406 | ||
407 | |||
408 | /* Prototypes for the shared DMA functions in the platform code. */ | ||
409 | |||
410 | /* DMA TX Channel type. Right now only limitations used are event types 0/1, | ||
411 | * for event-triggered DMA transactions. | ||
412 | */ | ||
413 | |||
414 | enum pasemi_dmachan_type { | ||
415 | RXCHAN = 0, /* Any RX chan */ | ||
416 | TXCHAN = 1, /* Any TX chan */ | ||
417 | TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */ | ||
418 | TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */ | ||
419 | }; | ||
420 | |||
421 | struct pasemi_dmachan { | ||
422 | int chno; /* Channel number */ | ||
423 | enum pasemi_dmachan_type chan_type; /* TX / RX */ | ||
424 | u64 *status; /* Ptr to cacheable status */ | ||
425 | int irq; /* IRQ used by channel */ | ||
426 | unsigned int ring_size; /* size of allocated ring */ | ||
427 | dma_addr_t ring_dma; /* DMA address for ring */ | ||
428 | u64 *ring_virt; /* Virt address for ring */ | ||
429 | void *priv; /* Ptr to start of client struct */ | ||
430 | }; | ||
431 | |||
432 | /* Read/write the different registers in the I/O Bridge, Ethernet | ||
433 | * and DMA Controller | ||
434 | */ | ||
435 | extern unsigned int pasemi_read_iob_reg(unsigned int reg); | ||
436 | extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val); | ||
437 | |||
438 | extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg); | ||
439 | extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val); | ||
440 | |||
441 | extern unsigned int pasemi_read_dma_reg(unsigned int reg); | ||
442 | extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val); | ||
443 | |||
444 | /* Channel management routines */ | ||
445 | |||
446 | extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, | ||
447 | int total_size, int offset); | ||
448 | extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan); | ||
449 | |||
450 | extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, | ||
451 | const u32 cmdsta); | ||
452 | extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan); | ||
453 | |||
454 | /* Common routines to allocate rings and buffers */ | ||
455 | |||
456 | extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size); | ||
457 | extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan); | ||
458 | |||
459 | extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, | ||
460 | dma_addr_t *handle); | ||
461 | extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, | ||
462 | dma_addr_t *handle); | ||
463 | |||
464 | /* Initialize the library, must be called before any other functions */ | ||
465 | extern int pasemi_dma_init(void); | ||
466 | |||
391 | #endif /* ASM_PASEMI_DMA_H */ | 467 | #endif /* ASM_PASEMI_DMA_H */ |