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authorViresh Kumar <viresh.kumar@st.com>2012-02-01 05:42:20 -0500
committerVinod Koul <vinod.koul@linux.intel.com>2012-02-22 07:45:37 -0500
commit8c9f7aa316f547f70d270a08d1212f958721c071 (patch)
tree84ca56d95dc87195042dcd6e6d3b255536d6edd0 /include
parent258aea76f552cc755da92e7e823abbb85e021514 (diff)
dmaengine/amba-pl08x: Take flow controller info from DMA_SLAVE_CONFIG
Flow controller information is passed now from DMA_SLAVE_CONFIG option. This patch makes changes in pl08x driver to use device_fc from it instead of platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/amba/pl08x.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 033f6aa670de..2c58853ca423 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -47,9 +47,6 @@ enum {
47 * @muxval: a number usually used to poke into some mux regiser to 47 * @muxval: a number usually used to poke into some mux regiser to
48 * mux in the signal to this channel 48 * mux in the signal to this channel
49 * @cctl_opt: default options for the channel control register 49 * @cctl_opt: default options for the channel control register
50 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
51 * channels. Fill with 'true' if peripheral should be flow controller. Direction
52 * will be selected at Runtime.
53 * @addr: source/target address in physical memory for this DMA channel, 50 * @addr: source/target address in physical memory for this DMA channel,
54 * can be the address of a FIFO register for burst requests for example. 51 * can be the address of a FIFO register for burst requests for example.
55 * This can be left undefined if the PrimeCell API is used for configuring 52 * This can be left undefined if the PrimeCell API is used for configuring
@@ -68,7 +65,6 @@ struct pl08x_channel_data {
68 int max_signal; 65 int max_signal;
69 u32 muxval; 66 u32 muxval;
70 u32 cctl; 67 u32 cctl;
71 bool device_fc;
72 dma_addr_t addr; 68 dma_addr_t addr;
73 bool circular_buffer; 69 bool circular_buffer;
74 bool single; 70 bool single;
@@ -183,6 +179,9 @@ enum pl08x_dma_chan_state {
183 * @host: a pointer to the host (internal use) 179 * @host: a pointer to the host (internal use)
184 * @state: whether the channel is idle, paused, running etc 180 * @state: whether the channel is idle, paused, running etc
185 * @slave: whether this channel is a device (slave) or for memcpy 181 * @slave: whether this channel is a device (slave) or for memcpy
182 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
183 * channels. Fill with 'true' if peripheral should be flow controller. Direction
184 * will be selected at Runtime.
186 * @waiting: a TX descriptor on this channel which is waiting for a physical 185 * @waiting: a TX descriptor on this channel which is waiting for a physical
187 * channel to become available 186 * channel to become available
188 */ 187 */
@@ -205,6 +204,7 @@ struct pl08x_dma_chan {
205 struct pl08x_driver_data *host; 204 struct pl08x_driver_data *host;
206 enum pl08x_dma_chan_state state; 205 enum pl08x_dma_chan_state state;
207 bool slave; 206 bool slave;
207 bool device_fc;
208 struct pl08x_txd *waiting; 208 struct pl08x_txd *waiting;
209}; 209};
210 210