diff options
| author | Krzysztof Halasa <khc@pm.waw.pl> | 2008-01-01 15:55:23 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-02-04 08:15:25 -0500 |
| commit | 82a96f5790ac93a406be72ed8f308dd29ad7e6af (patch) | |
| tree | 29e3029fa42938370b4cdfc0202593374aa366e6 /include | |
| parent | c18f65816ef80b67eb4511ed8359c2dfcd69680d (diff) | |
[ARM] 4713/3: Adds drivers for IXP4xx QMgr and NPE features
This patch adds drivers for IXP4xx hardware Queue Manager and for
Network Processor Engines. Requires patch #4712 (reading/writing
CPU feature (aka fuse) bits).
Posted to linux-arm-kernel on 2 Dec 2007 and revised.
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/npe.h | 39 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/qmgr.h | 126 |
2 files changed, 165 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h new file mode 100644 index 000000000000..37d0511689dc --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/npe.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | #ifndef __IXP4XX_NPE_H | ||
| 2 | #define __IXP4XX_NPE_H | ||
| 3 | |||
| 4 | #include <linux/kernel.h> | ||
| 5 | |||
| 6 | extern const char *npe_names[]; | ||
| 7 | |||
| 8 | struct npe_regs { | ||
| 9 | u32 exec_addr, exec_data, exec_status_cmd, exec_count; | ||
| 10 | u32 action_points[4]; | ||
| 11 | u32 watchpoint_fifo, watch_count; | ||
| 12 | u32 profile_count; | ||
| 13 | u32 messaging_status, messaging_control; | ||
| 14 | u32 mailbox_status, /*messaging_*/ in_out_fifo; | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct npe { | ||
| 18 | struct resource *mem_res; | ||
| 19 | struct npe_regs __iomem *regs; | ||
| 20 | u32 regs_phys; | ||
| 21 | int id; | ||
| 22 | int valid; | ||
| 23 | }; | ||
| 24 | |||
| 25 | |||
| 26 | static inline const char *npe_name(struct npe *npe) | ||
| 27 | { | ||
| 28 | return npe_names[npe->id]; | ||
| 29 | } | ||
| 30 | |||
| 31 | int npe_running(struct npe *npe); | ||
| 32 | int npe_send_message(struct npe *npe, const void *msg, const char *what); | ||
| 33 | int npe_recv_message(struct npe *npe, void *msg, const char *what); | ||
| 34 | int npe_send_recv_message(struct npe *npe, void *msg, const char *what); | ||
| 35 | int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); | ||
| 36 | struct npe *npe_request(int id); | ||
| 37 | void npe_release(struct npe *npe); | ||
| 38 | |||
| 39 | #endif /* __IXP4XX_NPE_H */ | ||
diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h new file mode 100644 index 000000000000..1e52b95cede5 --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/qmgr.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of version 2 of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef IXP4XX_QMGR_H | ||
| 10 | #define IXP4XX_QMGR_H | ||
| 11 | |||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | |||
| 15 | #define HALF_QUEUES 32 | ||
| 16 | #define QUEUES 64 /* only 32 lower queues currently supported */ | ||
| 17 | #define MAX_QUEUE_LENGTH 4 /* in dwords */ | ||
| 18 | |||
| 19 | #define QUEUE_STAT1_EMPTY 1 /* queue status bits */ | ||
| 20 | #define QUEUE_STAT1_NEARLY_EMPTY 2 | ||
| 21 | #define QUEUE_STAT1_NEARLY_FULL 4 | ||
| 22 | #define QUEUE_STAT1_FULL 8 | ||
| 23 | #define QUEUE_STAT2_UNDERFLOW 1 | ||
| 24 | #define QUEUE_STAT2_OVERFLOW 2 | ||
| 25 | |||
| 26 | #define QUEUE_WATERMARK_0_ENTRIES 0 | ||
| 27 | #define QUEUE_WATERMARK_1_ENTRY 1 | ||
| 28 | #define QUEUE_WATERMARK_2_ENTRIES 2 | ||
| 29 | #define QUEUE_WATERMARK_4_ENTRIES 3 | ||
| 30 | #define QUEUE_WATERMARK_8_ENTRIES 4 | ||
| 31 | #define QUEUE_WATERMARK_16_ENTRIES 5 | ||
| 32 | #define QUEUE_WATERMARK_32_ENTRIES 6 | ||
| 33 | #define QUEUE_WATERMARK_64_ENTRIES 7 | ||
| 34 | |||
| 35 | /* queue interrupt request conditions */ | ||
| 36 | #define QUEUE_IRQ_SRC_EMPTY 0 | ||
| 37 | #define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 | ||
| 38 | #define QUEUE_IRQ_SRC_NEARLY_FULL 2 | ||
| 39 | #define QUEUE_IRQ_SRC_FULL 3 | ||
| 40 | #define QUEUE_IRQ_SRC_NOT_EMPTY 4 | ||
| 41 | #define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 | ||
| 42 | #define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 | ||
| 43 | #define QUEUE_IRQ_SRC_NOT_FULL 7 | ||
| 44 | |||
| 45 | struct qmgr_regs { | ||
| 46 | u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ | ||
| 47 | u32 stat1[4]; /* 0x400 - 0x40F */ | ||
| 48 | u32 stat2[2]; /* 0x410 - 0x417 */ | ||
| 49 | u32 statne_h; /* 0x418 - queue nearly empty */ | ||
| 50 | u32 statf_h; /* 0x41C - queue full */ | ||
| 51 | u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ | ||
| 52 | u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ | ||
| 53 | u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ | ||
| 54 | u32 reserved[1776]; | ||
| 55 | u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ | ||
| 56 | }; | ||
| 57 | |||
| 58 | void qmgr_set_irq(unsigned int queue, int src, | ||
| 59 | void (*handler)(void *pdev), void *pdev); | ||
| 60 | void qmgr_enable_irq(unsigned int queue); | ||
| 61 | void qmgr_disable_irq(unsigned int queue); | ||
| 62 | |||
| 63 | /* request_ and release_queue() must be called from non-IRQ context */ | ||
| 64 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | ||
| 65 | unsigned int nearly_empty_watermark, | ||
| 66 | unsigned int nearly_full_watermark); | ||
| 67 | void qmgr_release_queue(unsigned int queue); | ||
| 68 | |||
| 69 | |||
| 70 | static inline void qmgr_put_entry(unsigned int queue, u32 val) | ||
| 71 | { | ||
| 72 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 73 | __raw_writel(val, &qmgr_regs->acc[queue][0]); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline u32 qmgr_get_entry(unsigned int queue) | ||
| 77 | { | ||
| 78 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 79 | return __raw_readl(&qmgr_regs->acc[queue][0]); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline int qmgr_get_stat1(unsigned int queue) | ||
| 83 | { | ||
| 84 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 85 | return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) | ||
| 86 | >> ((queue & 7) << 2)) & 0xF; | ||
| 87 | } | ||
| 88 | |||
| 89 | static inline int qmgr_get_stat2(unsigned int queue) | ||
| 90 | { | ||
| 91 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 92 | return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) | ||
| 93 | >> ((queue & 0xF) << 1)) & 0x3; | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline int qmgr_stat_empty(unsigned int queue) | ||
| 97 | { | ||
| 98 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline int qmgr_stat_nearly_empty(unsigned int queue) | ||
| 102 | { | ||
| 103 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); | ||
| 104 | } | ||
| 105 | |||
| 106 | static inline int qmgr_stat_nearly_full(unsigned int queue) | ||
| 107 | { | ||
| 108 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline int qmgr_stat_full(unsigned int queue) | ||
| 112 | { | ||
| 113 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline int qmgr_stat_underflow(unsigned int queue) | ||
| 117 | { | ||
| 118 | return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline int qmgr_stat_overflow(unsigned int queue) | ||
| 122 | { | ||
| 123 | return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); | ||
| 124 | } | ||
| 125 | |||
| 126 | #endif | ||
