ARM: KVM: move GIC/timer code to a common location

As KVM/arm64 is looming on the horizon, it makes sense to move some
of the common code to a single location in order to reduce duplication.

The code could live anywhere. Actually, most of KVM is already built
with a bunch of ugly ../../.. hacks in the various Makefiles, so we're
not exactly talking about style here. But maybe it is time to start
moving into a less ugly direction.

The include files must be in a "public" location, as they are accessed
from non-KVM files (arch/arm/kernel/asm-offsets.c).

For this purpose, introduce two new locations:
- virt/kvm/arm/ : x86 and ia64 already share the ioapic code in
  virt/kvm, so this could be seen as a (very ugly) precedent.
- include/kvm/  : there is already an include/xen, and while the
  intent is slightly different, this seems as good a location as
  any

Eventually, we should probably have independant Makefiles at every
levels (just like everywhere else in the kernel), but this is just
the first step.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>

2 files changed, 305 insertions, 0 deletions

diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
new file mode 100644
index 000000000000..68cb9e1dfb81
--- /dev/null
+++ b/include/kvm/arm_arch_timer.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
+#define __ASM_ARM_KVM_ARCH_TIMER_H
+
+#include <linux/clocksource.h>
+#include <linux/hrtimer.h>
+#include <linux/workqueue.h>
+
+struct arch_timer_kvm {
+#ifdef CONFIG_KVM_ARM_TIMER
+        /* Is the timer enabled */
+        bool                    enabled;
+
+        /* Virtual offset */
+        cycle_t                 cntvoff;
+#endif
+};
+
+struct arch_timer_cpu {
+#ifdef CONFIG_KVM_ARM_TIMER
+        /* Registers: control register, timer value */
+        u32                             cntv_ctl;       /* Saved/restored */
+        cycle_t                         cntv_cval;      /* Saved/restored */
+
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+
+        /* Background timer used when the guest is not running */
+        struct hrtimer                  timer;
+
+        /* Work queued with the above timer expires */
+        struct work_struct              expired;
+
+        /* Background timer active */
+        bool                            armed;
+
+        /* Timer IRQ */
+        const struct kvm_irq_level      *irq;
+#endif
+};
+
+#ifdef CONFIG_KVM_ARM_TIMER
+int kvm_timer_hyp_init(void);
+int kvm_timer_init(struct kvm *kvm);
+void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
+void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
+void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
+void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
+#else
+static inline int kvm_timer_hyp_init(void)
+{
+        return 0;
+};
+
+static inline int kvm_timer_init(struct kvm *kvm)
+{
+        return 0;
+}
+
+static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
+#endif
+
+#endif
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
new file mode 100644
index 000000000000..343744e4809c
--- /dev/null
+++ b/include/kvm/arm_vgic.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_KVM_VGIC_H
+#define __ASM_ARM_KVM_VGIC_H
+
+#include <linux/kernel.h>
+#include <linux/kvm.h>
+#include <linux/irqreturn.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/irqchip/arm-gic.h>
+
+#define VGIC_NR_IRQS            128
+#define VGIC_NR_SGIS            16
+#define VGIC_NR_PPIS            16
+#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
+#define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
+#define VGIC_MAX_CPUS           KVM_MAX_VCPUS
+#define VGIC_MAX_LRS            (1 << 6)
+
+/* Sanity checks... */
+#if (VGIC_MAX_CPUS > 8)
+#error  Invalid number of CPU interfaces
+#endif
+
+#if (VGIC_NR_IRQS & 31)
+#error "VGIC_NR_IRQS must be a multiple of 32"
+#endif
+
+#if (VGIC_NR_IRQS > 1024)
+#error "VGIC_NR_IRQS must be <= 1024"
+#endif
+
+/*
+ * The GIC distributor registers describing interrupts have two parts:
+ * - 32 per-CPU interrupts (SGI + PPI)
+ * - a bunch of shared interrupts (SPI)
+ */
+struct vgic_bitmap {
+        union {
+                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
+                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
+        } percpu[VGIC_MAX_CPUS];
+        union {
+                u32 reg[VGIC_NR_SHARED_IRQS / 32];
+                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
+        } shared;
+};
+
+struct vgic_bytemap {
+        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
+        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
+};
+
+struct vgic_dist {
+#ifdef CONFIG_KVM_ARM_VGIC
+        spinlock_t              lock;
+        bool                    ready;
+
+        /* Virtual control interface mapping */
+        void __iomem            *vctrl_base;
+
+        /* Distributor and vcpu interface mapping in the guest */
+        phys_addr_t             vgic_dist_base;
+        phys_addr_t             vgic_cpu_base;
+
+        /* Distributor enabled */
+        u32                     enabled;
+
+        /* Interrupt enabled (one bit per IRQ) */
+        struct vgic_bitmap      irq_enabled;
+
+        /* Interrupt 'pin' level */
+        struct vgic_bitmap      irq_state;
+
+        /* Level-triggered interrupt in progress */
+        struct vgic_bitmap      irq_active;
+
+        /* Interrupt priority. Not used yet. */
+        struct vgic_bytemap     irq_priority;
+
+        /* Level/edge triggered */
+        struct vgic_bitmap      irq_cfg;
+
+        /* Source CPU per SGI and target CPU */
+        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
+
+        /* Target CPU for each IRQ */
+        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
+        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
+
+        /* Bitmap indicating which CPU has something pending */