diff options
| author | Mike Turquette <mturquette@linaro.org> | 2014-09-28 13:47:15 -0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-09-28 13:47:15 -0400 |
| commit | 6e18ff26c2b529de06207caa2be9e5f1cf520972 (patch) | |
| tree | 015fefb702a8650266c429167b09fddef5c61005 /include | |
| parent | 7af472485733c19a52bba5d1a064f6d88c0d9880 (diff) | |
| parent | 45bcf9c6f299ae77c14c2ae8cea3f8e540fe80d1 (diff) | |
Merge tag 'hix5hd2-clock-for-3.18-v2' of git://github.com/hisilicon/linux-hisi into clk-next
Hisilicon HiX5HD2 clock updates for 3.18-v2
- Add I2C clocks
- Add watchdog clocks
- Add sd clocks
- Add complex clock implementation to support sata, usb and ethernet
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/hix5hd2-clock.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h index aad579a75802..fd29c174ba63 100644 --- a/include/dt-bindings/clock/hix5hd2-clock.h +++ b/include/dt-bindings/clock/hix5hd2-clock.h | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | #define HIX5HD2_SFC_MUX 64 | 46 | #define HIX5HD2_SFC_MUX 64 |
| 47 | #define HIX5HD2_MMC_MUX 65 | 47 | #define HIX5HD2_MMC_MUX 65 |
| 48 | #define HIX5HD2_FEPHY_MUX 66 | 48 | #define HIX5HD2_FEPHY_MUX 66 |
| 49 | #define HIX5HD2_SD_MUX 67 | ||
| 49 | 50 | ||
| 50 | /* gate clocks */ | 51 | /* gate clocks */ |
| 51 | #define HIX5HD2_SFC_RST 128 | 52 | #define HIX5HD2_SFC_RST 128 |
| @@ -53,6 +54,32 @@ | |||
| 53 | #define HIX5HD2_MMC_CIU_CLK 130 | 54 | #define HIX5HD2_MMC_CIU_CLK 130 |
| 54 | #define HIX5HD2_MMC_BIU_CLK 131 | 55 | #define HIX5HD2_MMC_BIU_CLK 131 |
| 55 | #define HIX5HD2_MMC_CIU_RST 132 | 56 | #define HIX5HD2_MMC_CIU_RST 132 |
| 57 | #define HIX5HD2_FWD_BUS_CLK 133 | ||
| 58 | #define HIX5HD2_FWD_SYS_CLK 134 | ||
| 59 | #define HIX5HD2_MAC0_PHY_CLK 135 | ||
| 60 | #define HIX5HD2_SD_CIU_CLK 136 | ||
| 61 | #define HIX5HD2_SD_BIU_CLK 137 | ||
| 62 | #define HIX5HD2_SD_CIU_RST 138 | ||
| 63 | #define HIX5HD2_WDG0_CLK 139 | ||
| 64 | #define HIX5HD2_WDG0_RST 140 | ||
| 65 | #define HIX5HD2_I2C0_CLK 141 | ||
| 66 | #define HIX5HD2_I2C0_RST 142 | ||
| 67 | #define HIX5HD2_I2C1_CLK 143 | ||
| 68 | #define HIX5HD2_I2C1_RST 144 | ||
| 69 | #define HIX5HD2_I2C2_CLK 145 | ||
| 70 | #define HIX5HD2_I2C2_RST 146 | ||
| 71 | #define HIX5HD2_I2C3_CLK 147 | ||
| 72 | #define HIX5HD2_I2C3_RST 148 | ||
| 73 | #define HIX5HD2_I2C4_CLK 149 | ||
| 74 | #define HIX5HD2_I2C4_RST 150 | ||
| 75 | #define HIX5HD2_I2C5_CLK 151 | ||
| 76 | #define HIX5HD2_I2C5_RST 152 | ||
| 77 | |||
| 78 | /* complex */ | ||
| 79 | #define HIX5HD2_MAC0_CLK 192 | ||
| 80 | #define HIX5HD2_MAC1_CLK 193 | ||
| 81 | #define HIX5HD2_SATA_CLK 194 | ||
| 82 | #define HIX5HD2_USB_CLK 195 | ||
| 56 | 83 | ||
| 57 | #define HIX5HD2_NR_CLKS 256 | 84 | #define HIX5HD2_NR_CLKS 256 |
| 58 | #endif /* __DTS_HIX5HD2_CLOCK_H */ | 85 | #endif /* __DTS_HIX5HD2_CLOCK_H */ |
