[PARISC] Update parisc specific input code from parisc tree

Update drivers to new input layer changes.

Signed-off-by: Helge Deller <deller@parisc-linux.org>
Signed-off-by: Matthew Wilcox <willy@parisc-linux.org>

Reorder code in gscps2_interrupt() and only enable ports when opened.
This fixes issues with hangs booting an SMP kernel on my C360.
Previously serio_interrupt() could be called before the lock in
struct serio was initialised.

Signed-off-by: Richard Hirst <rhirst@parisc-linux.org>

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

4 files changed, 952 insertions, 0 deletions

diff --git a/include/linux/hil.h b/include/linux/hil.h
new file mode 100644
index 000000000000..13352d7d0caf
--- /dev/null
+++ b/include/linux/hil.h
@@ -0,0 +1,483 @@
+#ifndef _HIL_H_
+#define _HIL_H_
+
+/*
+ * Hewlett Packard Human Interface Loop (HP-HIL) Protocol -- header.
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ * A note of thanks to HP for providing and shipping reference materials
+ * free of charge to help in the development of HIL support for Linux.
+ *
+ */
+
+#include <asm/types.h>
+
+/* Physical constants relevant to raw loop/device timing. 
+ */ 
+
+#define HIL_CLOCK               8MHZ
+#define HIL_EK1_CLOCK           30HZ
+#define HIL_EK2_CLOCK           60HZ
+
+#define HIL_TIMEOUT_DEV         5       /* ms */
+#define HIL_TIMEOUT_DEVS        10      /* ms */
+#define HIL_TIMEOUT_NORESP      10      /* ms */
+#define HIL_TIMEOUT_DEVS_DATA   16      /* ms */
+#define HIL_TIMEOUT_SELFTEST    200     /* ms */
+
+
+/* Actual wire line coding.  These will only be useful if someone is 
+ * implementing a software MLC to run HIL devices on a non-parisc machine.
+ */
+
+#define HIL_WIRE_PACKET_LEN     15
+enum hil_wire_bitpos {
+        HIL_WIRE_START          = 0,
+        HIL_WIRE_ADDR2,
+        HIL_WIRE_ADDR1,
+        HIL_WIRE_ADDR0,
+        HIL_WIRE_COMMAND,
+        HIL_WIRE_DATA7,
+        HIL_WIRE_DATA6,
+        HIL_WIRE_DATA5,
+        HIL_WIRE_DATA4,
+        HIL_WIRE_DATA3,
+        HIL_WIRE_DATA2,
+        HIL_WIRE_DATA1,
+        HIL_WIRE_DATA0,
+        HIL_WIRE_PARITY,
+        HIL_WIRE_STOP
+};
+
+/* HP documentation uses these bit positions to refer to commands;
+ * we will call these "packets".
+ */
+enum hil_pkt_bitpos {
+        HIL_PKT_CMD             = 0x00000800,
+        HIL_PKT_ADDR2           = 0x00000400,
+        HIL_PKT_ADDR1           = 0x00000200,
+        HIL_PKT_ADDR0           = 0x00000100,
+        HIL_PKT_ADDR_MASK       = 0x00000700,
+        HIL_PKT_ADDR_SHIFT      = 8,
+        HIL_PKT_DATA7           = 0x00000080,
+        HIL_PKT_DATA6           = 0x00000040,
+        HIL_PKT_DATA5           = 0x00000020,
+        HIL_PKT_DATA4           = 0x00000010,
+        HIL_PKT_DATA3           = 0x00000008,
+        HIL_PKT_DATA2           = 0x00000004,
+        HIL_PKT_DATA1           = 0x00000002,
+        HIL_PKT_DATA0           = 0x00000001,
+        HIL_PKT_DATA_MASK       = 0x000000FF,
+        HIL_PKT_DATA_SHIFT      = 0
+};
+
+/* The HIL MLC also has several error/status/control bits.  We extend the 
+ * "packet" to include these when direct access to the MLC is available,
+ * or emulate them in cases where they are not available. 
+ *
+ * This way the device driver knows that the underlying MLC driver
+ * has had to deal with loop errors.
+ */
+enum hil_error_bitpos {
+        HIL_ERR_OB      = 0x00000800, /* MLC is busy sending an auto-poll, 
+                                         or we have filled up the output 
+                                         buffer and must wait. */
+        HIL_ERR_INT     = 0x00010000, /* A normal interrupt has occurred. */
+        HIL_ERR_NMI     = 0x00020000, /* An NMI has occurred. */
+        HIL_ERR_LERR    = 0x00040000, /* A poll didn't come back. */
+        HIL_ERR_PERR    = 0x01000000, /* There was a Parity Error. */
+        HIL_ERR_FERR    = 0x02000000, /* There was a Framing Error. */
+        HIL_ERR_FOF     = 0x04000000  /* Input FIFO Overflowed. */
+};
+
+enum hil_control_bitpos {
+        HIL_CTRL_TEST   = 0x00010000,
+        HIL_CTRL_IPF    = 0x00040000,
+        HIL_CTRL_APE    = 0x02000000
+};
+
+/* Bits 30,31 are unused, we use them to control write behavior. */
+#define HIL_DO_ALTER_CTRL  0x40000000 /* Write MSW of packet to control 
+                                          before writing LSW to loop */
+#define HIL_CTRL_ONLY      0xc0000000 /* *Only* alter the control registers */
+
+/* This gives us a 32-bit "packet" 
+ */
+typedef u32 hil_packet;
+
+
+/* HIL Loop commands 
+ */
+enum hil_command {
+        HIL_CMD_IFC     = 0x00, /* Interface Clear */
+        HIL_CMD_EPT     = 0x01, /* Enter Pass-Thru Mode */
+        HIL_CMD_ELB     = 0x02, /* Enter Loop-Back Mode */
+        HIL_CMD_IDD     = 0x03, /* Identify and Describe */
+        HIL_CMD_DSR     = 0x04, /* Device Soft Reset */
+        HIL_CMD_PST     = 0x05, /* Perform Self Test */
+        HIL_CMD_RRG     = 0x06, /* Read Register */
+        HIL_CMD_WRG     = 0x07, /* Write Register */
+        HIL_CMD_ACF     = 0x08, /* Auto Configure */
+        HIL_CMDID_ACF   = 0x07, /* Auto Configure bits with incremented ID */
+        HIL_CMD_POL     = 0x10, /* Poll */
+        HIL_CMDCT_POL   = 0x0f, /* Poll command bits with item count  */
+        HIL_CMD_RPL     = 0x20, /* RePoll */
+        HIL_CMDCT_RPL   = 0x0f, /* RePoll command bits with item count */
+        HIL_CMD_RNM     = 0x30, /* Report Name */
+        HIL_CMD_RST     = 0x31, /* Report Status */
+        HIL_CMD_EXD     = 0x32, /* Extended Describe */
+        HIL_CMD_RSC     = 0x33, /* Report Security Code */
+
+        /* 0x34 to 0x3c reserved for future use  */
+
+        HIL_CMD_DKA     = 0x3d, /* Disable Keyswitch Autorepeat */
+        HIL_CMD_EK1     = 0x3e, /* Enable Keyswitch Autorepeat 1 */
+        HIL_CMD_EK2     = 0x3f, /* Enable Keyswitch Autorepeat 2 */
+        HIL_CMD_PR1     = 0x40, /* Prompt1 */  
+        HIL_CMD_PR2     = 0x41, /* Prompt2 */
+        HIL_CMD_PR3     = 0x42, /* Prompt3 */
+        HIL_CMD_PR4     = 0x43, /* Prompt4 */
+        HIL_CMD_PR5     = 0x44, /* Prompt5 */
+        HIL_CMD_PR6     = 0x45, /* Prompt6 */
+        HIL_CMD_PR7     = 0x46, /* Prompt7 */
+        HIL_CMD_PRM     = 0x47, /* Prompt (General Purpose) */
+        HIL_CMD_AK1     = 0x48, /* Acknowlege1 */  
+        HIL_CMD_AK2     = 0x49, /* Acknowlege2 */
+        HIL_CMD_AK3     = 0x4a, /* Acknowlege3 */
+        HIL_CMD_AK4     = 0x4b, /* Acknowlege4 */
+        HIL_CMD_AK5     = 0x4c, /* Acknowlege5 */
+        HIL_CMD_AK6     = 0x4d, /* Acknowlege6 */
+        HIL_CMD_AK7     = 0x4e, /* Acknowlege7 */
+        HIL_CMD_ACK     = 0x4f, /* Acknowlege (General Purpose) */
+
+        /* 0x50 to 0x78 reserved for future use  */
+        /* 0x80 to 0xEF device-specific commands */
+        /* 0xf0 to 0xf9 reserved for future use  */
+
+        HIL_CMD_RIO     = 0xfa, /* Register I/O Error */
+        HIL_CMD_SHR     = 0xfb, /* System Hard Reset */
+        HIL_CMD_TER     = 0xfc, /* Transmission Error */
+        HIL_CMD_CAE     = 0xfd, /* Configuration Address Error */
+        HIL_CMD_DHR     = 0xfe, /* Device Hard Reset */
+
+        /* 0xff is prohibited from use. */
+};