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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
commit5f76945a9c978b8b8bf8eb7fe3b17b9981240a97 (patch)
treedf61aca168df657bc71ce8b578bcb0c81b0622ee /include
parent940e3a8dd6683a3787faf769b3df7a06f1c2fa31 (diff)
parentcd9d6f10d07f26dd8a70e519c22b6b4f8a9e3e7a (diff)
Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6
Pull fbdev updates from Florian Tobias Schandinat: "This includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches" Fix up some trivial conflicts (mostly just include line changes, but also some due to the renaming of the deferred work functions by Tejun). * tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6: (193 commits) gbefb: fix compile error video: mark nuc900fb_map_video_memory as __devinit video/mx3fb: set .owner to prevent module unloading while being used video: exynos_dp: use clk_prepare_enable and clk_disable_unprepare drivers/video/exynos/exynos_mipi_dsi.c: fix error return code drivers/video/savage/savagefb_driver.c: fix error return code video: s3c-fb: use clk_prepare_enable and clk_disable_unprepare da8xx-fb: save and restore LCDC context across suspend/resume cycle da8xx-fb: add pm_runtime support video/udlfb: fix line counting in fb_write OMAPDSS: add missing include for string.h OMAPDSS: DISPC: Configure color conversion coefficients for writeback OMAPDSS: DISPC: Add manager like functions for writeback OMAPDSS: DISPC: Configure writeback FIFOs OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup OMAPDSS: DISPC: Add function to set channel in for writeback OMAPDSS: DISPC: Don't set chroma resampling bit for writeback OMAPDSS: DISPC: Downscale chroma if plane is writeback OMAPDSS: DISPC: Configure input and output sizes for writeback ...
Diffstat (limited to 'include')
-rw-r--r--include/video/omapdss.h112
-rw-r--r--include/video/samsung_fimd.h533
2 files changed, 626 insertions, 19 deletions
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index a6267a2d292b..3729173b7fbc 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -48,10 +48,10 @@
48#define DISPC_IRQ_FRAMEDONEWB (1 << 23) 48#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49#define DISPC_IRQ_FRAMEDONETV (1 << 24) 49#define DISPC_IRQ_FRAMEDONETV (1 << 24)
50#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 50#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
51#define DISPC_IRQ_FRAMEDONE3 (1 << 26) 51#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
52#define DISPC_IRQ_VSYNC3 (1 << 27) 52#define DISPC_IRQ_VSYNC3 (1 << 28)
53#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 28) 53#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
54#define DISPC_IRQ_SYNC_LOST3 (1 << 29) 54#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
55 55
56struct omap_dss_device; 56struct omap_dss_device;
57struct omap_overlay_manager; 57struct omap_overlay_manager;
@@ -73,6 +73,7 @@ enum omap_plane {
73 OMAP_DSS_VIDEO1 = 1, 73 OMAP_DSS_VIDEO1 = 1,
74 OMAP_DSS_VIDEO2 = 2, 74 OMAP_DSS_VIDEO2 = 2,
75 OMAP_DSS_VIDEO3 = 3, 75 OMAP_DSS_VIDEO3 = 3,
76 OMAP_DSS_WB = 4,
76}; 77};
77 78
78enum omap_channel { 79enum omap_channel {
@@ -186,6 +187,8 @@ enum omap_overlay_caps {
186 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 187 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
187 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 188 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
188 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 189 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
190 OMAP_DSS_OVL_CAP_POS = 1 << 4,
191 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
189}; 192};
190 193
191enum omap_overlay_manager_caps { 194enum omap_overlay_manager_caps {
@@ -207,6 +210,16 @@ enum omap_hdmi_flags {
207 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 210 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
208}; 211};
209 212
213enum omap_dss_output_id {
214 OMAP_DSS_OUTPUT_DPI = 1 << 0,
215 OMAP_DSS_OUTPUT_DBI = 1 << 1,
216 OMAP_DSS_OUTPUT_SDI = 1 << 2,
217 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
218 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
219 OMAP_DSS_OUTPUT_VENC = 1 << 5,
220 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
221};
222
210/* RFBI */ 223/* RFBI */
211 224
212struct rfbi_timings { 225struct rfbi_timings {
@@ -243,7 +256,7 @@ void rfbi_bus_unlock(void);
243 256
244/* DSI */ 257/* DSI */
245 258
246struct omap_dss_dsi_videomode_data { 259struct omap_dss_dsi_videomode_timings {
247 /* DSI video mode blanking data */ 260 /* DSI video mode blanking data */
248 /* Unit: byte clock cycles */ 261 /* Unit: byte clock cycles */
249 u16 hsa; 262 u16 hsa;
@@ -424,6 +437,8 @@ struct omap_overlay {
424 struct omap_overlay_info *info); 437 struct omap_overlay_info *info);
425 438
426 int (*wait_for_go)(struct omap_overlay *ovl); 439 int (*wait_for_go)(struct omap_overlay *ovl);
440
441 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
427}; 442};
428 443
429struct omap_overlay_manager_info { 444struct omap_overlay_manager_info {
@@ -448,9 +463,10 @@ struct omap_overlay_manager {
448 enum omap_overlay_manager_caps caps; 463 enum omap_overlay_manager_caps caps;
449 struct list_head overlays; 464 struct list_head overlays;
450 enum omap_display_type supported_displays; 465 enum omap_display_type supported_displays;
466 enum omap_dss_output_id supported_outputs;
451 467
452 /* dynamic fields */ 468 /* dynamic fields */
453 struct omap_dss_device *device; 469 struct omap_dss_output *output;
454 470
455 /* 471 /*
456 * The following functions do not block: 472 * The following functions do not block:
@@ -463,9 +479,9 @@ struct omap_overlay_manager {
463 * interrupt context 479 * interrupt context
464 */ 480 */
465 481
466 int (*set_device)(struct omap_overlay_manager *mgr, 482 int (*set_output)(struct omap_overlay_manager *mgr,
467 struct omap_dss_device *dssdev); 483 struct omap_dss_output *output);
468 int (*unset_device)(struct omap_overlay_manager *mgr); 484 int (*unset_output)(struct omap_overlay_manager *mgr);
469 485
470 int (*set_manager_info)(struct omap_overlay_manager *mgr, 486 int (*set_manager_info)(struct omap_overlay_manager *mgr,
471 struct omap_overlay_manager_info *info); 487 struct omap_overlay_manager_info *info);
@@ -475,6 +491,8 @@ struct omap_overlay_manager {
475 int (*apply)(struct omap_overlay_manager *mgr); 491 int (*apply)(struct omap_overlay_manager *mgr);
476 int (*wait_for_go)(struct omap_overlay_manager *mgr); 492 int (*wait_for_go)(struct omap_overlay_manager *mgr);
477 int (*wait_for_vsync)(struct omap_overlay_manager *mgr); 493 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
494
495 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
478}; 496};
479 497
480/* 22 pins means 1 clk lane and 10 data lanes */ 498/* 22 pins means 1 clk lane and 10 data lanes */
@@ -492,6 +510,37 @@ struct omap_dsi_pin_config {
492 int pins[OMAP_DSS_MAX_DSI_PINS]; 510 int pins[OMAP_DSS_MAX_DSI_PINS];
493}; 511};
494 512
513struct omap_dss_writeback_info {
514 u32 paddr;
515 u32 p_uv_addr;
516 u16 buf_width;
517 u16 width;
518 u16 height;
519 enum omap_color_mode color_mode;
520 u8 rotation;
521 enum omap_dss_rotation_type rotation_type;
522 bool mirror;
523 u8 pre_mult_alpha;
524};
525
526struct omap_dss_output {
527 struct list_head list;
528
529 /* display type supported by the output */
530 enum omap_display_type type;
531
532 /* output instance */
533 enum omap_dss_output_id id;
534
535 /* output's platform device pointer */
536 struct platform_device *pdev;
537
538 /* dynamic fields */
539 struct omap_overlay_manager *manager;
540
541 struct omap_dss_device *device;
542};
543
495struct omap_dss_device { 544struct omap_dss_device {
496 struct device dev; 545 struct device dev;
497 546
@@ -564,7 +613,7 @@ struct omap_dss_device {
564 613
565 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 614 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
566 enum omap_dss_dsi_mode dsi_mode; 615 enum omap_dss_dsi_mode dsi_mode;
567 struct omap_dss_dsi_videomode_data dsi_vm_data; 616 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
568 } panel; 617 } panel;
569 618
570 struct { 619 struct {
@@ -590,7 +639,7 @@ struct omap_dss_device {
590 639
591 enum omap_display_caps caps; 640 enum omap_display_caps caps;
592 641
593 struct omap_overlay_manager *manager; 642 struct omap_dss_output *output;
594 643
595 enum omap_dss_display_state state; 644 enum omap_dss_display_state state;
596 645
@@ -605,6 +654,8 @@ struct omap_dss_device {
605 654
606struct omap_dss_hdmi_data 655struct omap_dss_hdmi_data
607{ 656{
657 int ct_cp_hpd_gpio;
658 int ls_oe_gpio;
608 int hpd_gpio; 659 int hpd_gpio;
609}; 660};
610 661
@@ -699,6 +750,11 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
699int omap_dss_get_num_overlays(void); 750int omap_dss_get_num_overlays(void);
700struct omap_overlay *omap_dss_get_overlay(int num); 751struct omap_overlay *omap_dss_get_overlay(int num);
701 752
753struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
754int omapdss_output_set_device(struct omap_dss_output *out,
755 struct omap_dss_device *dssdev);
756int omapdss_output_unset_device(struct omap_dss_output *out);
757
702void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 758void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
703 u16 *xres, u16 *yres); 759 u16 *xres, u16 *yres);
704int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 760int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
@@ -719,6 +775,15 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
719void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 775void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
720 bool enable); 776 bool enable);
721int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); 777int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
778void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
779 struct omap_video_timings *timings);
780void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
781void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
782 enum omap_dss_dsi_pixel_format fmt);
783void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
784 enum omap_dss_dsi_mode mode);
785void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
786 struct omap_dss_dsi_videomode_timings *timings);
722 787
723int omap_dsi_update(struct omap_dss_device *dssdev, int channel, 788int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
724 void (*callback)(int, void *), void *data); 789 void (*callback)(int, void *), void *data);
@@ -727,6 +792,8 @@ int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
727void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); 792void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
728int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, 793int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
729 const struct omap_dsi_pin_config *pin_cfg); 794 const struct omap_dsi_pin_config *pin_cfg);
795int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
796 unsigned long ddr_clk, unsigned long lp_clk);
730 797
731int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); 798int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
732void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, 799void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
@@ -734,22 +801,29 @@ void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
734 801
735int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); 802int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
736void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); 803void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
737void dpi_set_timings(struct omap_dss_device *dssdev, 804void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
738 struct omap_video_timings *timings); 805 struct omap_video_timings *timings);
739int dpi_check_timings(struct omap_dss_device *dssdev, 806int dpi_check_timings(struct omap_dss_device *dssdev,
740 struct omap_video_timings *timings); 807 struct omap_video_timings *timings);
808void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
741 809
742int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); 810int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
743void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); 811void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
812void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
813 struct omap_video_timings *timings);
814void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
744 815
745int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); 816int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
746void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); 817void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
747int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, 818int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
748 u16 *x, u16 *y, u16 *w, u16 *h); 819 void *data);
749int omap_rfbi_update(struct omap_dss_device *dssdev, 820int omap_rfbi_configure(struct omap_dss_device *dssdev);
750 u16 x, u16 y, u16 w, u16 h, 821void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
751 void (*callback)(void *), void *data); 822void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
752int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size, 823 int pixel_size);
824void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
753 int data_lines); 825 int data_lines);
826void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
827 struct rfbi_timings *timings);
754 828
755#endif 829#endif
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
new file mode 100644
index 000000000000..7ae6c07f2ef8
--- /dev/null
+++ b/include/video/samsung_fimd.h
@@ -0,0 +1,533 @@
1/* include/video/samsung_fimd.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style fimd and framebuffer register definitions
9 *
10 * This is the register set for the fimd and new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* VIDCON0 */
24
25#define VIDCON0 (0x00)
26#define VIDCON0_INTERLACE (1 << 29)
27#define VIDCON0_VIDOUT_MASK (0x3 << 26)
28#define VIDCON0_VIDOUT_SHIFT (26)
29#define VIDCON0_VIDOUT_RGB (0x0 << 26)
30#define VIDCON0_VIDOUT_TV (0x1 << 26)
31#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
32#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
33
34#define VIDCON0_L1_DATA_MASK (0x7 << 23)
35#define VIDCON0_L1_DATA_SHIFT (23)
36#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
37#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
38#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
39#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
40#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
41#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
42
43#define VIDCON0_L0_DATA_MASK (0x7 << 20)
44#define VIDCON0_L0_DATA_SHIFT (20)
45#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
46#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
47#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
48#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
49#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
50#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
51
52#define VIDCON0_PNRMODE_MASK (0x3 << 17)
53#define VIDCON0_PNRMODE_SHIFT (17)
54#define VIDCON0_PNRMODE_RGB (0x0 << 17)
55#define VIDCON0_PNRMODE_BGR (0x1 << 17)
56#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
57#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
58
59#define VIDCON0_CLKVALUP (1 << 16)
60#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
61#define VIDCON0_CLKVAL_F_SHIFT (6)
62#define VIDCON0_CLKVAL_F_LIMIT (0xff)
63#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
64#define VIDCON0_VLCKFREE (1 << 5)
65#define VIDCON0_CLKDIR (1 << 4)
66
67#define VIDCON0_CLKSEL_MASK (0x3 << 2)
68#define VIDCON0_CLKSEL_SHIFT (2)
69#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
70#define VIDCON0_CLKSEL_LCD (0x1 << 2)
71#define VIDCON0_CLKSEL_27M (0x3 << 2)
72
73#define VIDCON0_ENVID (1 << 1)
74#define VIDCON0_ENVID_F (1 << 0)
75
76#define VIDCON1 (0x04)
77#define VIDCON1_LINECNT_MASK (0x7ff << 16)
78#define VIDCON1_LINECNT_SHIFT (16)
79#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
80#define VIDCON1_VSTATUS_MASK (0x3 << 13)
81#define VIDCON1_VSTATUS_SHIFT (13)
82#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
83#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
84#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
85#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
86#define VIDCON1_VCLK_MASK (0x3 << 9)
87#define VIDCON1_VCLK_HOLD (0x0 << 9)
88#define VIDCON1_VCLK_RUN (0x1 << 9)
89
90#define VIDCON1_INV_VCLK (1 << 7)
91#define VIDCON1_INV_HSYNC (1 << 6)
92#define VIDCON1_INV_VSYNC (1 << 5)
93#define VIDCON1_INV_VDEN (1 << 4)
94
95/* VIDCON2 */
96
97#define VIDCON2 (0x08)
98#define VIDCON2_EN601 (1 << 23)
99#define VIDCON2_TVFMTSEL_SW (1 << 14)
100
101#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
102#define VIDCON2_TVFMTSEL1_SHIFT (12)
103#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
104#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
105#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
106
107#define VIDCON2_ORGYCbCr (1 << 8)
108#define VIDCON2_YUVORDCrCb (1 << 7)
109
110/* PRTCON (S3C6410, S5PC100)
111 * Might not be present in the S3C6410 documentation,
112 * but tests prove it's there almost for sure; shouldn't hurt in any case.
113 */
114#define PRTCON (0x0c)
115#define PRTCON_PROTECT (1 << 11)
116
117/* VIDTCON0 */
118
119#define VIDTCON0_VBPDE_MASK (0xff << 24)
120#define VIDTCON0_VBPDE_SHIFT (24)
121#define VIDTCON0_VBPDE_LIMIT (0xff)
122#define VIDTCON0_VBPDE(_x) ((_x) << 24)
123
124#define VIDTCON0_VBPD_MASK (0xff << 16)
125#define VIDTCON0_VBPD_SHIFT (16)
126#define VIDTCON0_VBPD_LIMIT (0xff)
127#define VIDTCON0_VBPD(_x) ((_x) << 16)
128
129#define VIDTCON0_VFPD_MASK (0xff << 8)
130#define VIDTCON0_VFPD_SHIFT (8)
131#define VIDTCON0_VFPD_LIMIT (0xff)
132#define VIDTCON0_VFPD(_x) ((_x) << 8)
133
134#define VIDTCON0_VSPW_MASK (0xff << 0)
135#define VIDTCON0_VSPW_SHIFT (0)
136#define VIDTCON0_VSPW_LIMIT (0xff)
137#define VIDTCON0_VSPW(_x) ((_x) << 0)
138
139/* VIDTCON1 */
140
141#define VIDTCON1_VFPDE_MASK (0xff << 24)
142#define VIDTCON1_VFPDE_SHIFT (24)
143#define VIDTCON1_VFPDE_LIMIT (0xff)
144#define VIDTCON1_VFPDE(_x) ((_x) << 24)
145
146#define VIDTCON1_HBPD_MASK (0xff << 16)
147#define VIDTCON1_HBPD_SHIFT (16)
148#define VIDTCON1_HBPD_LIMIT (0xff)
149#define VIDTCON1_HBPD(_x) ((_x) << 16)
150
151#define VIDTCON1_HFPD_MASK (0xff << 8)
152#define VIDTCON1_HFPD_SHIFT (8)
153#define VIDTCON1_HFPD_LIMIT (0xff)
154#define VIDTCON1_HFPD(_x) ((_x) << 8)
155
156#define VIDTCON1_HSPW_MASK (0xff << 0)
157#define VIDTCON1_HSPW_SHIFT (0)
158#define VIDTCON1_HSPW_LIMIT (0xff)
159#define VIDTCON1_HSPW(_x) ((_x) << 0)
160
161#define VIDTCON2 (0x18)
162#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
163#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
164#define VIDTCON2_LINEVAL_SHIFT (11)
165#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
166#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
167
168#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
169#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
170#define VIDTCON2_HOZVAL_SHIFT (0)
171#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
172#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
173
174/* WINCONx */
175
176
177#define WINCONx_BITSWP (1 << 18)
178#define WINCONx_BYTSWP (1 << 17)
179#define WINCONx_HAWSWP (1 << 16)
180#define WINCONx_WSWP (1 << 15)
181#define WINCONx_BURSTLEN_MASK (0x3 << 9)
182#define WINCONx_BURSTLEN_SHIFT (9)
183#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
184#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
185#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
186
187#define WINCONx_ENWIN (1 << 0)
188#define WINCON0_BPPMODE_MASK (0xf << 2)
189#define WINCON0_BPPMODE_SHIFT (2)
190#define WINCON0_BPPMODE_1BPP (0x0 << 2)
191#define WINCON0_BPPMODE_2BPP (0x1 << 2)
192#define WINCON0_BPPMODE_4BPP (0x2 << 2)
193#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
194#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
195#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
196#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
197#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
198
199#define WINCON1_BLD_PIX (1 << 6)
200
201#define WINCON1_ALPHA_SEL (1 << 1)
202#define WINCON1_BPPMODE_MASK (0xf << 2)
203#define WINCON1_BPPMODE_SHIFT (2)
204#define WINCON1_BPPMODE_1BPP (0x0 << 2)
205#define WINCON1_BPPMODE_2BPP (0x1 << 2)
206#define WINCON1_BPPMODE_4BPP (0x2 << 2)
207#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
208#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
209#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
210#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
211#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
212#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
213#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
214#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
215#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
216#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
217#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
218#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
219
220/* S5PV210 */
221#define SHADOWCON (0x34)
222#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
223/* DMA channels (all windows) */
224#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
225/* Local input channels (windows 0-2) */
226#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
227
228#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
229#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
230#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
231#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
232#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
233
234#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
235#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
236#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
237#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
238#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
239
240#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
241#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
242#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
243#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
244#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
245
246#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
247#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
248#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
249#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
250#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
251
252/* For VIDOSD[1..4]C */
253#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
254#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
255#define VIDISD14C_ALPHA0_G_SHIFT (16)
256#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
257#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
258#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
259#define VIDISD14C_ALPHA0_B_SHIFT (12)
260#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
261#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
262#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
263#define VIDISD14C_ALPHA1_R_SHIFT (8)
264#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
265#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
266#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
267#define VIDISD14C_ALPHA1_G_SHIFT (4)
268#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
269#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
270#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
271#define VIDISD14C_ALPHA1_B_SHIFT (0)
272#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
273#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
274
275/* Video buffer addresses */
276#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
277#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
278#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
279#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
280#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
281
282#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
283#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
284#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
285#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
286#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
287
288#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
289#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
290#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
291#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
292#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
293
294/* Interrupt controls and status */
295
296#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
297#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
298#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
299#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
300
301#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
302#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
303#define VIDINTCON0_INT_I80IFDONE (1 << 17)
304
305#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
306#define VIDINTCON0_FRAMESEL0_SHIFT (15)
307#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
308#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
309#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
310#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
311
312#define VIDINTCON0_FRAMESEL1 (1 << 13)
313#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
314#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
315#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
316#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
317#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
318
319#define VIDINTCON0_INT_FRAME (1 << 12)
320#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
321#define VIDINTCON0_FIFIOSEL_SHIFT (5)
322#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
323#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
324
325#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
326#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
327#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
328#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
329#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
330#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
331#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
332
333#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
334#define VIDINTCON0_INT_FIFO_SHIFT (0)
335#define VIDINTCON0_INT_ENABLE (1 << 0)
336
337#define VIDINTCON1 (0x134)
338#define VIDINTCON1_INT_I180 (1 << 2)
339#define VIDINTCON1_INT_FRAME (1 << 1)
340#define VIDINTCON1_INT_FIFO (1 << 0)
341
342/* Window colour-key control registers */
343#define WKEYCON (0x140) /* 6410,V210 */
344
345#define WKEYCON0 (0x00)
346#define WKEYCON1 (0x04)
347
348#define WxKEYCON0_KEYBL_EN (1 << 26)
349#define WxKEYCON0_KEYEN_F (1 << 25)
350#define WxKEYCON0_DIRCON (1 << 24)
351#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
352#define WxKEYCON0_COMPKEY_SHIFT (0)
353#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
354#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
355#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
356#define WxKEYCON1_COLVAL_SHIFT (0)
357#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
358#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
359
360
361/* Window blanking (MAP) */
362
363#define WINxMAP_MAP (1 << 24)
364#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
365#define WINxMAP_MAP_COLOUR_SHIFT (0)
366#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
367#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
368
369#define WPALCON_PAL_UPDATE (1 << 9)
370#define WPALCON_W1PAL_MASK (0x7 << 3)
371#define WPALCON_W1PAL_SHIFT (3)
372#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
373#define WPALCON_W1PAL_24BPP (0x1 << 3)
374#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
375#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
376#define WPALCON_W1PAL_18BPP (0x4 << 3)
377#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
378#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
379
380#define WPALCON_W0PAL_MASK (0x7 << 0)
381#define WPALCON_W0PAL_SHIFT (0)
382#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
383#define WPALCON_W0PAL_24BPP (0x1 << 0)
384#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
385#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
386#define WPALCON_W0PAL_18BPP (0x4 << 0)
387#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
388#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
389
390/* Blending equation control */
391#define BLENDCON (0x260)
392#define BLENDCON_NEW_MASK (1 << 0)
393#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
394#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
395
396#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
397#define VIDCON1_FSTATUS_EVEN (1 << 15)
398
399/* Video timing controls */
400#define VIDTCON0 (0x10)
401#define VIDTCON1 (0x14)
402#define VIDTCON2 (0x18)
403
404/* Window position controls */
405
406#define WINCON(_win) (0x20 + ((_win) * 4))
407
408/* OSD1 and OSD4 do not have register D */
409
410#define VIDOSD_BASE (0x40)
411
412#define VIDINTCON0 (0x130)
413
414/* WINCONx */
415
416#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
417#define WINCONx_CSCWIDTH_SHIFT (26)
418#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
419#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
420
421#define WINCONx_ENLOCAL (1 << 22)
422#define WINCONx_BUFSTATUS (1 << 21)
423#define WINCONx_BUFSEL (1 << 20)
424#define WINCONx_BUFAUTOEN (1 << 19)
425#define WINCONx_YCbCr (1 << 13)
426
427#define WINCON1_LOCALSEL_CAMIF (1 << 23)
428
429#define WINCON2_LOCALSEL_CAMIF (1 << 23)
430#define WINCON2_BLD_PIX (1 << 6)
431
432#define WINCON2_ALPHA_SEL (1 << 1)
433#define WINCON2_BPPMODE_MASK (0xf << 2)
434#define WINCON2_BPPMODE_SHIFT (2)
435#define WINCON2_BPPMODE_1BPP (0x0 << 2)
436#define WINCON2_BPPMODE_2BPP (0x1 << 2)
437#define WINCON2_BPPMODE_4BPP (0x2 << 2)
438#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
439#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
440#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
441#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
442#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
443#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
444#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
445#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
446#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
447#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
448#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
449
450#define WINCON3_BLD_PIX (1 << 6)
451
452#define WINCON3_ALPHA_SEL (1 << 1)
453#define WINCON3_BPPMODE_MASK (0xf << 2)
454#define WINCON3_BPPMODE_SHIFT (2)
455#define WINCON3_BPPMODE_1BPP (0x0 << 2)
456#define WINCON3_BPPMODE_2BPP (0x1 << 2)
457#define WINCON3_BPPMODE_4BPP (0x2 << 2)
458#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
459#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
460#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
461#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
462#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
463#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
464#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
465#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
466#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
467#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
468
469#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
470#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
471#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
472
473#define DITHMODE (0x170)
474#define WINxMAP(_win) (0x180 + ((_win) * 4))
475
476
477#define DITHMODE_R_POS_MASK (0x3 << 5)
478#define DITHMODE_R_POS_SHIFT (5)
479#define DITHMODE_R_POS_8BIT (0x0 << 5)
480#define DITHMODE_R_POS_6BIT (0x1 << 5)
481#define DITHMODE_R_POS_5BIT (0x2 << 5)
482
483#define DITHMODE_G_POS_MASK (0x3 << 3)
484#define DITHMODE_G_POS_SHIFT (3)
485#define DITHMODE_G_POS_8BIT (0x0 << 3)
486#define DITHMODE_G_POS_6BIT (0x1 << 3)
487#define DITHMODE_G_POS_5BIT (0x2 << 3)
488
489#define DITHMODE_B_POS_MASK (0x3 << 1)
490#define DITHMODE_B_POS_SHIFT (1)
491#define DITHMODE_B_POS_8BIT (0x0 << 1)
492#define DITHMODE_B_POS_6BIT (0x1 << 1)
493#define DITHMODE_B_POS_5BIT (0x2 << 1)
494
495#define DITHMODE_DITH_EN (1 << 0)
496
497#define WPALCON (0x1A0)
498
499/* Palette control */
500/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
501 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
502#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
503#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
504#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
505
506
507/* Notes on per-window bpp settings
508 *
509 * Value Win0 Win1 Win2 Win3 Win 4
510 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
511 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
512 * 0010 4(P) 4(P) 4(P) 4(P) -none-
513 * 0011 8(P) 8(P) -none- -none- -none-
514 * 0100 -none- 8(A232) 8(A232) -none- -none-
515 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
516 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
517 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
518 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
519 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
520 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
521 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
522 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
523 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
524 * 1110 -none- -none- -none- -none- -none-
525 * 1111 -none- -none- -none- -none- -none-
526*/
527
528/* FIMD Version 8 register offset definitions */
529#define FIMD_V8_VIDTCON0 (0x20010)
530#define FIMD_V8_VIDTCON1 (0x20014)
531#define FIMD_V8_VIDTCON2 (0x20018)
532#define FIMD_V8_VIDTCON3 (0x2001C)
533#define FIMD_V8_VIDCON1 (0x20004)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 07:06:31 -0500