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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-17 14:41:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-17 14:41:49 -0400
commit55a6fbf8fc57d7b60d5028663f534475c4965215 (patch)
treefbe6b7ef5251d11b60c72d5d07d03312b6c22d44 /include
parent3fe0344faf7fdcb158bd5c1a9aec960a8d70c8e8 (diff)
parent2021de874e9f09774616772cfdefdab0e6193b09 (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: mfd: early init for MFD running regulators mfd: fix tmio related warnings mfd: asic3: enable SD/SDIO cell mfd: asic3: enable DS1WM cell mfd: asic3: remove SD/SDIO controller register definitions mfd: asic3: use resource_size macro instead of local variable mfd: add ASIC3 IRQ numbers mfd: asic3: add clock handling for MFD cells mfd: asic3: add asic3_set_register common operation mfd: Fix Kconfig help text for WM8350 mfd: add PCAP driver mfd: add U300 AB3100 core support drivers/mfd: remove obsolete irq_desc_t typedef mfd/pcf50633-gpio.c: add MODULE_LICENSE mfd: Mark WM8350 mask revision as readable to match silicon mfd: Mark clocks_init as non-init in twl4030-core.c mfd: Correct readability of WM8350 register 227
Diffstat (limited to 'include')
-rw-r--r--include/linux/mfd/ab3100.h103
-rw-r--r--include/linux/mfd/asic3.h236
-rw-r--r--include/linux/mfd/ezx-pcap.h256
-rw-r--r--include/linux/mfd/tmio.h2
4 files changed, 375 insertions, 222 deletions
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
new file mode 100644
index 000000000000..7a3f316e3848
--- /dev/null
+++ b/include/linux/mfd/ab3100.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2007-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * AB3100 core access functions
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 */
7
8#include <linux/device.h>
9
10#ifndef MFD_AB3100_H
11#define MFD_AB3100_H
12
13#define ABUNKNOWN 0
14#define AB3000 1
15#define AB3100 2
16
17/*
18 * AB3100, EVENTA1, A2 and A3 event register flags
19 * these are catenated into a single 32-bit flag in the code
20 * for event notification broadcasts.
21 */
22#define AB3100_EVENTA1_ONSWA (0x01<<16)
23#define AB3100_EVENTA1_ONSWB (0x02<<16)
24#define AB3100_EVENTA1_ONSWC (0x04<<16)
25#define AB3100_EVENTA1_DCIO (0x08<<16)
26#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
27#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
28#define AB3100_EVENTA1_VBUS (0x40<<16)
29#define AB3100_EVENTA1_VSET_USB (0x80<<16)
30
31#define AB3100_EVENTA2_READY_TX (0x01<<8)
32#define AB3100_EVENTA2_READY_RX (0x02<<8)
33#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
34#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
35#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
36#define AB3100_EVENTA2_MIDR (0x20<<8)
37#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
38#define AB3100_EVENTA2_ALARM (0x80<<8)
39
40#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
41#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
42#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
43#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
44#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
45#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
46#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
47#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
48
49/* AB3100, STR register flags */
50#define AB3100_STR_ONSWA (0x01)
51#define AB3100_STR_ONSWB (0x02)
52#define AB3100_STR_ONSWC (0x04)
53#define AB3100_STR_DCIO (0x08)
54#define AB3100_STR_BOOT_MODE (0x10)
55#define AB3100_STR_SIM_OFF (0x20)
56#define AB3100_STR_BATT_REMOVAL (0x40)
57#define AB3100_STR_VBUS (0x80)
58
59/**
60 * struct ab3100
61 * @access_mutex: lock out concurrent accesses to the AB3100 registers
62 * @dev: pointer to the containing device
63 * @i2c_client: I2C client for this chip
64 * @testreg_client: secondary client for test registers
65 * @chip_name: name of this chip variant
66 * @chip_id: 8 bit chip ID for this chip variant
67 * @work: an event handling worker
68 * @event_subscribers: event subscribers are listed here
69 * @startup_events: a copy of the first reading of the event registers
70 * @startup_events_read: whether the first events have been read
71 *
72 * This struct is PRIVATE and devices using it should NOT
73 * access ANY fields. It is used as a token for calling the
74 * AB3100 functions.
75 */
76struct ab3100 {
77 struct mutex access_mutex;
78 struct device *dev;
79 struct i2c_client *i2c_client;
80 struct i2c_client *testreg_client;
81 char chip_name[32];
82 u8 chip_id;
83 struct work_struct work;
84 struct blocking_notifier_head event_subscribers;
85 u32 startup_events;
86 bool startup_events_read;
87};
88
89int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval);
90int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval);
91int ab3100_get_register_page(struct ab3100 *ab3100,
92 u8 first_reg, u8 *regvals, u8 numregs);
93int ab3100_mask_and_set_register(struct ab3100 *ab3100,
94 u8 reg, u8 andmask, u8 ormask);
95u8 ab3100_get_chip_type(struct ab3100 *ab3100);
96int ab3100_event_register(struct ab3100 *ab3100,
97 struct notifier_block *nb);
98int ab3100_event_unregister(struct ab3100 *ab3100,
99 struct notifier_block *nb);
100int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
101 u32 *fatevent);
102
103#endif
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index 322cd6deb9f0..de3c4ad19afb 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -30,6 +30,13 @@ struct asic3_platform_data {
30#define ASIC3_NUM_GPIOS 64 30#define ASIC3_NUM_GPIOS 64
31#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 31#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
32 32
33#define ASIC3_IRQ_LED0 64
34#define ASIC3_IRQ_LED1 65
35#define ASIC3_IRQ_LED2 66
36#define ASIC3_IRQ_SPI 67
37#define ASIC3_IRQ_SMBUS 68
38#define ASIC3_IRQ_OWM 69
39
33#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio)) 40#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
34 41
35#define ASIC3_GPIO_BANK_A 0 42#define ASIC3_GPIO_BANK_A 0
@@ -227,8 +234,8 @@ struct asic3_platform_data {
227 234
228 235
229/* Basic control of the SD ASIC */ 236/* Basic control of the SD ASIC */
230#define ASIC3_SDHWCTRL_Base 0x0E00 237#define ASIC3_SDHWCTRL_BASE 0x0E00
231#define ASIC3_SDHWCTRL_SDConf 0x00 238#define ASIC3_SDHWCTRL_SDCONF 0x00
232 239
233#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */ 240#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
234#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */ 241#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
@@ -242,10 +249,10 @@ struct asic3_platform_data {
242/* SD card power supply ctrl 1=enable */ 249/* SD card power supply ctrl 1=enable */
243#define ASIC3_SDHWCTRL_SDPWR (1 << 6) 250#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
244 251
245#define ASIC3_EXTCF_Base 0x1100 252#define ASIC3_EXTCF_BASE 0x1100
246 253
247#define ASIC3_EXTCF_Select 0x00 254#define ASIC3_EXTCF_SELECT 0x00
248#define ASIC3_EXTCF_Reset 0x04 255#define ASIC3_EXTCF_RESET 0x04
249 256
250#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */ 257#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
251#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */ 258#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
@@ -279,222 +286,9 @@ struct asic3_platform_data {
279 * SDIO_CTRL Control registers for SDIO operations 286 * SDIO_CTRL Control registers for SDIO operations
280 * 287 *
281 *****************************************************************************/ 288 *****************************************************************************/
282#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */ 289#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
283 290#define ASIC3_SD_CTRL_BASE 0x1000
284#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */ 291#define ASIC3_SDIO_CTRL_BASE 0x1200
285
286/* [0:8] SD Control Register Base Address */
287#define ASIC3_SD_CONFIG_Addr0 0x20
288
289/* [9:31] SD Control Register Base Address */
290#define ASIC3_SD_CONFIG_Addr1 0x24
291
292/* R/O: interrupt assigned to pin */
293#define ASIC3_SD_CONFIG_IntPin 0x78
294
295/*
296 * Set to 0x1f to clock SD controller, 0 otherwise.
297 * At 0x82 - Gated Clock Ctrl
298 */
299#define ASIC3_SD_CONFIG_ClkStop 0x80
300
301/* Control clock of SD controller */
302#define ASIC3_SD_CONFIG_ClockMode 0x84
303#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
304#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
305
306/* auto power up after card inserted */
307#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
308
309/* auto power down when card removed */
310#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
311#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
312#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
313#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
314#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
315
316/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
317#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
318#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
319
320/* Bit 1: double buffer/single buffer */
321#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
322
323/* Memory access enable (set to 1 to access SD Controller) */
324#define SD_CONFIG_COMMAND_MAE (1<<1)
325
326#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
327
328#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
329#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
330
331 /* two bits - number of cycles for card detection */
332#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
333
334
335#define ASIC3_SD_CTRL_Base 0x1000
336
337#define ASIC3_SD_CTRL_Cmd 0x00
338#define ASIC3_SD_CTRL_Arg0 0x08
339#define ASIC3_SD_CTRL_Arg1 0x0C
340#define ASIC3_SD_CTRL_StopInternal 0x10
341#define ASIC3_SD_CTRL_TransferSectorCount 0x14
342#define ASIC3_SD_CTRL_Response0 0x18
343#define ASIC3_SD_CTRL_Response1 0x1C
344#define ASIC3_SD_CTRL_Response2 0x20
345#define ASIC3_SD_CTRL_Response3 0x24
346#define ASIC3_SD_CTRL_Response4 0x28
347#define ASIC3_SD_CTRL_Response5 0x2C
348#define ASIC3_SD_CTRL_Response6 0x30
349#define ASIC3_SD_CTRL_Response7 0x34
350#define ASIC3_SD_CTRL_CardStatus 0x38
351#define ASIC3_SD_CTRL_BufferCtrl 0x3C
352#define ASIC3_SD_CTRL_IntMaskCard 0x40
353#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
354#define ASIC3_SD_CTRL_CardClockCtrl 0x48
355#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
356#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
357#define ASIC3_SD_CTRL_ErrorStatus0 0x58
358#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
359#define ASIC3_SD_CTRL_DataPort 0x60
360#define ASIC3_SD_CTRL_TransactionCtrl 0x68
361#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
362
363#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
364
365#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
366
367#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
368#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
369#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
370#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
371#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
372#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
373#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
374#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
375#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
376#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
377#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
378
379#define MEM_CARD_OPTION_REQUIRED 0x000e
380#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
381#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
382#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
383#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
384
385#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
386#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
387#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
388#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
389#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
390#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
391#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
392#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
393#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
394#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
395#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
396#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
397#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
398#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
399
400#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
401#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
402
403#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
404#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
405#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
406#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
407#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
408#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
409#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
410#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
411#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
412
413#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
414#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
415#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
416#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
417#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
418#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
419#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
420#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
421#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
422#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
423#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
424#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
425#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
426
427#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
428#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
429#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
430#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
431#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
432#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
433#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
434#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
435#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
436#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
437
438#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
439#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
440#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
441#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
442#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
443#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
444#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
445#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
446#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
447#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
448#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
449#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
450#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
451
452#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
453#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
454#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
455#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
456#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
457#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
458#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
459#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
460#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
461
462#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
463#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
464#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
465#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
466
467#define ASIC3_SDIO_CTRL_Base 0x1200
468
469#define ASIC3_SDIO_CTRL_Cmd 0x00
470#define ASIC3_SDIO_CTRL_CardPortSel 0x04
471#define ASIC3_SDIO_CTRL_Arg0 0x08
472#define ASIC3_SDIO_CTRL_Arg1 0x0C
473#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
474#define ASIC3_SDIO_CTRL_Response0 0x18
475#define ASIC3_SDIO_CTRL_Response1 0x1C
476#define ASIC3_SDIO_CTRL_Response2 0x20
477#define ASIC3_SDIO_CTRL_Response3 0x24
478#define ASIC3_SDIO_CTRL_Response4 0x28
479#define ASIC3_SDIO_CTRL_Response5 0x2C
480#define ASIC3_SDIO_CTRL_Response6 0x30
481#define ASIC3_SDIO_CTRL_Response7 0x34
482#define ASIC3_SDIO_CTRL_CardStatus 0x38
483#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
484#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
485#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
486#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
487#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
488#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
489#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
490#define ASIC3_SDIO_CTRL_DataPort 0x60
491#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
492#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
493#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
494#define ASIC3_SDIO_CTRL_HostInformation 0x74
495#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
496#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
497#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
498 292
499#define ASIC3_MAP_SIZE_32BIT 0x2000 293#define ASIC3_MAP_SIZE_32BIT 0x2000
500#define ASIC3_MAP_SIZE_16BIT 0x1000 294#define ASIC3_MAP_SIZE_16BIT 0x1000
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
new file mode 100644
index 000000000000..c12c3c0932bf
--- /dev/null
+++ b/include/linux/mfd/ezx-pcap.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
3 *
4 * For further information, please see http://wiki.openezx.org/PCAP2
5 */
6
7#ifndef EZX_PCAP_H
8#define EZX_PCAP_H
9
10struct pcap_subdev {
11 int id;
12 const char *name;
13 void *platform_data;
14};
15
16struct pcap_platform_data {
17 unsigned int irq_base;
18 unsigned int config;
19 void (*init) (void *); /* board specific init */
20 int num_subdevs;
21 struct pcap_subdev *subdevs;
22};
23
24struct pcap_chip;
25
26int ezx_pcap_write(struct pcap_chip *, u8, u32);
27int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
28int pcap_to_irq(struct pcap_chip *, int);
29int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
30int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
31
32#define PCAP_SECOND_PORT 1
33#define PCAP_CS_AH 2
34
35#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
36#define PCAP_REGISTER_READ_OP_BIT 0x00000000
37
38#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
39#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
40#define PCAP_REGISTER_ADDRESS_SHIFT 26
41#define PCAP_REGISTER_NUMBER 32
42#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
43#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
44
45/* registers acessible by both pcap ports */
46#define PCAP_REG_ISR 0x0 /* Interrupt Status */
47#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
48#define PCAP_REG_PSTAT 0x2 /* Processor Status */
49#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
50#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
51#define PCAP_REG_BATT 0x8 /* Battery Control */
52#define PCAP_REG_ADC 0x9 /* AD Control */
53#define PCAP_REG_ADR 0xa /* AD Result */
54#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
55#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
56#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
57#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
58#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
59#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
60#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
61#define PCAP_REG_GP 0x1b /* General Purpose */
62#define PCAP_REG_TEST1 0x1c
63#define PCAP_REG_TEST2 0x1d
64#define PCAP_REG_VENDOR_TEST1 0x1e
65#define PCAP_REG_VENDOR_TEST2 0x1f
66
67/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
68#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
69#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
70#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
71#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
72#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
73#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
74#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
75#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
76#define PCAP_REG_PWR 0x13 /* Power Control */
77#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
78#define PCAP_REG_VENDOR_REV 0x17
79#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
80
81/* PCAP2 Interrupts */
82#define PCAP_NIRQS 23
83#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
84#define PCAP_IRQ_TS 1 /* Touch Screen */
85#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
86#define PCAP_IRQ_WH 3 /* ADC above high limit */
87#define PCAP_IRQ_WL 4 /* ADC below low limit */
88#define PCAP_IRQ_TODA 5 /* Time of day alarm */
89#define PCAP_IRQ_USB4V 6 /* USB above 4V */
90#define PCAP_IRQ_ONOFF 7 /* On/Off button */
91#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
92#define PCAP_IRQ_USB1V 9 /* USB above 1V */
93#define PCAP_IRQ_MOBPORT 10
94#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
95#define PCAP_IRQ_HS 12 /* Headset attach */
96#define PCAP_IRQ_ST 13
97#define PCAP_IRQ_PC 14 /* Power Cut */
98#define PCAP_IRQ_WARM 15
99#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
100#define PCAP_IRQ_CLK 17
101#define PCAP_IRQ_SYSRST 18 /* System Reset */
102#define PCAP_IRQ_DUMMY 19
103#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
104#define PCAP_IRQ_SOFTRESET 21
105#define PCAP_IRQ_MNEXB 22
106
107/* voltage regulators */
108#define V1 0
109#define V2 1
110#define V3 2
111#define V4 3
112#define V5 4
113#define V6 5
114#define V7 6
115#define V8 7
116#define V9 8
117#define V10 9
118#define VAUX1 10
119#define VAUX2 11
120#define VAUX3 12
121#define VAUX4 13
122#define VSIM 14
123#define VSIM2 15
124#define VVIB 16
125#define SW1 17
126#define SW2 18
127#define SW3 19
128#define SW1S 20
129#define SW2S 21
130
131#define PCAP_BATT_DAC_MASK 0x000000ff
132#define PCAP_BATT_DAC_SHIFT 0
133#define PCAP_BATT_B_FDBK (1 << 8)
134#define PCAP_BATT_EXT_ISENSE (1 << 9)
135#define PCAP_BATT_V_COIN_MASK 0x00003c00
136#define PCAP_BATT_V_COIN_SHIFT 10
137#define PCAP_BATT_I_COIN (1 << 14)
138#define PCAP_BATT_COIN_CH_EN (1 << 15)
139#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
140#define PCAP_BATT_EOL_SEL_SHIFT 17
141#define PCAP_BATT_EOL_CMP_EN (1 << 20)
142#define PCAP_BATT_BATT_DET_EN (1 << 21)
143#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
144
145#define PCAP_ADC_ADEN (1 << 0)
146#define PCAP_ADC_RAND (1 << 1)
147#define PCAP_ADC_AD_SEL1 (1 << 2)
148#define PCAP_ADC_AD_SEL2 (1 << 3)
149#define PCAP_ADC_ADA1_MASK 0x00000070
150#define PCAP_ADC_ADA1_SHIFT 4
151#define PCAP_ADC_ADA2_MASK 0x00000380
152#define PCAP_ADC_ADA2_SHIFT 7
153#define PCAP_ADC_ATO_MASK 0x00003c00
154#define PCAP_ADC_ATO_SHIFT 10
155#define PCAP_ADC_ATOX (1 << 14)
156#define PCAP_ADC_MTR1 (1 << 15)
157#define PCAP_ADC_MTR2 (1 << 16)
158#define PCAP_ADC_TS_M_MASK 0x000e0000
159#define PCAP_ADC_TS_M_SHIFT 17
160#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
161#define PCAP_ADC_TS_REFENB (1 << 21)
162#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
163#define PCAP_ADC_BATT_I_ADC (1 << 23)
164
165#define PCAP_ADC_BANK_0 0
166#define PCAP_ADC_BANK_1 1
167/* ADC bank 0 */
168#define PCAP_ADC_CH_COIN 0
169#define PCAP_ADC_CH_BATT 1
170#define PCAP_ADC_CH_BPLUS 2
171#define PCAP_ADC_CH_MOBPORTB 3
172#define PCAP_ADC_CH_TEMPERATURE 4
173#define PCAP_ADC_CH_CHARGER_ID 5
174#define PCAP_ADC_CH_AD6 6
175/* ADC bank 1 */
176#define PCAP_ADC_CH_AD7 0
177#define PCAP_ADC_CH_AD8 1
178#define PCAP_ADC_CH_AD9 2
179#define PCAP_ADC_CH_TS_X1 3
180#define PCAP_ADC_CH_TS_X2 4
181#define PCAP_ADC_CH_TS_Y1 5
182#define PCAP_ADC_CH_TS_Y2 6
183
184#define PCAP_ADC_T_NOW 0
185#define PCAP_ADC_T_IN_BURST 1
186#define PCAP_ADC_T_OUT_BURST 2
187
188#define PCAP_ADC_ATO_IN_BURST 6
189#define PCAP_ADC_ATO_OUT_BURST 0
190
191#define PCAP_ADC_TS_M_XY 1
192#define PCAP_ADC_TS_M_PRESSURE 2
193#define PCAP_ADC_TS_M_PLATE_X 3
194#define PCAP_ADC_TS_M_PLATE_Y 4
195#define PCAP_ADC_TS_M_STANDBY 5
196#define PCAP_ADC_TS_M_NONTS 6
197
198#define PCAP_ADR_ADD1_MASK 0x000003ff
199#define PCAP_ADR_ADD1_SHIFT 0
200#define PCAP_ADR_ADD2_MASK 0x000ffc00
201#define PCAP_ADR_ADD2_SHIFT 10
202#define PCAP_ADR_ADINC1 (1 << 20)
203#define PCAP_ADR_ADINC2 (1 << 21)
204#define PCAP_ADR_ASC (1 << 22)
205#define PCAP_ADR_ONESHOT (1 << 23)
206
207#define PCAP_BUSCTRL_FSENB (1 << 0)
208#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
209#define PCAP_BUSCTRL_USB_PU (1 << 2)
210#define PCAP_BUSCTRL_USB_PD (1 << 3)
211#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
212#define PCAP_BUSCTRL_USB_PS (1 << 5)
213#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
214#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
215#define PCAP_BUSCTRL_CURRLIM (1 << 8)
216#define PCAP_BUSCTRL_RS232ENB (1 << 9)
217#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
218#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
219#define PCAP_BUSCTRL_USB_PDM (1 << 12)
220#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
221
222/* leds */
223#define PCAP_LED0 0
224#define PCAP_LED1 1
225#define PCAP_BL0 2
226#define PCAP_BL1 3
227#define PCAP_VIB 4
228#define PCAP_LED_3MA 0
229#define PCAP_LED_4MA 1
230#define PCAP_LED_5MA 2
231#define PCAP_LED_9MA 3
232#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
233#define PCAP_LED_GPIO_EN 0x01000000
234#define PCAP_LED_GPIO_INVERT 0x02000000
235#define PCAP_LED_T_MASK 0xf
236#define PCAP_LED_C_MASK 0x3
237#define PCAP_BL_MASK 0x1f
238#define PCAP_BL0_SHIFT 0
239#define PCAP_LED0_EN (1 << 5)
240#define PCAP_LED1_EN (1 << 6)
241#define PCAP_LED0_T_SHIFT 7
242#define PCAP_LED1_T_SHIFT 11
243#define PCAP_LED0_C_SHIFT 15
244#define PCAP_LED1_C_SHIFT 17
245#define PCAP_BL1_SHIFT 20
246#define PCAP_VIB_MASK 0x3
247#define PCAP_VIB_SHIFT 20
248#define PCAP_VIB_EN (1 << 19)
249
250/* RTC */
251#define PCAP_RTC_DAY_MASK 0x3fff
252#define PCAP_RTC_TOD_MASK 0xffff
253#define PCAP_RTC_PC_MASK 0x7
254#define SEC_PER_DAY 86400
255
256#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index c377118884e6..6b9c5d06690c 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -22,7 +22,7 @@
22 * data for the MMC controller 22 * data for the MMC controller
23 */ 23 */
24struct tmio_mmc_data { 24struct tmio_mmc_data {
25 unsigned int hclk; 25 const unsigned int hclk;
26}; 26};
27 27
28/* 28/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 20:37:28 -0400