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authorMichael Turquette <mturquette@linaro.org>2015-02-02 17:59:38 -0500
committerMichael Turquette <mturquette@linaro.org>2015-02-02 17:59:38 -0500
commit54eea32f7ed3037c91853924227585b65df909a8 (patch)
tree4e3e9ece8a66f611e980ddc503ca7184db8f83fb /include
parente36f014edff70fc02b3d3d79cead1d58f289332e (diff)
parentb530e7d2108a871279dcf707d9d15a3358767d2b (diff)
Merge branch 'clk-next' into v3.19-rc7
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/alphascale,asm9260.h97
-rw-r--r--include/dt-bindings/clock/exynos4.h7
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h88
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h1
-rw-r--r--include/dt-bindings/clock/qcom,lcc-ipq806x.h30
-rw-r--r--include/dt-bindings/clock/qcom,lcc-msm8960.h50
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h4
-rw-r--r--include/linux/clk-private.h220
-rw-r--r--include/linux/clk-provider.h52
-rw-r--r--include/linux/clk.h45
-rw-r--r--include/linux/clk/sunxi.h22
-rw-r--r--include/linux/clk/ti.h17
12 files changed, 376 insertions, 257 deletions
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000000..04e8db27daf0
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_ASM9260_H
15#define _DT_BINDINGS_CLK_ASM9260_H
16
17/* ahb gate */
18#define CLKID_AHB_ROM 0
19#define CLKID_AHB_RAM 1
20#define CLKID_AHB_GPIO 2
21#define CLKID_AHB_MAC 3
22#define CLKID_AHB_EMI 4
23#define CLKID_AHB_USB0 5
24#define CLKID_AHB_USB1 6
25#define CLKID_AHB_DMA0 7
26#define CLKID_AHB_DMA1 8
27#define CLKID_AHB_UART0 9
28#define CLKID_AHB_UART1 10
29#define CLKID_AHB_UART2 11
30#define CLKID_AHB_UART3 12
31#define CLKID_AHB_UART4 13
32#define CLKID_AHB_UART5 14
33#define CLKID_AHB_UART6 15
34#define CLKID_AHB_UART7 16
35#define CLKID_AHB_UART8 17
36#define CLKID_AHB_UART9 18
37#define CLKID_AHB_I2S0 19
38#define CLKID_AHB_I2C0 20
39#define CLKID_AHB_I2C1 21
40#define CLKID_AHB_SSP0 22
41#define CLKID_AHB_IOCONFIG 23
42#define CLKID_AHB_WDT 24
43#define CLKID_AHB_CAN0 25
44#define CLKID_AHB_CAN1 26
45#define CLKID_AHB_MPWM 27
46#define CLKID_AHB_SPI0 28
47#define CLKID_AHB_SPI1 29
48#define CLKID_AHB_QEI 30
49#define CLKID_AHB_QUADSPI0 31
50#define CLKID_AHB_CAMIF 32
51#define CLKID_AHB_LCDIF 33
52#define CLKID_AHB_TIMER0 34
53#define CLKID_AHB_TIMER1 35
54#define CLKID_AHB_TIMER2 36
55#define CLKID_AHB_TIMER3 37
56#define CLKID_AHB_IRQ 38
57#define CLKID_AHB_RTC 39
58#define CLKID_AHB_NAND 40
59#define CLKID_AHB_ADC0 41
60#define CLKID_AHB_LED 42
61#define CLKID_AHB_DAC0 43
62#define CLKID_AHB_LCD 44
63#define CLKID_AHB_I2S1 45
64#define CLKID_AHB_MAC1 46
65
66/* devider */
67#define CLKID_SYS_CPU 47
68#define CLKID_SYS_AHB 48
69#define CLKID_SYS_I2S0M 49
70#define CLKID_SYS_I2S0S 50
71#define CLKID_SYS_I2S1M 51
72#define CLKID_SYS_I2S1S 52
73#define CLKID_SYS_UART0 53
74#define CLKID_SYS_UART1 54
75#define CLKID_SYS_UART2 55
76#define CLKID_SYS_UART3 56
77#define CLKID_SYS_UART4 56
78#define CLKID_SYS_UART5 57
79#define CLKID_SYS_UART6 58
80#define CLKID_SYS_UART7 59
81#define CLKID_SYS_UART8 60
82#define CLKID_SYS_UART9 61
83#define CLKID_SYS_SPI0 62
84#define CLKID_SYS_SPI1 63
85#define CLKID_SYS_QUADSPI 64
86#define CLKID_SYS_SSP0 65
87#define CLKID_SYS_NAND 66
88#define CLKID_SYS_TRACE 67
89#define CLKID_SYS_CAMM 68
90#define CLKID_SYS_WDT 69
91#define CLKID_SYS_CLKOUT 70
92#define CLKID_SYS_MAC 71
93#define CLKID_SYS_LCD 72
94#define CLKID_SYS_ADCANA 73
95
96#define MAX_CLKS 74
97#endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c622d0..c4b1676ea674 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
265#define CLK_DIV_ACP 456
266#define CLK_DIV_DMC 457
267#define CLK_DIV_C2C 458 /* Exynos4x12 only */
268#define CLK_DIV_GDL 459
269#define CLK_DIV_GDR 460
265 270
266/* must be greater than maximal clock id */ 271/* must be greater than maximal clock id */
267#define CLK_NR_CLKS 456 272#define CLK_NR_CLKS 461
268 273
269#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 274#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
17#define DOUT_SCLK_CC_PLL 4 17#define DOUT_SCLK_CC_PLL 4
18#define DOUT_SCLK_MFC_PLL 5 18#define DOUT_SCLK_MFC_PLL 5
19#define DOUT_ACLK_CCORE_133 6 19#define DOUT_ACLK_CCORE_133 6
20#define TOPC_NR_CLK 7 20#define DOUT_ACLK_MSCL_532 7
21#define ACLK_MSCL_532 8
22#define DOUT_SCLK_AUD_PLL 9
23#define FOUT_AUD_PLL 10
24#define TOPC_NR_CLK 11
21 25
22/* TOP0 */ 26/* TOP0 */
23#define DOUT_ACLK_PERIC1 1 27#define DOUT_ACLK_PERIC1 1
@@ -26,7 +30,15 @@
26#define CLK_SCLK_UART1 4 30#define CLK_SCLK_UART1 4
27#define CLK_SCLK_UART2 5 31#define CLK_SCLK_UART2 5
28#define CLK_SCLK_UART3 6 32#define CLK_SCLK_UART3 6
29#define TOP0_NR_CLK 7 33#define CLK_SCLK_SPI0 7
34#define CLK_SCLK_SPI1 8
35#define CLK_SCLK_SPI2 9
36#define CLK_SCLK_SPI3 10
37#define CLK_SCLK_SPI4 11
38#define CLK_SCLK_SPDIF 12
39#define CLK_SCLK_PCM1 13
40#define CLK_SCLK_I2S1 14
41#define TOP0_NR_CLK 15
30 42
31/* TOP1 */ 43/* TOP1 */
32#define DOUT_ACLK_FSYS1_200 1 44#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +82,23 @@
70#define PCLK_HSI2C6 9 82#define PCLK_HSI2C6 9
71#define PCLK_HSI2C7 10 83#define PCLK_HSI2C7 10
72#define PCLK_HSI2C8 11 84#define PCLK_HSI2C8 11
73#define PERIC1_NR_CLK 12 85#define PCLK_SPI0 12
86#define PCLK_SPI1 13
87#define PCLK_SPI2 14
88#define PCLK_SPI3 15
89#define PCLK_SPI4 16
90#define SCLK_SPI0 17
91#define SCLK_SPI1 18
92#define SCLK_SPI2 19
93#define SCLK_SPI3 20
94#define SCLK_SPI4 21
95#define PCLK_I2S1 22
96#define PCLK_PCM1 23
97#define PCLK_SPDIF 24
98#define SCLK_I2S1 25
99#define SCLK_PCM1 26
100#define SCLK_SPDIF 27
101#define PERIC1_NR_CLK 28
74 102
75/* PERIS */ 103/* PERIS */
76#define PCLK_CHIPID 1 104#define PCLK_CHIPID 1
@@ -82,11 +110,63 @@
82 110
83/* FSYS0 */ 111/* FSYS0 */
84#define ACLK_MMC2 1 112#define ACLK_MMC2 1
85#define FSYS0_NR_CLK 2 113#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
114#define ACLK_USBDRD300 3
115#define SCLK_USBDRD300_SUSPENDCLK 4
116#define SCLK_USBDRD300_REFCLK 5
117#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
118#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
119#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
120#define ACLK_PDMA0 9
121#define ACLK_PDMA1 10
122#define FSYS0_NR_CLK 11
86 123
87/* FSYS1 */ 124/* FSYS1 */
88#define ACLK_MMC1 1 125#define ACLK_MMC1 1
89#define ACLK_MMC0 2 126#define ACLK_MMC0 2
90#define FSYS1_NR_CLK 3 127#define FSYS1_NR_CLK 3
91 128
129/* MSCL */
130#define USERMUX_ACLK_MSCL_532 1
131#define DOUT_PCLK_MSCL 2
132#define ACLK_MSCL_0 3
133#define ACLK_MSCL_1 4
134#define ACLK_JPEG 5
135#define ACLK_G2D 6
136#define ACLK_LH_ASYNC_SI_MSCL_0 7
137#define ACLK_LH_ASYNC_SI_MSCL_1 8
138#define ACLK_AXI2ACEL_BRIDGE 9
139#define ACLK_XIU_MSCLX_0 10
140#define ACLK_XIU_MSCLX_1 11
141#define ACLK_QE_MSCL_0 12
142#define ACLK_QE_MSCL_1 13
143#define ACLK_QE_JPEG 14
144#define ACLK_QE_G2D 15
145#define ACLK_PPMU_MSCL_0 16
146#define ACLK_PPMU_MSCL_1 17
147#define ACLK_MSCLNP_133 18
148#define ACLK_AHB2APB_MSCL0P 19
149#define ACLK_AHB2APB_MSCL1P 20
150
151#define PCLK_MSCL_0 21
152#define PCLK_MSCL_1 22
153#define PCLK_JPEG 23
154#define PCLK_G2D 24
155#define PCLK_QE_MSCL_0 25
156#define PCLK_QE_MSCL_1 26
157#define PCLK_QE_JPEG 27
158#define PCLK_QE_G2D 28
159#define PCLK_PPMU_MSCL_0 29
160#define PCLK_PPMU_MSCL_1 30
161#define PCLK_AXI2ACEL_BRIDGE 31
162#define PCLK_PMU_MSCL 32
163#define MSCL_NR_CLK 33
164
165/* AUD */
166#define SCLK_I2S 1
167#define SCLK_PCM 2
168#define PCLK_I2S 3
169#define PCLK_PCM 4
170#define ACLK_ADMA 5
171#define AUD_NR_CLK 6
92#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 172#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cadb0bd4..04fb29ae30e6 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -238,7 +238,6 @@
238#define PLL0_VOTE 221 238#define PLL0_VOTE 221
239#define PLL3 222 239#define PLL3 222
240#define PLL3_VOTE 223 240#define PLL3_VOTE 223
241#define PLL4 224
242#define PLL4_VOTE 225 241#define PLL4_VOTE 225
243#define PLL8 226 242#define PLL8 226
244#define PLL8_VOTE 227 243#define PLL8_VOTE 227
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000000..4e944b85c56d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
15#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SPDIF_SRC 9
27#define SPDIF_CLK 10
28#define AHBIX_CLK 11
29
30#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000000..4fb2aa64d9fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
15#define _DT_BINDINGS_CLK_LCC_MSM8960_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SLIMBUS_SRC 9
27#define AUDIO_SLIMBUS_CLK 10
28#define SPS_SLIMBUS_CLK 11
29#define CODEC_I2S_MIC_OSR_SRC 12
30#define CODEC_I2S_MIC_OSR_CLK 13
31#define CODEC_I2S_MIC_DIV_CLK 14
32#define CODEC_I2S_MIC_BIT_DIV_CLK 15
33#define CODEC_I2S_MIC_BIT_CLK 16
34#define SPARE_I2S_MIC_OSR_SRC 17
35#define SPARE_I2S_MIC_OSR_CLK 18
36#define SPARE_I2S_MIC_DIV_CLK 19
37#define SPARE_I2S_MIC_BIT_DIV_CLK 20
38#define SPARE_I2S_MIC_BIT_CLK 21
39#define CODEC_I2S_SPKR_OSR_SRC 22
40#define CODEC_I2S_SPKR_OSR_CLK 23
41#define CODEC_I2S_SPKR_DIV_CLK 24
42#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
43#define CODEC_I2S_SPKR_BIT_CLK 26
44#define SPARE_I2S_SPKR_OSR_SRC 27
45#define SPARE_I2S_SPKR_OSR_CLK 28
46#define SPARE_I2S_SPKR_DIV_CLK 29
47#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
48#define SPARE_I2S_SPKR_BIT_CLK 31
49
50#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..1e626335acf3 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,9 @@
80#define SCLK_SDIO0_SAMPLE 119 80#define SCLK_SDIO0_SAMPLE 119
81#define SCLK_SDIO1_SAMPLE 120 81#define SCLK_SDIO1_SAMPLE 120
82#define SCLK_EMMC_SAMPLE 121 82#define SCLK_EMMC_SAMPLE 121
83#define SCLK_USBPHY480M_SRC 122
84#define SCLK_PVTM_CORE 123
85#define SCLK_PVTM_GPU 124
83 86
84#define DCLK_VOP0 190 87#define DCLK_VOP0 190
85#define DCLK_VOP1 191 88#define DCLK_VOP1 191
@@ -154,6 +157,7 @@
154#define PCLK_PUBL0 365 157#define PCLK_PUBL0 365
155#define PCLK_DDRUPCTL1 366 158#define PCLK_DDRUPCTL1 366
156#define PCLK_PUBL1 367 159#define PCLK_PUBL1 367
160#define PCLK_WDT 368
157 161
158/* hclk gates */ 162/* hclk gates */
159#define HCLK_GPS 448 163#define HCLK_GPS 448
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
deleted file mode 100644
index 0ca5f6046920..000000000000
--- a/include/linux/clk-private.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * linux/include/linux/clk-private.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __LINUX_CLK_PRIVATE_H
12#define __LINUX_CLK_PRIVATE_H
13
14#include <linux/clk-provider.h>
15#include <linux/kref.h>
16#include <linux/list.h>
17
18/*
19 * WARNING: Do not include clk-private.h from any file that implements struct
20 * clk_ops. Doing so is a layering violation!
21 *
22 * This header exists only to allow for statically initialized clock data. Any
23 * static clock data must be defined in a separate file from the logic that
24 * implements the clock operations for that same data.
25 */
26
27#ifdef CONFIG_COMMON_CLK
28
29struct module;
30
31struct clk {
32 const char *name;
33 const struct clk_ops *ops;
34 struct clk_hw *hw;
35 struct module *owner;
36 struct clk *parent;
37 const char **parent_names;
38 struct clk **parents;
39 u8 num_parents;
40 u8 new_parent_index;
41 unsigned long rate;
42 unsigned long new_rate;
43 struct clk *new_parent;
44 struct clk *new_child;
45 unsigned long flags;
46 unsigned int enable_count;
47 unsigned int prepare_count;
48 unsigned long accuracy;
49 int phase;
50 struct hlist_head children;
51 struct hlist_node child_node;
52 struct hlist_node debug_node;
53 unsigned int notifier_count;
54#ifdef CONFIG_DEBUG_FS
55 struct dentry *dentry;
56#endif
57 struct kref ref;
58};
59
60/*
61 * DOC: Basic clock implementations common to many platforms
62 *
63 * Each basic clock hardware type is comprised of a structure describing the
64 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
65 * unique flags for that hardware type, a registration function and an
66 * alternative macro for static initialization
67 */
68
69#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
70 _parents) \
71 static struct clk _name = { \
72 .name = #_name, \
73 .ops = &_ops, \
74 .hw = &_name##_hw.hw, \
75 .parent_names = _parent_names, \
76 .num_parents = ARRAY_SIZE(_parent_names), \
77 .parents = _parents, \
78 .flags = _flags | CLK_IS_BASIC, \
79 }
80
81#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
82 _fixed_rate_flags) \
83 static struct clk _name; \
84 static const char *_name##_parent_names[] = {}; \
85 static struct clk_fixed_rate _name##_hw = { \
86 .hw = { \
87 .clk = &_name, \
88 }, \
89 .fixed_rate = _rate, \
90 .flags = _fixed_rate_flags, \
91 }; \
92 DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
93 _name##_parent_names, NULL);
94
95#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
96 _flags, _reg, _bit_idx, \
97 _gate_flags, _lock) \
98 static struct clk _name; \
99 static const char *_name##_parent_names[] = { \
100 _parent_name, \
101 }; \
102 static struct clk *_name##_parents[] = { \
103 _parent_ptr, \
104 }; \
105 static struct clk_gate _name##_hw = { \
106 .hw = { \
107 .clk = &_name, \
108 }, \
109 .reg = _reg, \
110 .bit_idx = _bit_idx, \
111 .flags = _gate_flags, \
112 .lock = _lock, \
113 }; \
114 DEFINE_CLK(_name, clk_gate_ops, _flags, \
115 _name##_parent_names, _name##_parents);
116
117#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
118 _flags, _reg, _shift, _width, \
119 _divider_flags, _table, _lock) \
120 static struct clk _name; \
121 static const char *_name##_parent_names[] = { \
122 _parent_name, \
123 }; \
124 static struct clk *_name##_parents[] = { \
125 _parent_ptr, \
126 }; \
127 static struct clk_divider _name##_hw = { \
128 .hw = { \
129 .clk = &_name, \
130 }, \
131 .reg = _reg, \
132 .shift = _shift, \
133 .width = _width, \
134 .flags = _divider_flags, \
135 .table = _table, \
136 .lock = _lock, \
137 }; \
138 DEFINE_CLK(_name, clk_divider_ops, _flags, \
139 _name##_parent_names, _name##_parents);
140
141#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
142 _flags, _reg, _shift, _width, \
143 _divider_flags, _lock) \
144 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
145 _flags, _reg, _shift, _width, \
146 _divider_flags, NULL, _lock)
147
148#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
149 _parent_ptr, _flags, _reg, \
150 _shift, _width, _divider_flags, \
151 _table, _lock) \
152 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
153 _flags, _reg, _shift, _width, \
154 _divider_flags, _table, _lock) \
155
156#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
157 _reg, _shift, _width, \
158 _mux_flags, _lock) \
159 static struct clk _name; \
160 static struct clk_mux _name##_hw = { \
161 .hw = { \
162 .clk = &_name, \
163 }, \
164 .reg = _reg, \
165 .shift = _shift, \
166 .mask = BIT(_width) - 1, \
167 .flags = _mux_flags, \
168 .lock = _lock, \
169 }; \
170 DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
171 _parents);
172
173#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
174 _parent_ptr, _flags, \
175 _mult, _div) \
176 static struct clk _name; \
177 static const char *_name##_parent_names[] = { \
178 _parent_name, \
179 }; \
180 static struct clk *_name##_parents[] = { \
181 _parent_ptr, \
182 }; \
183 static struct clk_fixed_factor _name##_hw = { \
184 .hw = { \
185 .clk = &_name, \
186 }, \
187 .mult = _mult, \
188 .div = _div, \
189 }; \
190 DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
191 _name##_parent_names, _name##_parents);
192
193/**
194 * __clk_init - initialize the data structures in a struct clk
195 * @dev: device initializing this clk, placeholder for now
196 * @clk: clk being initialized
197 *
198 * Initializes the lists in struct clk, queries the hardware for the
199 * parent and rate and sets them both.
200 *
201 * Any struct clk passed into __clk_init must have the following members
202 * populated:
203 * .name
204 * .ops
205 * .hw
206 * .parent_names
207 * .num_parents
208 * .flags
209 *
210 * It is not necessary to call clk_register if __clk_init is used directly with
211 * statically initialized clock data.
212 *
213 * Returns 0 on success, otherwise an error code.
214 */
215int __clk_init(struct device *dev, struct clk *clk);
216
217struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
218
219#endif /* CONFIG_COMMON_CLK */
220#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d936409520f8..17dd6e9439d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,7 @@
33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34 34
35struct clk_hw; 35struct clk_hw;
36struct clk_core;
36struct dentry; 37struct dentry;
37 38
38/** 39/**
@@ -174,9 +175,12 @@ struct clk_ops {
174 unsigned long parent_rate); 175 unsigned long parent_rate);
175 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 176 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
176 unsigned long *parent_rate); 177 unsigned long *parent_rate);
177 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 178 long (*determine_rate)(struct clk_hw *hw,
178 unsigned long *best_parent_rate, 179 unsigned long rate,
179 struct clk_hw **best_parent_hw); 180 unsigned long min_rate,
181 unsigned long max_rate,
182 unsigned long *best_parent_rate,
183 struct clk_hw **best_parent_hw);
180 int (*set_parent)(struct clk_hw *hw, u8 index); 184 int (*set_parent)(struct clk_hw *hw, u8 index);
181 u8 (*get_parent)(struct clk_hw *hw); 185 u8 (*get_parent)(struct clk_hw *hw);
182 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 186 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -216,13 +220,17 @@ struct clk_init_data {
216 * clk_foo and then referenced by the struct clk instance that uses struct 220 * clk_foo and then referenced by the struct clk instance that uses struct
217 * clk_foo's clk_ops 221 * clk_foo's clk_ops
218 * 222 *
219 * @clk: pointer to the struct clk instance that points back to this struct 223 * @core: pointer to the struct clk_core instance that points back to this
220 * clk_hw instance 224 * struct clk_hw instance
225 *
226 * @clk: pointer to the per-user struct clk instance that can be used to call
227 * into the clk API
221 * 228 *
222 * @init: pointer to struct clk_init_data that contains the init data shared 229 * @init: pointer to struct clk_init_data that contains the init data shared
223 * with the common clock framework. 230 * with the common clock framework.
224 */ 231 */
225struct clk_hw { 232struct clk_hw {
233 struct clk_core *core;
226 struct clk *clk; 234 struct clk *clk;
227 const struct clk_init_data *init; 235 const struct clk_init_data *init;
228}; 236};
@@ -294,6 +302,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
294 const char *parent_name, unsigned long flags, 302 const char *parent_name, unsigned long flags,
295 void __iomem *reg, u8 bit_idx, 303 void __iomem *reg, u8 bit_idx,
296 u8 clk_gate_flags, spinlock_t *lock); 304 u8 clk_gate_flags, spinlock_t *lock);
305void clk_unregister_gate(struct clk *clk);
297 306
298struct clk_div_table { 307struct clk_div_table {
299 unsigned int val; 308 unsigned int val;
@@ -352,6 +361,17 @@ struct clk_divider {
352#define CLK_DIVIDER_READ_ONLY BIT(5) 361#define CLK_DIVIDER_READ_ONLY BIT(5)
353 362
354extern const struct clk_ops clk_divider_ops; 363extern const struct clk_ops clk_divider_ops;
364
365unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
366 unsigned int val, const struct clk_div_table *table,
367 unsigned long flags);
368long divider_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *prate, const struct clk_div_table *table,
370 u8 width, unsigned long flags);
371int divider_get_val(unsigned long rate, unsigned long parent_rate,
372 const struct clk_div_table *table, u8 width,
373 unsigned long flags);
374
355struct clk *clk_register_divider(struct device *dev, const char *name, 375struct clk *clk_register_divider(struct device *dev, const char *name,
356 const char *parent_name, unsigned long flags, 376 const char *parent_name, unsigned long flags,
357 void __iomem *reg, u8 shift, u8 width, 377 void __iomem *reg, u8 shift, u8 width,
@@ -361,6 +381,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
361 void __iomem *reg, u8 shift, u8 width, 381 void __iomem *reg, u8 shift, u8 width,
362 u8 clk_divider_flags, const struct clk_div_table *table, 382 u8 clk_divider_flags, const struct clk_div_table *table,
363 spinlock_t *lock); 383 spinlock_t *lock);
384void clk_unregister_divider(struct clk *clk);
364 385
365/** 386/**
366 * struct clk_mux - multiplexer clock 387 * struct clk_mux - multiplexer clock
@@ -382,6 +403,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
382 * register, and mask of mux bits are in higher 16-bit of this register. 403 * register, and mask of mux bits are in higher 16-bit of this register.
383 * While setting the mux bits, higher 16-bit should also be updated to 404 * While setting the mux bits, higher 16-bit should also be updated to
384 * indicate changing mux bits. 405 * indicate changing mux bits.
406 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
407 * frequency.
385 */ 408 */
386struct clk_mux { 409struct clk_mux {
387 struct clk_hw hw; 410 struct clk_hw hw;
@@ -396,7 +419,8 @@ struct clk_mux {
396#define CLK_MUX_INDEX_ONE BIT(0) 419#define CLK_MUX_INDEX_ONE BIT(0)
397#define CLK_MUX_INDEX_BIT BIT(1) 420#define CLK_MUX_INDEX_BIT BIT(1)
398#define CLK_MUX_HIWORD_MASK BIT(2) 421#define CLK_MUX_HIWORD_MASK BIT(2)
399#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 422#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
423#define CLK_MUX_ROUND_CLOSEST BIT(4)
400 424
401extern const struct clk_ops clk_mux_ops; 425extern const struct clk_ops clk_mux_ops;
402extern const struct clk_ops clk_mux_ro_ops; 426extern const struct clk_ops clk_mux_ro_ops;
@@ -411,6 +435,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
411 void __iomem *reg, u8 shift, u32 mask, 435 void __iomem *reg, u8 shift, u32 mask,
412 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 436 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
413 437
438void clk_unregister_mux(struct clk *clk);
439
414void of_fixed_factor_clk_setup(struct device_node *node); 440void of_fixed_factor_clk_setup(struct device_node *node);
415 441
416/** 442/**
@@ -550,15 +576,23 @@ bool __clk_is_prepared(struct clk *clk);
550bool __clk_is_enabled(struct clk *clk); 576bool __clk_is_enabled(struct clk *clk);
551struct clk *__clk_lookup(const char *name); 577struct clk *__clk_lookup(const char *name);
552long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 578long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
579 unsigned long min_rate,
580 unsigned long max_rate,
581 unsigned long *best_parent_rate,
582 struct clk_hw **best_parent_p);
583unsigned long __clk_determine_rate(struct clk_hw *core,
584 unsigned long rate,
585 unsigned long min_rate,
586 unsigned long max_rate);
587long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
588 unsigned long min_rate,
589 unsigned long max_rate,
553 unsigned long *best_parent_rate, 590 unsigned long *best_parent_rate,
554 struct clk_hw **best_parent_p); 591 struct clk_hw **best_parent_p);
555 592
556/* 593/*
557 * FIXME clock api without lock protection 594 * FIXME clock api without lock protection
558 */ 595 */
559int __clk_prepare(struct clk *clk);
560void __clk_unprepare(struct clk *clk);
561void __clk_reparent(struct clk *clk, struct clk *new_parent);
562unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 596unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
563 597
564struct of_device_id; 598struct of_device_id;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index c7f258a81761..8381bbfbc308 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -302,6 +302,46 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
302int clk_set_rate(struct clk *clk, unsigned long rate); 302int clk_set_rate(struct clk *clk, unsigned long rate);
303 303
304/** 304/**
305 * clk_has_parent - check if a clock is a possible parent for another
306 * @clk: clock source
307 * @parent: parent clock source
308 *
309 * This function can be used in drivers that need to check that a clock can be
310 * the parent of another without actually changing the parent.
311 *
312 * Returns true if @parent is a possible parent for @clk, false otherwise.
313 */
314bool clk_has_parent(struct clk *clk, struct clk *parent);
315
316/**
317 * clk_set_rate_range - set a rate range for a clock source
318 * @clk: clock source
319 * @min: desired minimum clock rate in Hz, inclusive
320 * @max: desired maximum clock rate in Hz, inclusive
321 *
322 * Returns success (0) or negative errno.
323 */
324int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
325
326/**
327 * clk_set_min_rate - set a minimum clock rate for a clock source
328 * @clk: clock source
329 * @rate: desired minimum clock rate in Hz, inclusive
330 *
331 * Returns success (0) or negative errno.
332 */
333int clk_set_min_rate(struct clk *clk, unsigned long rate);
334
335/**
336 * clk_set_max_rate - set a maximum clock rate for a clock source
337 * @clk: clock source
338 * @rate: desired maximum clock rate in Hz, inclusive
339 *
340 * Returns success (0) or negative errno.
341 */
342int clk_set_max_rate(struct clk *clk, unsigned long rate);
343
344/**
305 * clk_set_parent - set the parent clock source for this clock 345 * clk_set_parent - set the parent clock source for this clock
306 * @clk: clock source 346 * @clk: clock source
307 * @parent: parent clock source 347 * @parent: parent clock source
@@ -374,6 +414,11 @@ static inline long clk_round_rate(struct clk *clk, unsigned long rate)
374 return 0; 414 return 0;
375} 415}
376 416
417static inline bool clk_has_parent(struct clk *clk, struct clk *parent)
418{
419 return true;
420}
421
377static inline int clk_set_parent(struct clk *clk, struct clk *parent) 422static inline int clk_set_parent(struct clk *clk, struct clk *parent)
378{ 423{
379 return 0; 424 return 0;
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
deleted file mode 100644
index aed28c4451d9..000000000000
--- a/include/linux/clk/sunxi.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __LINUX_CLK_SUNXI_H_
16#define __LINUX_CLK_SUNXI_H_
17
18#include <linux/clk.h>
19
20void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
21
22#endif
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 55ef529a0dbf..0eac65054283 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,7 @@
15#ifndef __LINUX_CLK_TI_H__ 15#ifndef __LINUX_CLK_TI_H__
16#define __LINUX_CLK_TI_H__ 16#define __LINUX_CLK_TI_H__
17 17
18#include <linux/clk-provider.h>
18#include <linux/clkdev.h> 19#include <linux/clkdev.h>
19 20
20/** 21/**
@@ -217,6 +218,13 @@ struct ti_dt_clk {
217/* Maximum number of clock memmaps */ 218/* Maximum number of clock memmaps */
218#define CLK_MAX_MEMMAPS 4 219#define CLK_MAX_MEMMAPS 4
219 220
221/* Static memmap indices */
222enum {
223 TI_CLKM_CM = 0,
224 TI_CLKM_PRM,
225 TI_CLKM_SCRM,
226};
227
220typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
221 229
222/** 230/**
@@ -263,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
263 u8 index); 271 u8 index);
264long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 272long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265 unsigned long rate, 273 unsigned long rate,
274 unsigned long min_rate,
275 unsigned long max_rate,
266 unsigned long *best_parent_rate, 276 unsigned long *best_parent_rate,
267 struct clk_hw **best_parent_clk); 277 struct clk_hw **best_parent_clk);
268unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 278unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@@ -272,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
272 unsigned long *parent_rate); 282 unsigned long *parent_rate);
273long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 283long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
274 unsigned long rate, 284 unsigned long rate,
285 unsigned long min_rate,
286 unsigned long max_rate,
275 unsigned long *best_parent_rate, 287 unsigned long *best_parent_rate,
276 struct clk_hw **best_parent_clk); 288 struct clk_hw **best_parent_clk);
277u8 omap2_init_dpll_parent(struct clk_hw *hw); 289u8 omap2_init_dpll_parent(struct clk_hw *hw);
@@ -348,4 +360,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
348extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 360extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
349extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 361extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
350 362
363int omap3430_clk_legacy_init(void);
364int omap3430es1_clk_legacy_init(void);
365int omap36xx_clk_legacy_init(void);
366int am35xx_clk_legacy_init(void);
367
351#endif 368#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 22:44:34 -0400