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authorLennert Buytenhek <buytenh@wantstofly.org>2005-10-28 10:31:45 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-28 10:31:45 -0400
commit3b90c9c33361d49893645ffcebe6ca230f434705 (patch)
treebf51c431a2730e6a6ec48cedbbfe24db6323172e /include
parent63a4b52c9ddca944afc1b78aacbf641c650780d7 (diff)
[ARM] 2908/1: add register definitions for ixp2000 msf
Patch from Lennert Buytenhek We already had a mapping for the msf, but we didn't have any register definitions for it yet. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-ixp2000/ixp2000-regs.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 32aece069869..def089d693d2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -392,4 +392,47 @@
392#define WDT_RESET_ENABLE 0x01000000 392#define WDT_RESET_ENABLE 0x01000000
393 393
394 394
395/*
396 * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
397 * units, but the registers that differ between the two don't overlap,
398 * so we can have one register list for both.
399 */
400#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
401#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
402#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
403#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
404#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
405#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
406#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
407#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
408#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
409#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
410#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
411#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
412#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
413#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
414#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
415#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
416#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
417#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
418#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
419#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
420#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
421#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
422#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
423#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
424#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
425#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
426#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
427#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
428#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
429#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
430#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
431#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
432#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
433#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
434#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
435#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
436
437
395#endif /* _IXP2000_H_ */ 438#endif /* _IXP2000_H_ */