Merge branch 'linus' into perf/urgent, to pick up the upstream merged bits

Signed-off-by: Ingo Molnar <mingo@kernel.org>

107 files changed, 2723 insertions, 451 deletions

diff --git a/include/asm-generic/futex.h b/include/asm-generic/futex.h
index 01f227e14254..b59b5a52637e 100644
--- a/include/asm-generic/futex.h
+++ b/include/asm-generic/futex.h
@@ -5,6 +5,119 @@
 #include <linux/uaccess.h>
 #include <asm/errno.h>
 
+#ifndef CONFIG_SMP
+/*
+ * The following implementation only for uniprocessor machines.
+ * For UP, it's relies on the fact that pagefault_disable() also disables
+ * preemption to ensure mutual exclusion.
+ *
+ */
+
+/**
+ * futex_atomic_op_inuser() - Atomic arithmetic operation with constant
+ *                        argument and comparison of the previous
+ *                        futex value with another constant.
+ *
+ * @encoded_op: encoded operation to execute
+ * @uaddr:      pointer to user space address
+ *
+ * Return:
+ * 0 - On success
+ * <0 - On error
+ */
+static inline int
+futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval, ret;
+        u32 tmp;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        pagefault_disable();
+
+        ret = -EFAULT;
+        if (unlikely(get_user(oldval, uaddr) != 0))
+                goto out_pagefault_enable;
+
+        ret = 0;
+        tmp = oldval;
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                tmp = oparg;
+                break;
+        case FUTEX_OP_ADD:
+                tmp += oparg;
+                break;
+        case FUTEX_OP_OR:
+                tmp |= oparg;
+                break;
+        case FUTEX_OP_ANDN:
+                tmp &= ~oparg;
+                break;
+        case FUTEX_OP_XOR:
+                tmp ^= oparg;
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0))
+                ret = -EFAULT;
+
+out_pagefault_enable:
+        pagefault_enable();
+
+        if (ret == 0) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+/**
+ * futex_atomic_cmpxchg_inatomic() - Compare and exchange the content of the
+ *                              uaddr with newval if the current value is
+ *                              oldval.
+ * @uval:       pointer to store content of @uaddr
+ * @uaddr:      pointer to user space address
+ * @oldval:     old value
+ * @newval:     new value to store to @uaddr
+ *
+ * Return:
+ * 0 - On success
+ * <0 - On error
+ */
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
+{
+        u32 val;
+
+        if (unlikely(get_user(val, uaddr) != 0))
+                return -EFAULT;
+
+        if (val == oldval && unlikely(put_user(newval, uaddr) != 0))
+                return -EFAULT;
+
+        *uval = val;
+
+        return 0;
+}
+
+#else
 static inline int
 futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
 {
@@ -54,4 +167,5 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
         return -ENOSYS;
 }
 
+#endif /* CONFIG_SMP */
 #endif
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b8fdc57a7335..9db042304df3 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -12,6 +12,7 @@
 #define __ASM_GENERIC_IO_H
 
 #include <asm/page.h> /* I/O is all done through memory accesses */
+#include <linux/string.h> /* for memset() and memcpy() */
 #include <linux/types.h>
 
 #ifdef CONFIG_GENERIC_IOMAP
@@ -24,260 +25,691 @@
 #define mmiowb() do {} while (0)
 #endif
 
-/*****************************************************************************/
 /*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the simple architectures, we just read/write the
- * memory location directly.
+ * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
+ *
+ * On some architectures memory mapped IO needs to be accessed differently.
+ * On the simple architectures, we just read/write the memory location
+ * directly.
  */
+
 #ifndef __raw_readb
+#define __raw_readb __raw_readb
 static inline u8 __raw_readb(const volatile void __iomem *addr)
 {
-        return *(const volatile u8 __force *) addr;
+        return *(const volatile u8 __force *)addr;
 }
 #endif
 
 #ifndef __raw_readw
+#define __raw_readw __raw_readw
 static inline u16 __raw_readw(const volatile void __iomem *addr)
 {
-        return *(const volatile u16 __force *) addr;
+        return *(const volatile u16 __force *)addr;
 }
 #endif
 
 #ifndef __raw_readl
+#define __raw_readl __raw_readl
 static inline u32 __raw_readl(const volatile void __iomem *addr)
 {
-        return *(const volatile u32 __force *) addr;
+        return *(const volatile u32 __force *)addr;
 }
 #endif
 
-#define readb __raw_readb
-
-#define readw readw
-static inline u16 readw(const volatile void __iomem *addr)
-{
-        return __le16_to_cpu(__raw_readw(addr));
-}
-
-#define readl readl
-static inline u32 readl(const volatile void __iomem *addr)
+#ifdef CONFIG_64BIT
+#ifndef __raw_readq
+#define __raw_readq __raw_readq
+static inline u64 __raw_readq(const volatile void __iomem *addr)
 {
-        return __le32_to_cpu(__raw_readl(addr));
+        return *(const volatile u64 __force *)addr;
 }
+#endif
+#endif /* CONFIG_64BIT */
 
 #ifndef __raw_writeb
-static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
 {
-        *(volatile u8 __force *) addr = b;
+        *(volatile u8 __force *)addr = value;
 }
 #endif
 
 #ifndef __raw_writew
-static inline void __raw_writew(u16 b, volatile void __iomem *addr)
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 value, volatile void __iomem *addr)
 {
-        *(volatile u16 __force *) addr = b;
+        *(volatile u16 __force *)addr = value;
 }
 #endif
 
 #ifndef __raw_writel
-static inline void __raw_writel(u32 b, volatile void __iomem *addr)
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 value, volatile void __iomem *addr)
 {
-        *(volatile u32 __force *) addr = b;
+        *(volatile u32 __force *)addr = value;
 }
 #endif
 
-#define writeb __raw_writeb
-#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
-#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
-
 #ifdef CONFIG_64BIT
-#ifndef __raw_readq
-static inline u64 __raw_readq(const volatile void __iomem *addr)
+#ifndef __raw_writeq
+#define __raw_writeq __raw_writeq
+static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
 {
-        return *(const volatile u64 __force *) addr;
+        *(volatile u64 __force *)addr = value;
 }
 #endif
+#endif /* CONFIG_64BIT */
 
-#define readq readq
-static inline u64 readq(const volatile void __iomem *addr)
-{
-        return __le64_to_cpu(__raw_readq(addr));
-}
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
 
-#ifndef __raw_writeq
-static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
+#ifndef readb
+#define readb readb
+static inline u8 readb(const volatile void __iomem *addr)
 {
-        *(volatile u64 __force *) addr = b;
+        return __raw_readb(addr);
 }
 #endif
 
-#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
-#endif /* CONFIG_64BIT */
-
-#ifndef PCI_IOBASE
-#define PCI_IOBASE ((void __iomem *) 0)
+#ifndef readw
+#define readw readw
+static inline u16 readw(const volatile void __iomem *addr)
+{
+        return __le16_to_cpu(__raw_readw(addr));
+}
 #endif
 
-/*****************************************************************************/
-/*
- * traditional input/output functions
- */
-
-static inline u8 inb(unsigned long addr)
+#ifndef readl
+#define readl readl
+static inline u32 readl(const volatile void __iomem *addr)
 {
-        return readb(addr + PCI_IOBASE);
+        return __le32_to_cpu(__raw_readl(addr));
 }
+#endif
 
-static inline u16 inw(unsigned long addr)
+#ifdef CONFIG_64BIT
+#ifndef readq
+#define readq readq
+static inline u64 readq(const volatile void __iomem *addr)
 {
-        return readw(addr + PCI_IOBASE);
+        return __le64_to_cpu(__raw_readq(addr));
 }
+#endif
+#endif /* CONFIG_64BIT */
 
-static inline u32 inl(unsigned long addr)
+#ifndef writeb
+#define writeb writeb
+static inline void writeb(u8 value, volatile void __iomem *addr)
 {
-        return readl(addr + PCI_IOBASE);
+        __raw_writeb(value, addr);
 }
+#endif
 
-static inline void outb(u8 b, unsigned long addr)
+#ifndef writew
+#define writew writew
+static inline void writew(u16 value, volatile void __iomem *addr)
 {
-        writeb(b, addr + PCI_IOBASE);
+        __raw_writew(cpu_to_le16(value), addr);
 }
+#endif
 
-static inline void outw(u16 b, unsigned long addr)
+#ifndef writel
+#define writel writel
+static inline void writel(u32 value, volatile void __iomem *addr)
 {
-        writew(b, addr + PCI_IOBASE);
+        __raw_writel(__cpu_to_le32(value), addr);
 }
+#endif
 
-static inline void outl(u32 b, unsigned long addr)
+#ifdef CONFIG_64BIT
+#ifndef writeq
+#define writeq writeq
+static inline void writeq(u64 value, volatile void __iomem *addr)
 {
-        writel(b, addr + PCI_IOBASE);
+        __raw_writeq(__cpu_to_le64(value), addr);
 }
+#endif
+#endif /* CONFIG_64BIT */
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+#ifndef readb_relaxed
+#define readb_relaxed readb
+#endif
 
-#define inb_p(addr)     inb(addr)
-#define inw_p(addr)     inw(addr)
-#define inl_p(addr)     inl(addr)
-#define outb_p(x, addr) outb((x), (addr))
-#define outw_p(x, addr) outw((x), (addr))
-#define outl_p(x, addr) outl((x), (addr))
+#ifndef readw_relaxed
+#define readw_relaxed readw
+#endif
 
-#ifndef insb
-static inline void insb(unsigned long addr, void *buffer, int count)
+#ifndef readl_relaxed
+#define readl_relaxed readl
+#endif
+
+#ifndef readq_relaxed
+#define readq_relaxed readq
+#endif
+
+#ifndef writeb_relaxed
+#define writeb_relaxed writeb
+#endif
+
+#ifndef writew_relaxed
+#define writew_relaxed writew
+#endif
+
+#ifndef writel_relaxed
+#define writel_relaxed writel
+#endif
+
+#ifndef writeq_relaxed
+#define writeq_relaxed writeq
+#endif
+
+/*
+ * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
+ * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
+ */
+#ifndef readsb
+#define readsb readsb
+static inline void readsb(const volatile void __iomem *addr, void *buffer,
+                          unsigned int count)
 {
         if (count) {
                 u8 *buf = buffer;
+
                 do {
-                        u8 x = __raw_readb(addr + PCI_IOBASE);
+                        u8 x = __raw_readb(addr);
                         *buf++ = x;
                 } while (--count);
         }
 }
 #endif
 
-#ifndef insw
-static inline void insw(unsigned long addr, void *buffer, int count)
+#ifndef readsw
+#define readsw readsw
+static inline void readsw(const volatile void __iomem *addr, void *buffer,
+                          unsigned int count)
 {
         if (count) {
                 u16 *buf = buffer;
+
                 do {
-                        u16 x = __raw_readw(addr + PCI_IOBASE);
+                        u16 x = __raw_readw(addr);
                         *buf++ = x;
                 } while (--count);
         }
 }
 #endif
 
-#ifndef insl
-static inline void insl(unsigned long addr, void *buffer, int count)
+#ifndef readsl
+#define readsl readsl
+static inline void readsl(const volatile void __iomem *addr, void *buffer,
+                          unsigned int count)
 {
         if (count) {
                 u32 *buf = buffer;
+
                 do {
-                        u32 x = __raw_readl(addr + PCI_IOBASE);
+                        u32 x = __raw_readl(addr);
                         *buf++ = x;
                 } while (--count);
         }
 }
 #endif
 
-#ifndef outsb
-static inline void outsb(unsigned long addr, const void *buffer, int count)
+#ifdef CONFIG_64BIT
+#ifndef readsq
+#define readsq readsq
+static inline void readsq(const volatile void __iomem *addr, void *buffer,
+                          unsigned int count)
+{
+        if (count) {
+                u64 *buf = buffer;
+
+                do {
+                        u64 x = __raw_readq(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef writesb
+#define writesb writesb
+static inline void writesb(volatile void __iomem *addr, const void *buffer,
+                           unsigned int count)
 {
         if (count) {
                 const u8 *buf = buffer;
+
                 do {
-                        __raw_writeb(*buf++, addr + PCI_IOBASE);
+                        __raw_writeb(*buf++, addr);
                 } while (--count);
         }
 }
 #endif
 
-#ifndef outsw
-static inline void outsw(unsigned long addr, const void *buffer, int count)
+#ifndef writesw
+#define writesw writesw
+static inline void writesw(volatile void __iomem *addr, const void *buffer,
+                           unsigned int count)
 {
         if (count) {
                 const u16 *buf = buffer;
+
                 do {
-                        __raw_writew(*buf++, addr + PCI_IOBASE);
+                        __raw_writew(*buf++, addr);
                 } while (--count);
         }
 }
 #endif
 
-#ifndef outsl
-static inline void outsl(unsigned long addr, const void *buffer, int count)
+#ifndef writesl
+#define writesl writesl
+static inline void writesl(volatile void __iomem *addr, const void *buffer,
+                           unsigned int count)
 {
         if (count) {
                 const u32 *buf = buffer;
+
                 do {
-                        __raw_writel(*buf++, addr + PCI_IOBASE);
+                        __raw_writel(*buf++, addr);
                 } while (--count);
         }
 }
 #endif
 
-#ifndef CONFIG_GENERIC_IOMAP
-#define ioread8(addr)           readb(addr)
-#define ioread16(addr)          readw(addr)
-#define ioread16be(addr)        __be16_to_cpu(__raw_readw(addr))
-#define ioread32(addr)          readl(addr)
-#define ioread32be(addr)        __be32_to_cpu(__raw_readl(addr))
-
-#define iowrite8(v, addr)       writeb((v), (addr))
-#define iowrite16(v, addr)      writew((v), (addr))
-#define iowrite16be(v, addr)    __raw_writew(__cpu_to_be16(v), addr)
-#define iowrite32(v, addr)      writel((v), (addr))
-#define iowrite32be(v, addr)    __raw_writel(__cpu_to_be32(v), addr)
-
-#define ioread8_rep(p, dst, count) \
-        insb((unsigned long) (p), (dst), (count))
-#define ioread16_rep(p, dst, count) \
-        insw((unsigned long) (p), (dst), (count))
-#define ioread32_rep(p, dst, count) \
-        insl((unsigned long) (p), (dst), (count))
-
-#define iowrite8_rep(p, src, count) \
-        outsb((unsigned long) (p), (src), (count))
-#define iowrite16_rep(p, src, count) \
-        outsw((unsigned long) (p), (src), (count))
-#define iowrite32_rep(p, src, count) \
-        outsl((unsigned long) (p), (src), (count))
-#endif /* CONFIG_GENERIC_IOMAP */
+#ifdef CONFIG_64BIT
+#ifndef writesq
+#define writesq writesq
+static inline void writesq(volatile void __iomem *addr, const void *buffer,
+                           unsigned int count)
+{
+        if (count) {
+                const u64 *buf = buffer;
+
+                do {
+                        __raw_writeq(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef PCI_IOBASE
+#define PCI_IOBASE ((void __iomem *)0)
+#endif
 
 #ifndef IO_SPACE_LIMIT
 #define IO_SPACE_LIMIT 0xffff
 #endif
 
+/*
+ * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
+ * implemented on hardware that needs an additional delay for I/O accesses to
+ * take effect.
+ */
+
+#ifndef inb
+#define inb inb
+static inline u8 inb(unsigned long addr)
+{
+        return readb(PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef inw
+#define inw inw
+static inline u16 inw(unsigned long addr)
+{
+        return readw(PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef inl
+#define inl inl
+static inline u32 inl(unsigned long addr)
+{
+        return readl(PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef outb
+#define outb outb
+static inline void outb(u8 value, unsigned long addr)
+{
+        writeb(value, PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef outw
+#define outw outw
+static inline void outw(u16 value, unsigned long addr)
+{
+        writew(value, PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef outl
+#define outl outl
+static inline void outl(u32 value, unsigned long addr)
+{
+        writel(value, PCI_IOBASE + addr);
+}
+#endif
+
+#ifndef inb_p
+#define inb_p inb_p
+static inline u8 inb_p(unsigned long addr)
+{
+        return inb(addr);
+}
+#endif
+
+#ifndef inw_p
+#define inw_p inw_p
+static inline u16 inw_p(unsigned long addr)
+{
+        return inw(addr);
+}
+#endif
+
+#ifndef inl_p
+#define inl_p inl_p
+static inline u32 inl_p(unsigned long addr)
+{
+        return inl(addr);
+}
+#endif
+
+#ifndef outb_p
+#define outb_p outb_p
+static inline void outb_p(u8 value, unsigned long addr)
+{
+        outb(value, addr);
+}
+#endif
+
+#ifndef outw_p
+#define outw_p outw_p
+static inline void outw_p(u16 value, unsigned long addr)
+{
+        outw(value, addr);
+}
+#endif
+
+#ifndef outl_p
+#define outl_p outl_p
+static inline void outl_p(u32 value, unsigned long addr)
+{
+        outl(value, addr);
+}
+#endif
+
+/*
+ * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
+ * single I/O port multiple times.
+ */
+
+#ifndef insb
+#define insb insb
+static inline void insb(unsigned long addr, void *buffer, unsigned int count)
+{
+        readsb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insw
+#define insw insw
+static inline void insw(unsigned long addr, void *buffer, unsigned int count)
+{
+        readsw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insl
+#define insl insl
+static inline void insl(unsigned long addr, void *buffer, unsigned int count)
+{
+        readsl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsb
+#define outsb outsb
+static inline void outsb(unsigned long addr, const void *buffer,
+                         unsigned int count)
+{
+        writesb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsw
+#define outsw outsw
+static inline void outsw(unsigned long addr, const void *buffer,
+                         unsigned int count)
+{
+        writesw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsl
+#define outsl outsl
+static inline void outsl(unsigned long addr, const void *buffer,
+                         unsigned int count)
+{
+        writesl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insb_p
+#define insb_p insb_p
+static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
+{
+        insb(addr, buffer, count);
+}
+#endif
+
+#ifndef insw_p
+#define insw_p insw_p
+static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
+{
+        insw(addr, buffer, count);
+}
+#endif
+
+#ifndef insl_p
+#define insl_p insl_p
+static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
+{
+        insl(addr, buffer, count);
+}
+#endif
+
+#ifndef outsb_p
+#define outsb_p outsb_p
+static inline void outsb_p(unsigned long addr, const void *buffer,
+                           unsigned int count)
+{
+        outsb(addr, buffer, count);
+}
+#endif
+
+#ifndef outsw_p
+#define outsw_p outsw_p
+static inline void outsw_p(unsigned long addr, const void *buffer,
+                           unsigned int count)
+{
+        outsw(addr, buffer, count);
+}
+#endif
+
+#ifndef outsl_p
+#define outsl_p outsl_p
+static inline void outsl_p(unsigned long addr, const void *buffer,
+                           unsigned int count)
+{
+        outsl(addr, buffer, count);
+}
+#endif
+
+#ifndef CONFIG_GENERIC_IOMAP
+#ifndef ioread8
+#define ioread8 ioread8
+static inline u8 ioread8(const volatile void __iomem *addr)
+{
+        return readb(addr);
+}
+#endif
+
+#ifndef ioread16
+#define ioread16 ioread16
+static inline u16 ioread16(const volatile void __iomem *addr)
+{
+        return readw(addr);
+}
+#endif
+
+#ifndef ioread32
+#define ioread32 ioread32
+static inline u32 ioread32(const volatile void __iomem *addr)
+{
+        return readl(addr);
+}
+#endif
+
+#ifndef iowrite8
+#define iowrite8 iowrite8
+static inline void iowrite8(u8 value, volatile void __iomem *addr)
+{
+        writeb(value, addr);
+}
+#endif
+
+#ifndef iowrite16
+#define iowrite16 iowrite16
+static inline void iowrite16(u16 value, volatile void __iomem *addr)
+{
+        writew(value, addr);
+}
+#endif
+
+#ifndef iowrite32
+#define iowrite32 iowrite32
+static inline void iowrite32(u32 value, volatile void __iomem *addr)
+{
+        writel(value, addr);
+}
+#endif
+
+#ifndef ioread16be
+#define ioread16be ioread16be
+static inline u16 ioread16be(const volatile void __iomem *addr)
+{
+        return __be16_to_cpu(__raw_readw(addr));
+}
+#endif
+
+#ifndef ioread32be
+#define ioread32be ioread32be
+static inline u32 ioread32be(const volatile void __iomem *addr)
+{
+        return __be32_to_cpu(__raw_readl(addr));
+}
+#endif
+
+#ifndef iowrite16be
+#define iowrite16be iowrite16be
+static inline void iowrite16be(u16 value, void volatile __iomem *addr)
+{
+        __raw_writew(__cpu_to_be16(value), addr);
+}
+#endif
+
+#ifndef iowrite32be
+#define iowrite32be iowrite32be
+static inline void iowrite32be(u32 value, volatile void __iomem *addr)
+{
+        __raw_writel(__cpu_to_be32(value), addr);
+}
+#endif
+
+#ifndef ioread8_rep
+#define ioread8_rep ioread8_rep
+static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
+                               unsigned int count)
+{
+        readsb(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread16_rep
+#define ioread16_rep ioread16_rep
+static inline void ioread16_rep(const volatile void __iomem *addr,
+                                void *buffer, unsigned int count)
+{
+        readsw(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread32_rep
+#define ioread32_rep ioread32_rep
+static inline void ioread32_rep(const volatile void __iomem *addr,
+                                void *buffer, unsigned int count)
+{
+        readsl(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite8_rep
+#define iowrite8_rep iowrite8_rep
+static inline void iowrite8_rep(volatile void __iomem *addr,
+                                const void *buffer,
+                                unsigned int count)
+{
+        writesb(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite16_rep
+#define iowrite16_rep iowrite16_rep
+static inline void iowrite16_rep(volatile void __iomem *addr,
+                                 const void *buffer,
+                                 unsigned int count)
+{
+        writesw(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite32_rep
+#define iowrite32_rep iowrite32_rep
+static inline void iowrite32_rep(volatile void __iomem *addr,
+                                 const void *buffer,
+                                 unsigned int count)
+{
+        writesl(addr, buffer, count);
+}
+#endif
+#endif /* CONFIG_GENERIC_IOMAP */
+
 #ifdef __KERNEL__
 
 #include <linux/vmalloc.h>
-#define __io_virt(x) ((void __force *) (x))
+#define __io_virt(x) ((void __force *)(x))
 
 #ifndef CONFIG_GENERIC_IOMAP
 struct pci_dev;
 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 
 #ifndef pci_iounmap
+#define pci_iounmap pci_iounmap
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
 {
 }
@@ -289,11 +721,15 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
  * These are pretty trivial
  */
 #ifndef virt_to_phys
+#define virt_to_phys virt_to_phys
 static inline unsigned long virt_to_phys(volatile void *address)
 {
         return __pa((unsigned long)address);
 }
+#endif
 
+#ifndef phys_to_virt
+#define phys_to_virt phys_to_virt
 static inline void *phys_to_virt(unsigned long address)
 {
         return __va(address);
@@ -306,37 +742,65 @@ static inline void *phys_to_virt(unsigned long address)
  * This implementation is for the no-MMU case only... if you have an MMU
  * you'll need to provide your own definitions.
  */
+
 #ifndef CONFIG_MMU
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+#ifndef ioremap
+#define ioremap ioremap
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
-        return (void __iomem*) (unsigned long)offset;
+        return (void __iomem *)(unsigned long)offset;
 }
+#endif
 
-#define __ioremap(offset, size, flags)  ioremap(offset, size)
+#ifndef __ioremap
+#define __ioremap __ioremap
+static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
+                                      unsigned long flags)
+{
+        return ioremap(offset, size);
+}
+#endif
 
 #ifndef ioremap_nocache
-#define ioremap_nocache ioremap
+#define ioremap_nocache ioremap_nocache
+static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
+{
+        return ioremap(offset, size);
+}
 #endif
 
 #ifndef ioremap_wc
-#define ioremap_wc ioremap_nocache
+#define ioremap_wc ioremap_wc
+static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
+{
+        return ioremap_nocache(offset, size);
+}
 #endif
 
+#ifndef iounmap
+#define iounmap iounmap
 static inline void iounmap(void __iomem *addr)
 {
 }
+#endif
 #endif /* CONFIG_MMU */
 
 #ifdef CONFIG_HAS_IOPORT_MAP
 #ifndef CONFIG_GENERIC_IOMAP
+#ifndef ioport_map
+#define ioport_map ioport_map
 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
 {
         return PCI_IOBASE + (port & IO_SPACE_LIMIT);
 }
+#endif
 
+#ifndef ioport_unmap
+#define ioport_unmap ioport_unmap
 static inline void ioport_unmap(void __iomem *p)
 {
 }
+#endif
 #else /* CONFIG_GENERIC_IOMAP */
 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 extern void ioport_unmap(void __iomem *p);
@@ -344,35 +808,68 @@ extern void ioport_unmap(void __iomem *p);
 #endif /* CONFIG_HAS_IOPORT_MAP */
 
 #ifndef xlate_dev_kmem_ptr
-#define xlate_dev_kmem_ptr(p)   p
+#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
+static inline void *xlate_dev_kmem_ptr(void *addr)
+{
+        return addr;
+}
 #endif
+
 #ifndef xlate_dev_mem_ptr
-#define xlate_dev_mem_ptr(p)    __va(p)
+#define xlate_dev_mem_ptr xlate_dev_mem_ptr
+static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
+{
+        return __va(addr);
+}
+#endif
+
+#ifndef unxlate_dev_mem_ptr
+#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
+static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
+{
+}
 #endif
 
 #ifdef CONFIG_VIRT_TO_BUS
 #ifndef virt_to_bus
-static inline unsigned long virt_to_bus(volatile void *address)
+static inline unsigned long virt_to_bus(void *address)
 {
-        return ((unsigned long) address);
+        return (unsigned long)address;
 }
 
 static inline void *bus_to_virt(unsigned long address)
 {
-        return (void *) address;
+        return (void *)address;
 }
 #endif
 #endif
 
 #ifndef memset_io
-#define memset_io(a, b, c)      memset(__io_virt(a), (b), (c))
+#define memset_io memset_io
+static inline void memset_io(volatile void __iomem *addr, int value,
+                             size_t size)
+{
+        memset(__io_virt(addr), value, size);
+}
 #endif
 
 #ifndef memcpy_fromio
-#define memcpy_fromio(a, b, c)  memcpy((a), __io_virt(b), (c))
+#define memcpy_fromio memcpy_fromio
+static inline void memcpy_fromio(void *buffer,
+                                 const volatile void __iomem *addr,
+                                 size_t size)
+{
+        memcpy(buffer, __io_virt(addr), size);
+}
 #endif
+
 #ifndef memcpy_toio
-#define memcpy_toio(a, b, c)    memcpy(__io_virt(a), (b), (c))
+#define memcpy_toio memcpy_toio
+static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
+                               size_t size)
+{
+        memcpy(__io_virt(addr), buffer, size);
+}
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-generic/seccomp.h b/include/asm-generic/seccomp.h
new file mode 100644
index 000000000000..9fa1f653ed3b
--- /dev/null
+++ b/include/asm-generic/seccomp.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-generic/seccomp.h
+ *
+ * Copyright (C) 2014 Linaro Limited
+ * Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASM_GENERIC_SECCOMP_H
+#define _ASM_GENERIC_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#if defined(CONFIG_COMPAT) && !defined(__NR_seccomp_read_32)
+#define __NR_seccomp_read_32            __NR_read
+#define __NR_seccomp_write_32           __NR_write
+#define __NR_seccomp_exit_32            __NR_exit
+#define __NR_seccomp_sigreturn_32       __NR_rt_sigreturn
+#endif /* CONFIG_COMPAT && ! already defined */
+
+#define __NR_seccomp_read               __NR_read
+#define __NR_seccomp_write              __NR_write
+#define __NR_seccomp_exit               __NR_exit
+#ifndef __NR_seccomp_sigreturn
+#define __NR_seccomp_sigreturn          __NR_rt_sigreturn
+#endif
+
+#endif /* _ASM_GENERIC_SECCOMP_H */
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index 5672d7ea1fa0..08848050922e 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -96,10 +96,9 @@ struct mmu_gather {
 #endif
         unsigned long           start;
         unsigned long           end;
-        unsigned int            need_flush : 1, /* Did free PTEs */
         /* we are in the middle of an operation to clear
          * a full mm and can make some optimizations */
-                                fullmm : 1,
+        unsigned int            fullmm : 1,
         /* we have performed an operation which
          * requires a complete flush of the tlb */
                                 need_flush_all : 1;
@@ -128,16 +127,54 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
                 tlb_flush_mmu(tlb);
 }
 
+static inline void __tlb_adjust_range(struct mmu_gather *tlb,
+                                      unsigned long address)
+{
+        tlb->start = min(tlb->start, address);
+        tlb->end = max(tlb->end, address + PAGE_SIZE);
+}
+
+static inline void __tlb_reset_range(struct mmu_gather *tlb)
+{
+        tlb->start = TASK_SIZE;
+        tlb->end = 0;
+}
+
+/*
+ * In the case of tlb vma handling, we can optimise these away in the
+ * case where we're doing a full MM flush.  When we're doing a munmap,
+ * the vmas are adjusted to only cover the region to be torn down.
+ */
+#ifndef tlb_start_vma
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#endif
+
+#define __tlb_end_vma(tlb, vma)                                 \
+        do {                                                    \
+                if (!tlb->fullmm && tlb->end) {                 \
+                        tlb_flush(tlb);                         \
+                        __tlb_reset_range(tlb);                 \
+                }                                               \
+        } while (0)
+
+#ifndef tlb_end_vma
+#define tlb_end_vma     __tlb_end_vma
+#endif
+
+#ifndef __tlb_remove_tlb_entry
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+#endif
+
 /**
  * tlb_remove_tlb_entry - remember a pte unmapping for later tlb invalidation.
  *
- * Record the fact that pte's were really umapped in ->need_flush, so we can
- * later optimise away the tlb invalidate.   This helps when userspace is
- * unmapping already-unmapped pages, which happens quite a lot.
+ * Record the fact that pte's were really unmapped by updating the range,
+ * so we can later optimise away the tlb invalidate.   This helps when
+ * userspace is unmapping already-unmapped pages, which happens quite a lot.
  */
 #define tlb_remove_tlb_entry(tlb, ptep, address)                \
         do {                                                    \
-                tlb->need_flush = 1;                            \
+                __tlb_adjust_range(tlb, address);               \
                 __tlb_remove_tlb_entry(tlb, ptep, address);     \
         } while (0)
 
@@ -151,27 +188,27 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 
 #define tlb_remove_pmd_tlb_entry(tlb, pmdp, address)            \
         do {                                                    \
-                tlb->need_flush = 1;                            \
+                __tlb_adjust_range(tlb, address);               \
                 __tlb_remove_pmd_tlb_entry(tlb, pmdp, address); \
         } while (0)
 
 #define pte_free_tlb(tlb, ptep, address)                        \
         do {                                                    \
-                tlb->need_flush = 1;                            \
+                __tlb_adjust_range(tlb, address);               \
                 __pte_free_tlb(tlb, ptep, address);             \
         } while (0)
 
 #ifndef __ARCH_HAS_4LEVEL_HACK
 #define pud_free_tlb(tlb, pudp, address)                        \
         do {                                                    \
-                tlb->need_flush = 1;                            \
+                __tlb_adjust_range(tlb, address);               \
                 __pud_free_tlb(tlb, pudp, address);             \
         } while (0)
 #endif
 
 #define pmd_free_tlb(tlb, pmdp, address)                        \
         do {                                                    \
-                tlb->need_flush = 1;                            \
+                __tlb_adjust_range(tlb, address);               \
                 __pmd_free_tlb(tlb, pmdp, address);             \
         } while (0)
 
diff --git a/include/dt-bindings/arm/ux500_pm_domains.h b/include/dt-bindings/arm/ux500_pm_domains.h
new file mode 100644
index 000000000000..398a6c0288d1
--- /dev/null
+++ b/include/dt-bindings/arm/ux500_pm_domains.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+
+#define DOMAIN_VAPE             0
+
+/* Number of PM domains. */
+#define NR_DOMAINS              (DOMAIN_VAPE + 1)
+
+#endif
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 5f2667ecd98e..f4b7478e23c8 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -198,6 +198,9 @@
 #define IMX5_CLK_OCRAM                  186
 #define IMX5_CLK_SAHARA_IPG_GATE        187
 #define IMX5_CLK_SATA_REF               188
-#define IMX5_CLK_END                    189
+#define IMX5_CLK_STEP_SEL               189
+#define IMX5_CLK_CPU_PODF_SEL           190
+#define IMX5_CLK_ARM                    191
+#define IMX5_CLK_END                    192
 
 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
index a929f86d0ddd..d72b5b35f15e 100644
--- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -60,7 +60,7 @@
 #define ESC1_CLK_SRC                    43
 #define HDMI_CLK_SRC                    44
 #define VSYNC_CLK_SRC                   45
-#define RBCPR_CLK_SRC                   46
+#define MMSS_RBCPR_CLK_SRC              46
 #define RBBMTIMER_CLK_SRC               47
 #define MAPLE_CLK_SRC                   48
 #define VDP_CLK_SRC                     49
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
index f6b4b0fe7a43..476135da0f23 100644
--- a/include/dt-bindings/clock/r8a7740-clock.h
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -40,6 +40,7 @@
 
 /* MSTP2 */
 #define R8A7740_CLK_SCIFA6      30
+#define R8A7740_CLK_INTCA       29
 #define R8A7740_CLK_SCIFA7      22
 #define R8A7740_CLK_DMAC1       18
 #define R8A7740_CLK_DMAC2       17
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 8ea7ab0346ad..c27b3b5133b9 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,8 +26,18 @@
 #define R8A7790_CLK_MSIOF0              0
 
 /* MSTP1 */
-#define R8A7790_CLK_JPU         6
+#define R8A7790_CLK_VCP1                0
+#define R8A7790_CLK_VCP0                1
+#define R8A7790_CLK_VPC1                2
+#define R8A7790_CLK_VPC0                3
+#define R8A7790_CLK_JPU                 6
+#define R8A7790_CLK_SSP1                9
 #define R8A7790_CLK_TMU1                11
+#define R8A7790_CLK_3DG                 12
+#define R8A7790_CLK_2DDMAC              15
+#define R8A7790_CLK_FDP1_2              17
+#define R8A7790_CLK_FDP1_1              18
+#define R8A7790_CLK_FDP1_0              19
 #define R8A7790_CLK_TMU3                21
 #define R8A7790_CLK_TMU2                22
 #define R8A7790_CLK_CMT0                24
@@ -68,6 +78,8 @@
 #define R8A7790_CLK_USBDMAC1            31
 
 /* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1         1
+#define R8A7790_CLK_AUDIO_DMAC0         2
 #define R8A7790_CLK_THERMAL             22
 #define R8A7790_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 58c3f49d068c..3ea2bbc0da3f 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,8 +25,15 @@
 #define R8A7791_CLK_MSIOF0              0
 
 /* MSTP1 */
-#define R8A7791_CLK_JPU         6
+#define R8A7791_CLK_VCP0                1
+#define R8A7791_CLK_VPC0                3
+#define R8A7791_CLK_JPU                 6
+#define R8A7791_CLK_SSP1                9
 #define R8A7791_CLK_TMU1                11
+#define R8A7791_CLK_3DG                 12
+#define R8A7791_CLK_2DDMAC              15
+#define R8A7791_CLK_FDP1_1              18
+#define R8A7791_CLK_FDP1_0              19
 #define R8A7791_CLK_TMU3                21
 #define R8A7791_CLK_TMU2                22
 #define R8A7791_CLK_CMT0                24
@@ -62,6 +69,8 @@
 #define R8A7791_CLK_USBDMAC1            31
 
 /* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1         1
+#define R8A7791_CLK_AUDIO_DMAC0         2
 #define R8A7791_CLK_THERMAL             22
 #define R8A7791_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 9ac1043e25bc..aa9c286e60c0 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -26,11 +26,18 @@
 #define R8A7794_CLK_MSIOF0              0
 
 /* MSTP1 */
+#define R8A7794_CLK_VCP0                1
+#define R8A7794_CLK_VPC0                3
 #define R8A7794_CLK_TMU1                11
+#define R8A7794_CLK_3DG                 12
+#define R8A7794_CLK_2DDMAC              15
+#define R8A7794_CLK_FDP1_0              19
 #define R8A7794_CLK_TMU3                21
 #define R8A7794_CLK_TMU2                22
 #define R8A7794_CLK_CMT0                24
 #define R8A7794_CLK_TMU0                25
+#define R8A7794_CLK_VSP1_DU0            28
+#define R8A7794_CLK_VSP1_S              31
 
 /* MSTP2 */
 #define R8A7794_CLK_SCIFA2              2
@@ -61,6 +68,8 @@
 #define R8A7794_CLK_SCIF0               21
 
 /* MSTP8 */
+#define R8A7794_CLK_VIN1                10
+#define R8A7794_CLK_VIN0                11
 #define R8A7794_CLK_ETHER               13
 
 /* MSTP9 */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000000..7af2b717b3b2
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,86 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU             0
+#define CLK_FDMA                1
+#define CLK_NAND                2
+#define CLK_HVA                 3
+#define CLK_PROC_STFE           4
+#define CLK_PROC_TP             5
+#define CLK_RX_ICN_DMU          6
+#define CLK_RX_ICN_DISP_0       6
+#define CLK_RX_ICN_DISP_1       6
+#define CLK_RX_ICN_HVA          7
+#define CLK_RX_ICN_TS           7
+#define CLK_ICN_CPU             8
+#define CLK_TX_ICN_DMU          9
+#define CLK_TX_ICN_HVA          9
+#define CLK_TX_ICN_TS           9
+#define CLK_ICN_COMPO           9
+#define CLK_MMC_0               10
+#define CLK_MMC_1               11
+#define CLK_JPEGDEC             12
+#define CLK_ICN_REG             13
+#define CLK_TRACE_A9            13
+#define CLK_PTI_STM             13
+#define CLK_EXT2F_A9            13
+#define CLK_IC_BDISP_0          14
+#define CLK_IC_BDISP_1          15
+#define CLK_PP_DMU              16
+#define CLK_VID_DMU             17
+#define CLK_DSS_LPC             18
+#define CLK_ST231_AUD_0         19
+#define CLK_ST231_GP_0          19
+#define CLK_ST231_GP_1          20
+#define CLK_ST231_DMU           21
+#define CLK_ICN_LMI             22
+#define CLK_TX_ICN_DISP_0       23
+#define CLK_TX_ICN_DISP_1       23
+#define CLK_ICN_SBC             24
+#define CLK_STFE_FRC2           25
+#define CLK_ETH_PHY             26
+#define CLK_ETH_REF_PHYCLK      27
+#define CLK_FLASH_PROMIP        28
+#define CLK_MAIN_DISP           29
+#define CLK_AUX_DISP            30
+#define CLK_COMPO_DVP           31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0               0
+#define CLK_PCM_1               1
+#define CLK_PCM_2               2
+#define CLK_SPDIFF              3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP       0
+#define CLK_PIX_PIP             1
+#define CLK_PIX_GDP1            2
+#define CLK_PIX_GDP2            3
+#define CLK_PIX_GDP3            4
+#define CLK_PIX_GDP4            5
+#define CLK_PIX_AUX_DISP        6
+#define CLK_DENC                7
+#define CLK_PIX_HDDAC           8
+#define CLK_HDDAC               9
+#define CLK_SDDAC               10
+#define CLK_PIX_DVO             11
+#define CLK_DVO                 12
+#define CLK_PIX_HDMI            13
+#define CLK_TMDS_HDMI           14
+#define CLK_REF_HDMIPHY         15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1           0
+#define CLK_TSOUT_0             1
+#define CLK_TSOUT_1             2
+#define CLK_MCHI                3
+#define CLK_VSENS_COMPO         4
+#define CLK_FRC1_REMOTE         5
+#define CLK_LPC_0               6
+#define CLK_LPC_1               7
+#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 000000000000..2097a4bbe155
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES        32
+#define CLK_RX_ICN_HADES        33
+#define CLK_ICN_REG_16          34
+#define CLK_PP_HADES            35
+#define CLK_CLUST_HADES         36
+#define CLK_HWPE_HADES          37
+#define CLK_FC_HADES            38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER       4
+#define CLK_USB2_PHY            5
+
+#endif
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index fc12621fb432..534c03f8ad72 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
 #define TEGRA114_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA114_CLK_MC 32
 /* 33 */
 #define TEGRA114_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 6bac637fd635..af9bc9a3ddbc 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -48,7 +48,7 @@
 #define TEGRA124_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA124_CLK_MC 32
 /* 33 */
 #define TEGRA124_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index 9406207cfac8..04500b243a4d 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
 /* 30 */
 #define TEGRA20_CLK_CACHE2 31
 
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
 #define TEGRA20_CLK_AHBDMA 33
 #define TEGRA20_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
new file mode 100644
index 000000000000..8f48985a3139
--- /dev/null
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -0,0 +1,25 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_EPP       3
+#define TEGRA_SWGROUP_G2        4
+#define TEGRA_SWGROUP_AVPC      5
+#define TEGRA_SWGROUP_NV        6
+#define TEGRA_SWGROUP_HDA       7
+#define TEGRA_SWGROUP_HC        8
+#define TEGRA_SWGROUP_MSENC     9
+#define TEGRA_SWGROUP_PPCS      10
+#define TEGRA_SWGROUP_VDE       11
+#define TEGRA_SWGROUP_MPCORELP  12
+#define TEGRA_SWGROUP_MPCORE    13
+#define TEGRA_SWGROUP_VI        14
+#define TEGRA_SWGROUP_ISP       15
+#define TEGRA_SWGROUP_XUSB_HOST 16
+#define TEGRA_SWGROUP_XUSB_DEV  17
+#define TEGRA_SWGROUP_EMUCIF    18
+#define TEGRA_SWGROUP_TSEC      19
+
+#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
new file mode 100644
index 000000000000..7d8ee798f34e
--- /dev/null
+++ b/include/dt-bindings/memory/tegra124-mc.h
@@ -0,0 +1,31 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_AFI       3
+#define TEGRA_SWGROUP_AVPC      4
+#define TEGRA_SWGROUP_HDA       5
+#define TEGRA_SWGROUP_HC        6
+#define TEGRA_SWGROUP_MSENC     7
+#define TEGRA_SWGROUP_PPCS      8
+#define TEGRA_SWGROUP_SATA      9
+#define TEGRA_SWGROUP_VDE       10
+#define TEGRA_SWGROUP_MPCORELP  11
+#define TEGRA_SWGROUP_MPCORE    12
+#define TEGRA_SWGROUP_ISP2      13
+#define TEGRA_SWGROUP_XUSB_HOST 14
+#define TEGRA_SWGROUP_XUSB_DEV  15
+#define TEGRA_SWGROUP_ISP2B     16
+#define TEGRA_SWGROUP_TSEC      17
+#define TEGRA_SWGROUP_A9AVP     18
+#define TEGRA_SWGROUP_GPU       19
+#define TEGRA_SWGROUP_SDMMC1A   20
+#define TEGRA_SWGROUP_SDMMC2A   21
+#define TEGRA_SWGROUP_SDMMC3A   22
+#define TEGRA_SWGROUP_SDMMC4A   23
+#define TEGRA_SWGROUP_VIC       24
+#define TEGRA_SWGROUP_VI        25
+
+#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
new file mode 100644
index 000000000000..502beb03d777
--- /dev/null
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -0,0 +1,24 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_EPP       3
+#define TEGRA_SWGROUP_G2        4
+#define TEGRA_SWGROUP_MPE       5
+#define TEGRA_SWGROUP_VI        6
+#define TEGRA_SWGROUP_AFI       7
+#define TEGRA_SWGROUP_AVPC      8
+#define TEGRA_SWGROUP_NV        9
+#define TEGRA_SWGROUP_NV2       10
+#define TEGRA_SWGROUP_HDA       11
+#define TEGRA_SWGROUP_HC        12
+#define TEGRA_SWGROUP_PPCS      13
+#define TEGRA_SWGROUP_SATA      14
+#define TEGRA_SWGROUP_VDE       15
+#define TEGRA_SWGROUP_MPCORELP  16
+#define TEGRA_SWGROUP_MPCORE    17
+#define TEGRA_SWGROUP_ISP       18
+
+#endif
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
new file mode 100644
index 000000000000..cf28631d7109
--- /dev/null
+++ b/include/dt-bindings/regulator/maxim,max77802.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for the Maxim 77802 PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+
+/* Regulator operating modes */
+#define MAX77802_OPMODE_LP      1
+#define MAX77802_OPMODE_NORMAL  3
+
+#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
diff --git a/include/dt-bindings/reset-controller/stih407-resets.h b/include/dt-bindings/reset-controller/stih407-resets.h
new file mode 100644
index 000000000000..02d4328fe479
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih407-resets.h
@@ -0,0 +1,61 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
+
+/* Powerdown requests control 0 */
+#define STIH407_EMISS_POWERDOWN         0
+#define STIH407_NAND_POWERDOWN          1
+
+/* Synp GMAC PowerDown */
+#define STIH407_ETH1_POWERDOWN          2
+
+/* Powerdown requests control 1 */
+#define STIH407_USB3_POWERDOWN          3
+#define STIH407_USB2_PORT1_POWERDOWN    4
+#define STIH407_USB2_PORT0_POWERDOWN    5
+#define STIH407_PCIE1_POWERDOWN         6
+#define STIH407_PCIE0_POWERDOWN         7
+#define STIH407_SATA1_POWERDOWN         8
+#define STIH407_SATA0_POWERDOWN         9
+
+/* Reset defines */
+#define STIH407_ETH1_SOFTRESET          0
+#define STIH407_MMC1_SOFTRESET          1
+#define STIH407_PICOPHY_SOFTRESET       2
+#define STIH407_IRB_SOFTRESET           3
+#define STIH407_PCIE0_SOFTRESET         4
+#define STIH407_PCIE1_SOFTRESET         5
+#define STIH407_SATA0_SOFTRESET         6
+#define STIH407_SATA1_SOFTRESET         7
+#define STIH407_MIPHY0_SOFTRESET        8
+#define STIH407_MIPHY1_SOFTRESET        9
+#define STIH407_MIPHY2_SOFTRESET        10
+#define STIH407_SATA0_PWR_SOFTRESET     11
+#define STIH407_SATA1_PWR_SOFTRESET     12
+#define STIH407_DELTA_SOFTRESET         13
+#define STIH407_BLITTER_SOFTRESET       14
+#define STIH407_HDTVOUT_SOFTRESET       15
+#define STIH407_HDQVDP_SOFTRESET        16
+#define STIH407_VDP_AUX_SOFTRESET       17
+#define STIH407_COMPO_SOFTRESET         18
+#define STIH407_HDMI_TX_PHY_SOFTRESET   19
+#define STIH407_JPEG_DEC_SOFTRESET      20
+#define STIH407_VP8_DEC_SOFTRESET       21
+#define STIH407_GPU_SOFTRESET           22
+#define STIH407_HVA_SOFTRESET           23
+#define STIH407_ERAM_HVA_SOFTRESET      24
+#define STIH407_LPM_SOFTRESET           25
+#define STIH407_KEYSCAN_SOFTRESET       26
+#define STIH407_USB2_PORT0_SOFTRESET    27
+#define STIH407_USB2_PORT1_SOFTRESET    28
+
+/* Picophy reset defines */
+#define STIH407_PICOPHY0_RESET          0
+#define STIH407_PICOPHY1_RESET          1
+#define STIH407_PICOPHY2_RESET          2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
diff --git a/include/linux/atmel-mci.h b/include/linux/atmel-mci.h
index 91b77f8d495d..9177947bf032 100644
--- a/include/linux/atmel-mci.h
+++ b/include/linux/atmel-mci.h
@@ -11,6 +11,7 @@
  * @detect_pin: GPIO pin wired to the card detect switch
  * @wp_pin: GPIO pin wired to the write protect sensor
  * @detect_is_active_high: The state of the detect pin when it is active
+ * @non_removable: The slot is not removable, only detect once
  *
  * If a given slot is not present on the board, @bus_width should be
  * set to 0. The other fields are ignored in this case.
@@ -26,6 +27,7 @@ struct mci_slot_pdata {
         int                     detect_pin;
         int                     wp_pin;
         bool                    detect_is_active_high;
+        bool                    non_removable;
 };
 
 /**
diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h
index c9be1589415a..15f7034aa377 100644
--- a/include/linux/blk-mq.h
+++ b/include/linux/blk-mq.h
@@ -167,6 +167,23 @@ struct request *blk_mq_alloc_request(struct request_queue *q, int rw,
                 gfp_t gfp, bool reserved);
 struct request *blk_mq_tag_to_rq(struct blk_mq_tags *tags, unsigned int tag);
 
+enum {
+        BLK_MQ_UNIQUE_TAG_BITS = 16,
+        BLK_MQ_UNIQUE_TAG_MASK = (1 << BLK_MQ_UNIQUE_TAG_BITS) - 1,
+};
+
+u32 blk_mq_unique_tag(struct request *rq);
+
+static inline u16 blk_mq_unique_tag_to_hwq(u32 unique_tag)
+{
+        return unique_tag >> BLK_MQ_UNIQUE_TAG_BITS;
+}
+
+static inline u16 blk_mq_unique_tag_to_tag(u32 unique_tag)
+{
+        return unique_tag & BLK_MQ_UNIQUE_TAG_MASK;
+}
+
 struct blk_mq_hw_ctx *blk_mq_map_queue(struct request_queue *, const int ctx_index);
 struct blk_mq_hw_ctx *blk_mq_alloc_single_hw_queue(struct blk_mq_tag_set *, unsigned int, int);
 
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index aac0f9ea952a..6d76b8b4aa2b 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -1136,7 +1136,6 @@ static inline bool blk_needs_flush_plug(struct task_struct *tsk)
 /*
  * tag stuff
  */
-#define blk_rq_tagged(rq)               ((rq)->cmd_flags & REQ_QUEUED)
 extern int blk_queue_start_tag(struct request_queue *, struct request *);
 extern struct request *blk_queue_find_tag(struct request_queue *, int);
 extern void blk_queue_end_tag(struct request_queue *, struct request *);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index be21af149f11..2839c639f092 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -352,7 +352,6 @@ struct clk_divider {
 #define CLK_DIVIDER_READ_ONLY           BIT(5)
 
 extern const struct clk_ops clk_divider_ops;
-extern const struct clk_ops clk_divider_ro_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index f75acbf70e96..74e5341463c9 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -254,13 +254,26 @@ extern const struct clk_ops ti_clk_mux_ops;
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long parent_rate);
+int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
+                                           unsigned long rate,
+                                           unsigned long parent_rate,
+                                           u8 index);
+long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
+                                       unsigned long rate,
+                                       unsigned long *best_parent_rate,
+                                       struct clk **best_parent_clk);
 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
                                          unsigned long parent_rate);
 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
                                     unsigned long target_rate,
                                     unsigned long *parent_rate);
+long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
+                                        unsigned long rate,
+                                        unsigned long *best_parent_rate,
+                                        struct clk **best_parent_clk);
 u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
@@ -278,6 +291,8 @@ int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
                          unsigned long parent_rate);
+int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long parent_rate, u8 index);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
 void omap2_dflt_clk_disable(struct clk_hw *hw);
 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h
index e1707de043ae..ca6d2acc5eb7 100644
--- a/include/linux/device-mapper.h
+++ b/include/linux/device-mapper.h
@@ -64,6 +64,7 @@ typedef int (*dm_request_endio_fn) (struct dm_target *ti,
                                     union map_info *map_context);
 
 typedef void (*dm_presuspend_fn) (struct dm_target *ti);
+typedef void (*dm_presuspend_undo_fn) (struct dm_target *ti);
 typedef void (*dm_postsuspend_fn) (struct dm_target *ti);
 typedef int (*dm_preresume_fn) (struct dm_target *ti);
 typedef void (*dm_resume_fn) (struct dm_target *ti);
@@ -145,6 +146,7 @@ struct target_type {
         dm_endio_fn end_io;
         dm_request_endio_fn rq_end_io;
         dm_presuspend_fn presuspend;
+        dm_presuspend_undo_fn presuspend_undo;
         dm_postsuspend_fn postsuspend;
         dm_preresume_fn preresume;
         dm_resume_fn resume;
diff --git a/include/linux/edac.h b/include/linux/edac.h
index e1e68da6f35c..da3b72e95db3 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -194,7 +194,8 @@ static inline char *mc_event_error_type(const unsigned int err_type)
  * @MEM_DDR3:           DDR3 RAM
  * @MEM_RDDR3:          Registered DDR3 RAM
  *                      This is a variant of the DDR3 memories.
- * @MEM_DDR4:           DDR4 RAM
+ * @MEM_LRDDR3          Load-Reduced DDR3 memory.
+ * @MEM_DDR4:           Unbuffered DDR4 RAM
  * @MEM_RDDR4:          Registered DDR4 RAM
  *                      This is a variant of the DDR4 memories.
  */
@@ -216,6 +217,7 @@ enum mem_type {
         MEM_XDR,
         MEM_DDR3,
         MEM_RDDR3,
+        MEM_LRDDR3,
         MEM_DDR4,
         MEM_RDDR4,
 };
diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h
index e50f98b0297a..eb0b1988050a 100644
--- a/include/linux/eeprom_93cx6.h
+++ b/include/linux/eeprom_93cx6.h
@@ -75,6 +75,10 @@ extern void eeprom_93cx6_read(struct eeprom_93cx6 *eeprom,
         const u8 word, u16 *data);
 extern void eeprom_93cx6_multiread(struct eeprom_93cx6 *eeprom,
         const u8 word, __le16 *data, const u16 words);
+extern void eeprom_93cx6_readb(struct eeprom_93cx6 *eeprom,
+        const u8 byte, u8 *data);
+extern void eeprom_93cx6_multireadb(struct eeprom_93cx6 *eeprom,
+        const u8 byte, u8 *data, const u16 bytes);
 
 extern void eeprom_93cx6_wren(struct eeprom_93cx6 *eeprom, bool enable);
 
diff --git a/include/linux/efi.h b/include/linux/efi.h
index 0949f9c7e872..0238d612750e 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -547,6 +547,9 @@ void efi_native_runtime_setup(void);
 #define SMBIOS_TABLE_GUID    \
     EFI_GUID(  0xeb9d2d31, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d )
 
+#define SMBIOS3_TABLE_GUID    \
+    EFI_GUID(  0xf2fd1544, 0x9794, 0x4a2c, 0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 )
+
 #define SAL_SYSTEM_TABLE_GUID    \
     EFI_GUID(  0xeb9d2d32, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d )
 
@@ -810,7 +813,8 @@ extern struct efi {
         unsigned long mps;              /* MPS table */
         unsigned long acpi;             /* ACPI table  (IA64 ext 0.71) */
         unsigned long acpi20;           /* ACPI table  (ACPI 2.0) */
-        unsigned long smbios;           /* SM BIOS table */
+        unsigned long smbios;           /* SMBIOS table (32 bit entry point) */
+        unsigned long smbios3;          /* SMBIOS table (64 bit entry point) */
         unsigned long sal_systab;       /* SAL system table */
         unsigned long boot_info;        /* boot info table */
         unsigned long hcdp;             /* HCDP table */
diff --git a/include/linux/i2c/pmbus.h b/include/linux/i2c/pmbus.h
index 69280db02c41..ee3c2aba2a8e 100644
--- a/include/linux/i2c/pmbus.h
+++ b/include/linux/i2c/pmbus.h
@@ -40,6 +40,10 @@
 
 struct pmbus_platform_data {
         u32 flags;              /* Device specific flags */
+
+        /* regulator support */
+        int num_regulators;
+        struct regulator_init_data *reg_init_data;
 };
 
 #endif /* _PMBUS_H_ */
diff --git a/include/linux/iio/events.h b/include/linux/iio/events.h
index 8bbd7bc1043d..03fa332ad2a8 100644
--- a/include/linux/iio/events.h
+++ b/include/linux/iio/events.h
@@ -72,7 +72,7 @@ struct iio_event_data {
 
 #define IIO_EVENT_CODE_EXTRACT_TYPE(mask) ((mask >> 56) & 0xFF)
 
-#define IIO_EVENT_CODE_EXTRACT_DIR(mask) ((mask >> 48) & 0xCF)
+#define IIO_EVENT_CODE_EXTRACT_DIR(mask) ((mask >> 48) & 0x7F)
 
 #define IIO_EVENT_CODE_EXTRACT_CHAN_TYPE(mask) ((mask >> 32) & 0xFF)
 
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 77fc43f8fb72..d996aef8044f 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -102,7 +102,7 @@ extern struct group_info init_groups;
 #define INIT_IDS
 #endif
 
-#ifdef CONFIG_TREE_PREEMPT_RCU
+#ifdef CONFIG_PREEMPT_RCU
 #define INIT_TASK_RCU_TREE_PREEMPT()                                    \
         .rcu_blocked_node = NULL,
 #else
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e6a7c9ff72f2..b29a5982e1c3 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/types.h>
+#include <linux/scatterlist.h>
 #include <trace/events/iommu.h>
 
 #define IOMMU_READ      (1 << 0)
@@ -97,6 +98,8 @@ enum iommu_attr {
  * @detach_dev: detach device from an iommu domain
  * @map: map a physically contiguous memory region to an iommu domain
  * @unmap: unmap a physically contiguous memory region from an iommu domain
+ * @map_sg: map a scatter-gather list of physically contiguous memory chunks
+ * to an iommu domain
  * @iova_to_phys: translate iova to physical address
  * @add_device: add device to iommu grouping
  * @remove_device: remove device from iommu grouping
@@ -114,6 +117,8 @@ struct iommu_ops {
                    phys_addr_t paddr, size_t size, int prot);
         size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
                      size_t size);
+        size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova,
+                         struct scatterlist *sg, unsigned int nents, int prot);
         phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova);
         int (*add_device)(struct device *dev);
         void (*remove_device)(struct device *dev);
@@ -156,6 +161,9 @@ extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
                      phys_addr_t paddr, size_t size, int prot);
 extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
                        size_t size);
+extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
+                                struct scatterlist *sg,unsigned int nents,
+                                int prot);
 extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
 extern void iommu_set_fault_handler(struct iommu_domain *domain,
                         iommu_fault_handler_t handler, void *token);
@@ -241,6 +249,13 @@ static inline int report_iommu_fault(struct iommu_domain *domain,
         return ret;
 }
 
+static inline size_t iommu_map_sg(struct iommu_domain *domain,
+                                  unsigned long iova, struct scatterlist *sg,
+                                  unsigned int nents, int prot)
+{
+        return domain->ops->map_sg(domain, iova, sg, nents, prot);
+}
+
 #else /* CONFIG_IOMMU_API */
 
 struct iommu_ops {};
@@ -293,6 +308,13 @@ static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova,
         return -ENODEV;
 }
 
+static inline size_t iommu_map_sg(struct iommu_domain *domain,
+                                  unsigned long iova, struct scatterlist *sg,
+                                  unsigned int nents, int prot)
+{
+        return -ENODEV;
+}
+
 static inline int iommu_domain_window_enable(struct iommu_domain *domain,
                                              u32 wnd_nr, phys_addr_t paddr,
                                              u64 size, int prot)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index ea53b04993f2..a6059bdf7b03 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -703,7 +703,7 @@ void kvm_arch_sync_events(struct kvm *kvm);
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu);
 void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
 
-bool kvm_is_mmio_pfn(pfn_t pfn);
+bool kvm_is_reserved_pfn(pfn_t pfn);
 
 struct kvm_irq_ack_notifier {
         struct hlist_node link;
diff --git a/include/linux/libata.h b/include/linux/libata.h
index bd5fefeaf548..bfbc817c34ee 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -1191,9 +1191,9 @@ extern void ata_scsi_unlock_native_capacity(struct scsi_device *sdev);
 extern int ata_scsi_slave_config(struct scsi_device *sdev);
 extern void ata_scsi_slave_destroy(struct scsi_device *sdev);
 extern int ata_scsi_change_queue_depth(struct scsi_device *sdev,
-                                       int queue_depth, int reason);
+                                       int queue_depth);
 extern int __ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
-                                    int queue_depth, int reason);
+                                    int queue_depth);
 extern struct ata_device *ata_dev_pair(struct ata_device *adev);
 extern int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev);
 extern void ata_scsi_port_error_handler(struct Scsi_Host *host, struct ata_port *ap);
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index 550c88fb0267..611b69fa8594 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -61,6 +61,7 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
 }
 #endif
 
+int mvebu_mbus_save_cpu_target(u32 *store_addr);
 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
 void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index adba89d9c660..689312745b2f 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -12,7 +12,6 @@
 
 int ab8500_sysctrl_read(u16 reg, u8 *value);
 int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
-void ab8500_restart(char mode, const char *cmd);
 
 #else
 
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index c0b075f6bc35..aacc10d7789c 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -125,6 +125,8 @@
 #define ARIZONA_MIC_BIAS_CTRL_1                  0x218
 #define ARIZONA_MIC_BIAS_CTRL_2                  0x219
 #define ARIZONA_MIC_BIAS_CTRL_3                  0x21A
+#define ARIZONA_HP_CTRL_1L                       0x225
+#define ARIZONA_HP_CTRL_1R                       0x226
 #define ARIZONA_ACCESSORY_DETECT_MODE_1          0x293
 #define ARIZONA_HEADPHONE_DETECT_1               0x29B
 #define ARIZONA_HEADPHONE_DETECT_2               0x29C
@@ -279,8 +281,16 @@
 #define ARIZONA_AIF2_FRAME_CTRL_2                0x548
 #define ARIZONA_AIF2_FRAME_CTRL_3                0x549
 #define ARIZONA_AIF2_FRAME_CTRL_4                0x54A
+#define ARIZONA_AIF2_FRAME_CTRL_5                0x54B
+#define ARIZONA_AIF2_FRAME_CTRL_6                0x54C
+#define ARIZONA_AIF2_FRAME_CTRL_7                0x54D
+#define ARIZONA_AIF2_FRAME_CTRL_8                0x54E
 #define ARIZONA_AIF2_FRAME_CTRL_11               0x551
 #define ARIZONA_AIF2_FRAME_CTRL_12               0x552
+#define ARIZONA_AIF2_FRAME_CTRL_13               0x553
+#define ARIZONA_AIF2_FRAME_CTRL_14               0x554
+#define ARIZONA_AIF2_FRAME_CTRL_15               0x555
+#define ARIZONA_AIF2_FRAME_CTRL_16               0x556
 #define ARIZONA_AIF2_TX_ENABLES                  0x559
 #define ARIZONA_AIF2_RX_ENABLES                  0x55A
 #define ARIZONA_AIF2_FORCE_WRITE                 0x55B
@@ -2245,6 +2255,46 @@
 #define ARIZONA_MICB3_ENA_WIDTH                       1  /* MICB3_ENA */
 
 /*
+ * R549 (0x225) - HP Ctrl 1L
+ */
+#define ARIZONA_RMV_SHRT_HP1L                    0x4000  /* RMV_SHRT_HP1L */
+#define ARIZONA_RMV_SHRT_HP1L_MASK               0x4000  /* RMV_SHRT_HP1L */
+#define ARIZONA_RMV_SHRT_HP1L_SHIFT                  14  /* RMV_SHRT_HP1L */
+#define ARIZONA_RMV_SHRT_HP1L_WIDTH                   1  /* RMV_SHRT_HP1L */
+#define ARIZONA_HP1L_FLWR                        0x0004  /* HP1L_FLWR */
+#define ARIZONA_HP1L_FLWR_MASK                   0x0004  /* HP1L_FLWR */
+#define ARIZONA_HP1L_FLWR_SHIFT                       2  /* HP1L_FLWR */
+#define ARIZONA_HP1L_FLWR_WIDTH                       1  /* HP1L_FLWR */
+#define ARIZONA_HP1L_SHRTI                       0x0002  /* HP1L_SHRTI */
+#define ARIZONA_HP1L_SHRTI_MASK                  0x0002  /* HP1L_SHRTI */
+#define ARIZONA_HP1L_SHRTI_SHIFT                      1  /* HP1L_SHRTI */
+#define ARIZONA_HP1L_SHRTI_WIDTH                      1  /* HP1L_SHRTI */
+#define ARIZONA_HP1L_SHRTO                       0x0001  /* HP1L_SHRTO */
+#define ARIZONA_HP1L_SHRTO_MASK                  0x0001  /* HP1L_SHRTO */
+#define ARIZONA_HP1L_SHRTO_SHIFT                      0  /* HP1L_SHRTO */
+#define ARIZONA_HP1L_SHRTO_WIDTH                      1  /* HP1L_SHRTO */
+
+/*
+ * R550 (0x226) - HP Ctrl 1R
+ */
+#define ARIZONA_RMV_SHRT_HP1R                    0x4000  /* RMV_SHRT_HP1R */
+#define ARIZONA_RMV_SHRT_HP1R_MASK               0x4000  /* RMV_SHRT_HP1R */
+#define ARIZONA_RMV_SHRT_HP1R_SHIFT                  14  /* RMV_SHRT_HP1R */
+#define ARIZONA_RMV_SHRT_HP1R_WIDTH                   1  /* RMV_SHRT_HP1R */
+#define ARIZONA_HP1R_FLWR                        0x0004  /* HP1R_FLWR */
+#define ARIZONA_HP1R_FLWR_MASK                   0x0004  /* HP1R_FLWR */
+#define ARIZONA_HP1R_FLWR_SHIFT                       2  /* HP1R_FLWR */
+#define ARIZONA_HP1R_FLWR_WIDTH                       1  /* HP1R_FLWR */
+#define ARIZONA_HP1R_SHRTI                       0x0002  /* HP1R_SHRTI */
+#define ARIZONA_HP1R_SHRTI_MASK                  0x0002  /* HP1R_SHRTI */
+#define ARIZONA_HP1R_SHRTI_SHIFT                      1  /* HP1R_SHRTI */
+#define ARIZONA_HP1R_SHRTI_WIDTH                      1  /* HP1R_SHRTI */
+#define ARIZONA_HP1R_SHRTO                       0x0001  /* HP1R_SHRTO */
+#define ARIZONA_HP1R_SHRTO_MASK                  0x0001  /* HP1R_SHRTO */
+#define ARIZONA_HP1R_SHRTO_SHIFT                      0  /* HP1R_SHRTO */
+#define ARIZONA_HP1R_SHRTO_WIDTH                      1  /* HP1R_SHRTO */
+
+/*
  * R659 (0x293) - Accessory Detect Mode 1
  */
 #define ARIZONA_ACCDET_SRC                       0x2000  /* ACCDET_SRC */
diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h
new file mode 100644
index 000000000000..1279ab1644b5
--- /dev/null
+++ b/include/linux/mfd/atmel-hlcdc.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ * Copyright (C) 2014 Atmel
+ *
+ * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_MFD_HLCDC_H
+#define __LINUX_MFD_HLCDC_H
+
+#include <linux/clk.h>
+#include <linux/regmap.h>
+
+#define ATMEL_HLCDC_CFG(i)              ((i) * 0x4)
+#define ATMEL_HLCDC_SIG_CFG             LCDCFG(5)
+#define ATMEL_HLCDC_HSPOL               BIT(0)
+#define ATMEL_HLCDC_VSPOL               BIT(1)
+#define ATMEL_HLCDC_VSPDLYS             BIT(2)
+#define ATMEL_HLCDC_VSPDLYE             BIT(3)
+#define ATMEL_HLCDC_DISPPOL             BIT(4)
+#define ATMEL_HLCDC_DITHER              BIT(6)
+#define ATMEL_HLCDC_DISPDLY             BIT(7)
+#define ATMEL_HLCDC_MODE_MASK           GENMASK(9, 8)
+#define ATMEL_HLCDC_PP                  BIT(10)
+#define ATMEL_HLCDC_VSPSU               BIT(12)
+#define ATMEL_HLCDC_VSPHO               BIT(13)
+#define ATMEL_HLCDC_GUARDTIME_MASK      GENMASK(20, 16)
+
+#define ATMEL_HLCDC_EN                  0x20
+#define ATMEL_HLCDC_DIS                 0x24
+#define ATMEL_HLCDC_SR                  0x28
+#define ATMEL_HLCDC_IER                 0x2c
+#define ATMEL_HLCDC_IDR                 0x30
+#define ATMEL_HLCDC_IMR                 0x34
+#define ATMEL_HLCDC_ISR                 0x38
+
+#define ATMEL_HLCDC_CLKPOL              BIT(0)
+#define ATMEL_HLCDC_CLKSEL              BIT(2)
+#define ATMEL_HLCDC_CLKPWMSEL           BIT(3)
+#define ATMEL_HLCDC_CGDIS(i)            BIT(8 + (i))
+#define ATMEL_HLCDC_CLKDIV_SHFT         16
+#define ATMEL_HLCDC_CLKDIV_MASK         GENMASK(23, 16)
+#define ATMEL_HLCDC_CLKDIV(div)         ((div - 2) << ATMEL_HLCDC_CLKDIV_SHFT)
+
+#define ATMEL_HLCDC_PIXEL_CLK           BIT(0)
+#define ATMEL_HLCDC_SYNC                BIT(1)
+#define ATMEL_HLCDC_DISP                BIT(2)
+#define ATMEL_HLCDC_PWM                 BIT(3)
+#define ATMEL_HLCDC_SIP                 BIT(4)
+
+#define ATMEL_HLCDC_SOF                 BIT(0)
+#define ATMEL_HLCDC_SYNCDIS             BIT(1)
+#define ATMEL_HLCDC_FIFOERR             BIT(4)
+#define ATMEL_HLCDC_LAYER_STATUS(x)     BIT((x) + 8)
+
+/**
+ * Structure shared by the MFD device and its subdevices.
+ *
+ * @regmap: register map used to access HLCDC IP registers
+ * @periph_clk: the hlcdc peripheral clock
+ * @sys_clk: the hlcdc system clock
+ * @slow_clk: the system slow clk
+ * @irq: the hlcdc irq
+ */
+struct atmel_hlcdc {
+        struct regmap *regmap;
+        struct clk *periph_clk;
+        struct clk *sys_clk;
+        struct clk *slow_clk;
+        int irq;
+};
+
+#endif /* __LINUX_MFD_HLCDC_H */
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index d0e31a2287ac..81589d176ae8 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -14,6 +14,8 @@
 enum {
         AXP202_ID = 0,
         AXP209_ID,
+        AXP288_ID,
+        NR_AXP20X_VARIANTS,
 };
 
 #define AXP20X_DATACACHE(m)             (0x04 + (m))
@@ -49,11 +51,13 @@ enum {
 #define AXP20X_IRQ3_EN                  0x42
 #define AXP20X_IRQ4_EN                  0x43
 #define AXP20X_IRQ5_EN                  0x44
+#define AXP20X_IRQ6_EN                  0x45
 #define AXP20X_IRQ1_STATE               0x48
 #define AXP20X_IRQ2_STATE               0x49
 #define AXP20X_IRQ3_STATE               0x4a
 #define AXP20X_IRQ4_STATE               0x4b
 #define AXP20X_IRQ5_STATE               0x4c
+#define AXP20X_IRQ6_STATE               0x4d
 
 /* ADC */
 #define AXP20X_ACIN_V_ADC_H             0x56
@@ -116,6 +120,15 @@ enum {
 #define AXP20X_CC_CTRL                  0xb8
 #define AXP20X_FG_RES                   0xb9
 
+/* AXP288 specific registers */
+#define AXP288_PMIC_ADC_H               0x56
+#define AXP288_PMIC_ADC_L               0x57
+#define AXP288_ADC_TS_PIN_CTRL          0x84
+
+#define AXP288_PMIC_ADC_EN              0x84
+#define AXP288_FG_TUNE5                 0xed
+
+
 /* Regulators IDs */
 enum {
         AXP20X_LDO1 = 0,
@@ -169,12 +182,58 @@ enum {
         AXP20X_IRQ_GPIO0_INPUT,
 };
 
+enum axp288_irqs {
+        AXP288_IRQ_VBUS_FALL     = 2,
+        AXP288_IRQ_VBUS_RISE,
+        AXP288_IRQ_OV,
+        AXP288_IRQ_FALLING_ALT,
+        AXP288_IRQ_RISING_ALT,
+        AXP288_IRQ_OV_ALT,
+        AXP288_IRQ_DONE          = 10,
+        AXP288_IRQ_CHARGING,
+        AXP288_IRQ_SAFE_QUIT,
+        AXP288_IRQ_SAFE_ENTER,
+        AXP288_IRQ_ABSENT,
+        AXP288_IRQ_APPEND,
+        AXP288_IRQ_QWBTU,
+        AXP288_IRQ_WBTU,
+        AXP288_IRQ_QWBTO,
+        AXP288_IRQ_WBTO,
+        AXP288_IRQ_QCBTU,
+        AXP288_IRQ_CBTU,
+        AXP288_IRQ_QCBTO,
+        AXP288_IRQ_CBTO,
+        AXP288_IRQ_WL2,
+        AXP288_IRQ_WL1,
+        AXP288_IRQ_GPADC,
+        AXP288_IRQ_OT            = 31,
+        AXP288_IRQ_GPIO0,
+        AXP288_IRQ_GPIO1,
+        AXP288_IRQ_POKO,
+        AXP288_IRQ_POKL,
+        AXP288_IRQ_POKS,
+        AXP288_IRQ_POKN,
+        AXP288_IRQ_POKP,
+        AXP288_IRQ_TIMER,
+        AXP288_IRQ_MV_CHNG,
+        AXP288_IRQ_BC_USB_CHNG,
+};
+
+#define AXP288_TS_ADC_H         0x58
+#define AXP288_TS_ADC_L         0x59
+#define AXP288_GP_ADC_H         0x5a
+#define AXP288_GP_ADC_L         0x5b
+
 struct axp20x_dev {
         struct device                   *dev;
         struct i2c_client               *i2c_client;
         struct regmap                   *regmap;
         struct regmap_irq_chip_data     *regmap_irqc;
         long                            variant;
+        int                             nr_cells;
+        struct mfd_cell                 *cells;
+        const struct regmap_config      *regmap_cfg;
+        const struct regmap_irq_chip    *regmap_irq_chip;
 };
 
 #endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index 73e1709d4c09..a76bc100bf97 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -111,6 +111,13 @@ extern int mfd_add_devices(struct device *parent, int id,
                            struct resource *mem_base,
                            int irq_base, struct irq_domain *irq_domain);
 
+static inline int mfd_add_hotplug_devices(struct device *parent,
+                const struct mfd_cell *cells, int n_devs)
+{
+        return mfd_add_devices(parent, PLATFORM_DEVID_AUTO, cells, n_devs,
+                        NULL, 0, NULL);
+}
+
 extern void mfd_remove_devices(struct device *parent);
 
 #endif
diff --git a/include/linux/mfd/dln2.h b/include/linux/mfd/dln2.h
new file mode 100644
index 000000000000..004b24576da8
--- /dev/null
+++ b/include/linux/mfd/dln2.h
@@ -0,0 +1,103 @@
+#ifndef __LINUX_USB_DLN2_H
+#define __LINUX_USB_DLN2_H
+
+#define DLN2_CMD(cmd, id)               ((cmd) | ((id) << 8))
+
+struct dln2_platform_data {
+        u16 handle;             /* sub-driver handle (internally used only) */
+        u8 port;                /* I2C/SPI port */
+};
+
+/**
+ * dln2_event_cb_t - event callback function signature
+ *
+ * @pdev - the sub-device that registered this callback
+ * @echo - the echo header field received in the message
+ * @data - the data payload
+ * @len  - the data payload length
+ *
+ * The callback function is called in interrupt context and the data payload is
+ * only valid during the call. If the user needs later access of the data, it
+ * must copy it.
+ */
+
+typedef void (*dln2_event_cb_t)(struct platform_device *pdev, u16 echo,
+                                const void *data, int len);
+
+/**
+ * dl2n_register_event_cb - register a callback function for an event
+ *
+ * @pdev - the sub-device that registers the callback
+ * @event - the event for which to register a callback
+ * @event_cb - the callback function
+ *
+ * @return 0 in case of success, negative value in case of error
+ */
+int dln2_register_event_cb(struct platform_device *pdev, u16 event,
+                           dln2_event_cb_t event_cb);
+
+/**
+ * dln2_unregister_event_cb - unregister the callback function for an event
+ *
+ * @pdev - the sub-device that registered the callback
+ * @event - the event for which to register a callback
+ */
+void dln2_unregister_event_cb(struct platform_device *pdev, u16 event);
+
+/**
+ * dln2_transfer - issue a DLN2 command and wait for a response and the
+ * associated data
+ *
+ * @pdev - the sub-device which is issuing this transfer
+ * @cmd - the command to be sent to the device
+ * @obuf - the buffer to be sent to the device; it can be NULL if the user
+ *      doesn't need to transmit data with this command
+ * @obuf_len - the size of the buffer to be sent to the device
+ * @ibuf - any data associated with the response will be copied here; it can be
+ *      NULL if the user doesn't need the response data
+ * @ibuf_len - must be initialized to the input buffer size; it will be modified
+ *      to indicate the actual data transferred;
+ *
+ * @return 0 for success, negative value for errors
+ */
+int dln2_transfer(struct platform_device *pdev, u16 cmd,
+                  const void *obuf, unsigned obuf_len,
+                  void *ibuf, unsigned *ibuf_len);
+
+/**
+ * dln2_transfer_rx - variant of @dln2_transfer() where TX buffer is not needed
+ *
+ * @pdev - the sub-device which is issuing this transfer
+ * @cmd - the command to be sent to the device
+ * @ibuf - any data associated with the response will be copied here; it can be
+ *      NULL if the user doesn't need the response data
+ * @ibuf_len - must be initialized to the input buffer size; it will be modified
+ *      to indicate the actual data transferred;
+ *
+ * @return 0 for success, negative value for errors
+ */
+
+static inline int dln2_transfer_rx(struct platform_device *pdev, u16 cmd,
+                                   void *ibuf, unsigned *ibuf_len)
+{
+        return dln2_transfer(pdev, cmd, NULL, 0, ibuf, ibuf_len);
+}
+
+/**
+ * dln2_transfer_tx - variant of @dln2_transfer() where RX buffer is not needed
+ *
+ * @pdev - the sub-device which is issuing this transfer
+ * @cmd - the command to be sent to the device
+ * @obuf - the buffer to be sent to the device; it can be NULL if the
+ *      user doesn't need to transmit data with this command
+ * @obuf_len - the size of the buffer to be sent to the device
+ *
+ * @return 0 for success, negative value for errors
+ */
+static inline int dln2_transfer_tx(struct platform_device *pdev, u16 cmd,
+                                   const void *obuf, unsigned obuf_len)
+{
+        return dln2_transfer(pdev, cmd, obuf, obuf_len, NULL, NULL);
+}
+
+#endif
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
index 7e6dc4b2b795..553f7d09258a 100644
--- a/include/linux/mfd/max77686.h
+++ b/include/linux/mfd/max77686.h
@@ -131,13 +131,6 @@ enum max77686_opmode {
         MAX77686_OPMODE_STANDBY,
 };
 
-enum max77802_opmode {
-        MAX77802_OPMODE_OFF,
-        MAX77802_OPMODE_STANDBY,
-        MAX77802_OPMODE_LP,
-        MAX77802_OPMODE_NORMAL,
-};
-
 struct max77686_opmode_data {
         int id;
         int mode;
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 582e67f34054..08dae01258b9 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -26,7 +26,6 @@
 
 #include <linux/i2c.h>
 
-#define MAX77693_NUM_IRQ_MUIC_REGS      3
 #define MAX77693_REG_INVALID            (0xff)
 
 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 74346d5e7899..0c12628e91c6 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -558,6 +558,7 @@
 #define SD_SAMPLE_POINT_CTL             0xFDA7
 #define SD_PUSH_POINT_CTL               0xFDA8
 #define SD_CMD0                         0xFDA9
+#define   SD_CMD_START                  0x40
 #define SD_CMD1                         0xFDAA
 #define SD_CMD2                         0xFDAB
 #define SD_CMD3                         0xFDAC
@@ -707,6 +708,14 @@
 #define PM_CTRL1                        0xFF44
 #define PM_CTRL2                        0xFF45
 #define PM_CTRL3                        0xFF46
+#define   SDIO_SEND_PME_EN              0x80
+#define   FORCE_RC_MODE_ON              0x40
+#define   FORCE_RX50_LINK_ON            0x20
+#define   D3_DELINK_MODE_EN             0x10
+#define   USE_PESRTB_CTL_DELINK         0x08
+#define   DELAY_PIN_WAKE                0x04
+#define   RESET_PIN_WAKE                0x02
+#define   PM_WAKE_EN                    0x01
 #define PM_CTRL4                        0xFF47
 
 /* Memory mapping */
@@ -752,6 +761,14 @@
 #define PHY_DUM_REG                     0x1F
 
 #define LCTLR                           0x80
+#define   LCTLR_EXT_SYNC                0x80
+#define   LCTLR_COMMON_CLOCK_CFG        0x40
+#define   LCTLR_RETRAIN_LINK            0x20
+#define   LCTLR_LINK_DISABLE            0x10
+#define   LCTLR_RCB                     0x08
+#define   LCTLR_RESERVED                0x04
+#define   LCTLR_ASPM_CTL_MASK           0x03
+
 #define PCR_SETTING_REG1                0x724
 #define PCR_SETTING_REG2                0x814
 #define PCR_SETTING_REG3                0x747
@@ -967,4 +984,24 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
         return (u8 *)(pcr->host_cmds_ptr);
 }
 
+static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
+                u8 mask, u8 append)
+{
+        int err;
+        u8 val;
+
+        err = pci_read_config_byte(pcr->pci, addr, &val);
+        if (err < 0)
+                return err;
+        return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
+}
+
+static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
+{
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg,     0xFF, val >> 24);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
+}
+
 #endif
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 1825edacbda7..3fdb7cfbffb3 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -28,6 +28,7 @@
 #define MIN_800_MV              800000
 #define MIN_750_MV              750000
 #define MIN_600_MV              600000
+#define MIN_500_MV              500000
 
 /* Macros to represent steps for LDO/BUCK */
 #define STEP_50_MV              50000
@@ -41,6 +42,7 @@ enum sec_device_type {
         S5M8767X,
         S2MPA01,
         S2MPS11X,
+        S2MPS13X,
         S2MPS14X,
         S2MPU02,
 };
diff --git a/include/linux/mfd/samsung/s2mps13.h b/include/linux/mfd/samsung/s2mps13.h
new file mode 100644
index 000000000000..ce5dda8958fe
--- /dev/null
+++ b/include/linux/mfd/samsung/s2mps13.h
@@ -0,0 +1,186 @@
+/*
+ * s2mps13.h
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_MFD_S2MPS13_H
+#define __LINUX_MFD_S2MPS13_H
+
+/* S2MPS13 registers */
+enum s2mps13_reg {
+        S2MPS13_REG_ID,
+        S2MPS13_REG_INT1,
+        S2MPS13_REG_INT2,
+        S2MPS13_REG_INT3,
+        S2MPS13_REG_INT1M,
+        S2MPS13_REG_INT2M,
+        S2MPS13_REG_INT3M,
+        S2MPS13_REG_ST1,
+        S2MPS13_REG_ST2,
+        S2MPS13_REG_PWRONSRC,
+        S2MPS13_REG_OFFSRC,
+        S2MPS13_REG_BU_CHG,
+        S2MPS13_REG_RTCCTRL,
+        S2MPS13_REG_CTRL1,
+        S2MPS13_REG_CTRL2,
+        S2MPS13_REG_RSVD1,
+        S2MPS13_REG_RSVD2,
+        S2MPS13_REG_RSVD3,
+        S2MPS13_REG_RSVD4,
+        S2MPS13_REG_RSVD5,
+        S2MPS13_REG_RSVD6,
+        S2MPS13_REG_CTRL3,
+        S2MPS13_REG_RSVD7,
+        S2MPS13_REG_RSVD8,
+        S2MPS13_REG_WRSTBI,
+        S2MPS13_REG_B1CTRL,
+        S2MPS13_REG_B1OUT,
+        S2MPS13_REG_B2CTRL,
+        S2MPS13_REG_B2OUT,
+        S2MPS13_REG_B3CTRL,
+        S2MPS13_REG_B3OUT,
+        S2MPS13_REG_B4CTRL,
+        S2MPS13_REG_B4OUT,
+        S2MPS13_REG_B5CTRL,
+        S2MPS13_REG_B5OUT,
+        S2MPS13_REG_B6CTRL,
+        S2MPS13_REG_B6OUT,
+        S2MPS13_REG_B7CTRL,
+        S2MPS13_REG_B7OUT,
+        S2MPS13_REG_B8CTRL,
+        S2MPS13_REG_B8OUT,
+        S2MPS13_REG_B9CTRL,
+        S2MPS13_REG_B9OUT,
+        S2MPS13_REG_B10CTRL,
+        S2MPS13_REG_B10OUT,
+        S2MPS13_REG_BB1CTRL,
+        S2MPS13_REG_BB1OUT,
+        S2MPS13_REG_BUCK_RAMP1,
+        S2MPS13_REG_BUCK_RAMP2,
+        S2MPS13_REG_LDO_DVS1,
+        S2MPS13_REG_LDO_DVS2,
+        S2MPS13_REG_LDO_DVS3,
+        S2MPS13_REG_B6OUT2,
+        S2MPS13_REG_L1CTRL,
+        S2MPS13_REG_L2CTRL,
+        S2MPS13_REG_L3CTRL,
+        S2MPS13_REG_L4CTRL,
+        S2MPS13_REG_L5CTRL,
+        S2MPS13_REG_L6CTRL,
+        S2MPS13_REG_L7CTRL,
+        S2MPS13_REG_L8CTRL,
+        S2MPS13_REG_L9CTRL,
+        S2MPS13_REG_L10CTRL,
+        S2MPS13_REG_L11CTRL,
+        S2MPS13_REG_L12CTRL,
+        S2MPS13_REG_L13CTRL,
+        S2MPS13_REG_L14CTRL,
+        S2MPS13_REG_L15CTRL,
+        S2MPS13_REG_L16CTRL,
+        S2MPS13_REG_L17CTRL,
+        S2MPS13_REG_L18CTRL,
+        S2MPS13_REG_L19CTRL,
+        S2MPS13_REG_L20CTRL,
+        S2MPS13_REG_L21CTRL,
+        S2MPS13_REG_L22CTRL,
+        S2MPS13_REG_L23CTRL,
+        S2MPS13_REG_L24CTRL,
+        S2MPS13_REG_L25CTRL,
+        S2MPS13_REG_L26CTRL,
+        S2MPS13_REG_L27CTRL,
+        S2MPS13_REG_L28CTRL,
+        S2MPS13_REG_L30CTRL,
+        S2MPS13_REG_L31CTRL,
+        S2MPS13_REG_L32CTRL,
+        S2MPS13_REG_L33CTRL,
+        S2MPS13_REG_L34CTRL,
+        S2MPS13_REG_L35CTRL,
+        S2MPS13_REG_L36CTRL,
+        S2MPS13_REG_L37CTRL,
+        S2MPS13_REG_L38CTRL,
+        S2MPS13_REG_L39CTRL,
+        S2MPS13_REG_L40CTRL,
+        S2MPS13_REG_LDODSCH1,
+        S2MPS13_REG_LDODSCH2,
+        S2MPS13_REG_LDODSCH3,
+        S2MPS13_REG_LDODSCH4,
+        S2MPS13_REG_LDODSCH5,
+};
+
+/*  regulator ids */
+enum s2mps13_regulators {
+        S2MPS13_LDO1,
+        S2MPS13_LDO2,
+        S2MPS13_LDO3,
+        S2MPS13_LDO4,
+        S2MPS13_LDO5,
+        S2MPS13_LDO6,
+        S2MPS13_LDO7,
+        S2MPS13_LDO8,
+        S2MPS13_LDO9,
+        S2MPS13_LDO10,
+        S2MPS13_LDO11,
+        S2MPS13_LDO12,
+        S2MPS13_LDO13,
+        S2MPS13_LDO14,
+        S2MPS13_LDO15,
+        S2MPS13_LDO16,
+        S2MPS13_LDO17,
+        S2MPS13_LDO18,
+        S2MPS13_LDO19,
+        S2MPS13_LDO20,
+        S2MPS13_LDO21,
+        S2MPS13_LDO22,
+        S2MPS13_LDO23,
+        S2MPS13_LDO24,
+        S2MPS13_LDO25,
+        S2MPS13_LDO26,
+        S2MPS13_LDO27,
+        S2MPS13_LDO28,
+        S2MPS13_LDO29,
+        S2MPS13_LDO30,
+        S2MPS13_LDO31,
+        S2MPS13_LDO32,
+        S2MPS13_LDO33,
+        S2MPS13_LDO34,
+        S2MPS13_LDO35,
+        S2MPS13_LDO36,
+        S2MPS13_LDO37,
+        S2MPS13_LDO38,
+        S2MPS13_LDO39,
+        S2MPS13_LDO40,
+        S2MPS13_BUCK1,
+        S2MPS13_BUCK2,
+        S2MPS13_BUCK3,
+        S2MPS13_BUCK4,
+        S2MPS13_BUCK5,
+        S2MPS13_BUCK6,
+        S2MPS13_BUCK7,
+        S2MPS13_BUCK8,
+        S2MPS13_BUCK9,
+        S2MPS13_BUCK10,
+
+        S2MPS13_REGULATOR_MAX,
+};
+
+/*
+ * Default ramp delay in uv/us. Datasheet says that ramp delay can be
+ * controlled however it does not specify which register is used for that.
+ * Let's assume that default value will be set.
+ */
+#define S2MPS13_BUCK_RAMP_DELAY         12500
+
+#endif /*  __LINUX_MFD_S2MPS13_H */
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374a1a4e..c877cad61a13 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -395,4 +395,43 @@
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
 
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR1_VDEC_SW_RST_MASK                    (0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RESET                   (0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE                 (0x0 << 20)
+#define IMX6SX_GPR1_VADC_SW_RST_MASK                    (0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RESET                   (0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RELEASE                 (0x0 << 19)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK              (0x3 << 13)
+#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK              (0x3 << 17)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT               (0x3 << 13)
+
+#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ                  (0x1 << 3)
+#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ                  (0x1 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK              (0x1 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1            (0x0 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2            (0x1 << 3)
+
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK                  (0x3 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN               (0x0 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD                   (0x1 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI           (0x2 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND                   (0x3 << 27)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK         (0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE       (0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE      (0x0 << 26)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK                  (0x3 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN               (0x0 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD                   (0x1 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI           (0x2 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND                   (0x3 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2               (0x0 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS                 (0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK                 (0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1               (0x0 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS                 (0x1 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK                 (0x1 << 1)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h
index e6088c2e2092..e1c12d84c26a 100644
--- a/include/linux/mfd/tc3589x.h
+++ b/include/linux/mfd/tc3589x.h
@@ -164,13 +164,10 @@ struct tc3589x_keypad_platform_data {
 
 /**
  * struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
- * @gpio_base: first gpio number assigned to TC3589x.  A maximum of
- *             %TC3589x_NR_GPIOS GPIOs will be allocated.
  * @setup: callback for board-specific initialization
  * @remove: callback for board-specific teardown
  */
 struct tc3589x_gpio_platform_data {
-        int gpio_base;
         void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
         void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
 };
@@ -178,18 +175,13 @@ struct tc3589x_gpio_platform_data {
 /**
  * struct tc3589x_platform_data - TC3589x platform data
  * @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
- * @irq_base: base IRQ number.  %TC3589x_NR_IRQS irqs will be used.
  * @gpio: GPIO-specific platform data
  * @keypad: keypad-specific platform data
  */
 struct tc3589x_platform_data {
         unsigned int block;
-        int irq_base;
         struct tc3589x_gpio_platform_data *gpio;
         const struct tc3589x_keypad_platform_data *keypad;
 };
 
-#define TC3589x_NR_GPIOS        24
-#define TC3589x_NR_IRQS         TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
-
 #endif
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index b0692d28f8e6..4d69c00497bd 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -88,6 +88,9 @@ struct mmc_ext_csd {
         unsigned int            data_tag_unit_size;     /* DATA TAG UNIT size */
         unsigned int            boot_ro_lock;           /* ro lock support */
         bool                    boot_ro_lockable;
+        bool                    ffu_capable;    /* Firmware upgrade support */
+#define MMC_FIRMWARE_LEN 8
+        u8                      fwrev[MMC_FIRMWARE_LEN];  /* FW version */
         u8                      raw_exception_status;   /* 54 */
         u8                      raw_partition_support;  /* 160 */
         u8                      raw_rpmb_size_mult;     /* 168 */
@@ -509,24 +512,8 @@ static inline int mmc_card_broken_irq_polling(const struct mmc_card *c)
 
 #define mmc_dev_to_card(d)      container_of(d, struct mmc_card, dev)
 
-#define mmc_list_to_card(l)     container_of(l, struct mmc_card, node)
-#define mmc_get_drvdata(c)      dev_get_drvdata(&(c)->dev)
-#define mmc_set_drvdata(c,d)    dev_set_drvdata(&(c)->dev, d)
-
-/*
- * MMC device driver (e.g., Flash card, I/O card...)
- */
-struct mmc_driver {
-        struct device_driver drv;
-        int (*probe)(struct mmc_card *);
-        void (*remove)(struct mmc_card *);
-        int (*suspend)(struct mmc_card *);
-        int (*resume)(struct mmc_card *);
-        void (*shutdown)(struct mmc_card *);
-};
-
-extern int mmc_register_driver(struct mmc_driver *);
-extern void mmc_unregister_driver(struct mmc_driver *);
+extern int mmc_register_driver(struct device_driver *);
+extern void mmc_unregister_driver(struct device_driver *);
 
 extern void mmc_fixup_device(struct mmc_card *card,
                              const struct mmc_fixup *table);
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index f206e29f94d7..cb2b0400d284 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -154,7 +154,8 @@ extern void mmc_start_bkops(struct mmc_card *card, bool from_exception);
 extern int __mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int, bool,
                         bool, bool);
 extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
-extern int mmc_send_ext_csd(struct mmc_card *card, u8 *ext_csd);
+extern int mmc_send_tuning(struct mmc_host *host);
+extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd);
 
 #define MMC_ERASE_ARG           0x00000000
 #define MMC_SECURE_ERASE_ARG    0x80000000
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 001366927cf4..42b724e8d503 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -54,6 +54,7 @@ struct mmc_data;
  *      transfer is in progress.
  * @use_dma: Whether DMA channel is initialized or not.
  * @using_dma: Whether DMA is in use for the current transfer.
+ * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
  * @sg_dma: Bus address of DMA buffer.
  * @sg_cpu: Virtual address of DMA buffer.
  * @dma_ops: Pointer to platform-specific DMA callbacks.
@@ -96,6 +97,7 @@ struct mmc_data;
  * @quirks: Set of quirks that apply to specific versions of the IP.
  * @irq_flags: The flags to be passed to request_irq.
  * @irq: The irq value to be passed to request_irq.
+ * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
  *
  * Locking
  * =======
@@ -135,11 +137,11 @@ struct dw_mci {
         struct mmc_command      stop_abort;
         unsigned int            prev_blksz;
         unsigned char           timing;
-        struct workqueue_struct *card_workqueue;
 
         /* DMA interface members*/
         int                     use_dma;
         int                     using_dma;
+        int                     dma_64bit_address;
 
         dma_addr_t              sg_dma;
         void                    *sg_cpu;
@@ -154,7 +156,6 @@ struct dw_mci {
         u32                     stop_cmdr;
         u32                     dir_status;
         struct tasklet_struct   tasklet;
-        struct work_struct      card_work;
         unsigned long           pending_events;
         unsigned long           completed_events;
         enum dw_mci_state       state;
@@ -193,6 +194,8 @@ struct dw_mci {
         bool                    vqmmc_enabled;
         unsigned long           irq_flags; /* IRQ flags */
         int                     irq;
+
+        int                     sdio_id0;
 };
 
 /* DMA ops for Internal/External DMAC interface */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index df0c15396bbf..9f322706f7cb 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -289,6 +289,7 @@ struct mmc_host {
 #define MMC_CAP2_HS400_1_2V     (1 << 16)       /* Can support HS400 1.2V */
 #define MMC_CAP2_HS400          (MMC_CAP2_HS400_1_8V | \
                                  MMC_CAP2_HS400_1_2V)
+#define MMC_CAP2_HSX00_1_2V     (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
 
         mmc_pm_flag_t           pm_caps;        /* supported pm features */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 1cd00b3a75b9..49ad7a943638 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -296,6 +296,7 @@ struct _mmc_csd {
 #define EXT_CSD_SANITIZE_START          165     /* W */
 #define EXT_CSD_WR_REL_PARAM            166     /* RO */
 #define EXT_CSD_RPMB_MULT               168     /* RO */
+#define EXT_CSD_FW_CONFIG               169     /* R/W */
 #define EXT_CSD_BOOT_WP                 173     /* R/W */
 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 #define EXT_CSD_PART_CONFIG             179     /* R/W */
@@ -332,6 +333,8 @@ struct _mmc_csd {
 #define EXT_CSD_GENERIC_CMD6_TIME       248     /* RO */
 #define EXT_CSD_CACHE_SIZE              249     /* RO, 4 bytes */
 #define EXT_CSD_PWR_CL_DDR_200_360      253     /* RO */
+#define EXT_CSD_FIRMWARE_VERSION        254     /* RO, 8 bytes */
+#define EXT_CSD_SUPPORTED_MODE          493     /* RO */
 #define EXT_CSD_TAG_UNIT_SIZE           498     /* RO */
 #define EXT_CSD_DATA_TAG_SUPPORT        499     /* RO */
 #define EXT_CSD_MAX_PACKED_WRITES       500     /* RO */
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dba793e3a331..375af80bde7d 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,12 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_BROKEN_DDR50                       (1<<7)
 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
 #define SDHCI_QUIRK2_STOP_WITH_TC                       (1<<8)
+/* Controller does not support 64-bit DMA */
+#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA                  (1<<9)
+/* need clear transfer mode register before send cmd */
+#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD  (1<<10)
+/* Capability register bit-63 indicates HS400 support */
+#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400               (1<<11)
 
         int irq;                /* Device IRQ */
         void __iomem *ioaddr;   /* Mapped address */
@@ -130,6 +136,7 @@ struct sdhci_host {
 #define SDHCI_SDIO_IRQ_ENABLED  (1<<9)  /* SDIO irq enabled */
 #define SDHCI_SDR104_NEEDS_TUNING (1<<10)       /* SDR104/HS200 needs tuning */
 #define SDHCI_USING_RETUNING_TIMER (1<<11)      /* Host is using a retuning timer for the card */
+#define SDHCI_USE_64_BIT_DMA    (1<<12) /* Use 64-bit DMA */
 
         unsigned int version;   /* SDHCI spec. version */
 
@@ -155,12 +162,19 @@ struct sdhci_host {
 
         int sg_count;           /* Mapped sg entries */
 
-        u8 *adma_desc;          /* ADMA descriptor table */
-        u8 *align_buffer;       /* Bounce buffer */
+        void *adma_table;       /* ADMA descriptor table */
+        void *align_buffer;     /* Bounce buffer */
+
+        size_t adma_table_sz;   /* ADMA descriptor table size */
+        size_t align_buffer_sz; /* Bounce buffer size */
 
         dma_addr_t adma_addr;   /* Mapped ADMA descr. table */
         dma_addr_t align_addr;  /* Mapped bounce buffer */
 
+        unsigned int desc_sz;   /* ADMA descriptor size */
+        unsigned int align_sz;  /* ADMA alignment */
+        unsigned int align_mask;        /* ADMA alignment mask */
+
         struct tasklet_struct finish_tasklet;   /* Tasklet structures */
 
         struct timer_list timer;        /* Timer for timeouts */
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index 50f0bc952328..aab032a6ae61 100644
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
@@ -84,8 +84,6 @@ struct sdio_driver {
         struct device_driver drv;
 };
 
-#define to_sdio_driver(d)       container_of(d, struct sdio_driver, drv)
-
 /**
  * SDIO_DEVICE - macro used to describe a specific SDIO device
  * @vend: the 16 bit manufacturer code
diff --git a/include/linux/of.h b/include/linux/of.h
index 29f0adc5f3e4..c55b50018ac4 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -922,4 +922,15 @@ static inline int of_changeset_update_property(struct of_changeset *ocs,
 /* CONFIG_OF_RESOLVE api */
 extern int of_resolve_phandles(struct device_node *tree);
 
+/**
+ * of_device_is_system_power_controller - Tells if system-power-controller is found for device_node
+ * @np: Pointer to the given device_node
+ *
+ * return true if present false otherwise
+ */
+static inline bool of_device_is_system_power_controller(const struct device_node *np)
+{
+        return of_property_read_bool(np, "system-power-controller");
+}
+
 #endif /* _LINUX_OF_H */
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
new file mode 100644
index 000000000000..c2080eebbb47
--- /dev/null
+++ b/include/linux/omap-gpmc.h
@@ -0,0 +1,199 @@
+/*
+ *  OMAP GPMC (General Purpose Memory Controller) defines
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+/* Maximum Number of Chip Selects */
+#define GPMC_CS_NUM             8
+
+#define GPMC_CONFIG_WP          0x00000005
+
+#define GPMC_IRQ_FIFOEVENTENABLE        0x01
+#define GPMC_IRQ_COUNT_EVENT            0x02
+
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
+
+/* bool type time settings */
+struct gpmc_bool_timings {
+        bool cycle2cyclediffcsen;
+        bool cycle2cyclesamecsen;
+        bool we_extra_delay;
+        bool oe_extra_delay;
+        bool adv_extra_delay;
+        bool cs_extra_delay;
+        bool time_para_granularity;
+};
+
+/*
+ * Note that all values in this struct are in nanoseconds except sync_clk
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+ */
+struct gpmc_timings {
+        /* Minimum clock period for synchronous mode (in picoseconds) */
+        u32 sync_clk;
+
+        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
+        u32 cs_on;              /* Assertion time */
+        u32 cs_rd_off;          /* Read deassertion time */
+        u32 cs_wr_off;          /* Write deassertion time */
+
+        /* ADV signal timings corresponding to GPMC_CONFIG3 */
+        u32 adv_on;             /* Assertion time */
+        u32 adv_rd_off;         /* Read deassertion time */
+        u32 adv_wr_off;         /* Write deassertion time */
+
+        /* WE signals timings corresponding to GPMC_CONFIG4 */
+        u32 we_on;              /* WE assertion time */
+        u32 we_off;             /* WE deassertion time */
+
+        /* OE signals timings corresponding to GPMC_CONFIG4 */
+        u32 oe_on;              /* OE assertion time */
+        u32 oe_off;             /* OE deassertion time */
+
+        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
+        u32 page_burst_access;  /* Multiple access word delay */
+        u32 access;             /* Start-cycle to first data valid delay */
+        u32 rd_cycle;           /* Total read cycle time */
+        u32 wr_cycle;           /* Total write cycle time */
+
+        u32 bus_turnaround;
+        u32 cycle2cycle_delay;
+
+        u32 wait_monitoring;
+        u32 clk_activation;
+
+        /* The following are only on OMAP3430 */
+        u32 wr_access;          /* WRACCESSTIME */
+        u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
+
+        struct gpmc_bool_timings bool_timings;
+};
+
+/* Device timings in picoseconds */
+struct gpmc_device_timings {
+        u32 t_ceasu;    /* address setup to CS valid */
+        u32 t_avdasu;   /* address setup to ADV valid */
+        /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
+         * of tusb using these timings even for sync whilst
+         * ideally for adv_rd/(wr)_off it should have considered
+         * t_avdh instead. This indirectly necessitates r/w
+         * variations of t_avdp as it is possible to have one
+         * sync & other async
+         */
+        u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
+        u32 t_avdp_w;
+        u32 t_aavdh;    /* address hold time */
+        u32 t_oeasu;    /* address setup to OE valid */
+        u32 t_aa;       /* access time from ADV assertion */
+        u32 t_iaa;      /* initial access time */
+        u32 t_oe;       /* access time from OE assertion */
+        u32 t_ce;       /* access time from CS asertion */
+        u32 t_rd_cycle; /* read cycle time */
+        u32 t_cez_r;    /* read CS deassertion to high Z */
+        u32 t_cez_w;    /* write CS deassertion to high Z */
+        u32 t_oez;      /* OE deassertion to high Z */
+        u32 t_weasu;    /* address setup to WE valid */
+        u32 t_wpl;      /* write assertion time */
+        u32 t_wph;      /* write deassertion time */
+        u32 t_wr_cycle; /* write cycle time */
+
+        u32 clk;
+        u32 t_bacc;     /* burst access valid clock to output delay */
+        u32 t_ces;      /* CS setup time to clk */
+        u32 t_avds;     /* ADV setup time to clk */
+        u32 t_avdh;     /* ADV hold time from clk */
+        u32 t_ach;      /* address hold time from clk */
+        u32 t_rdyo;     /* clk to ready valid */
+
+        u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
+        u32 t_ce_avd;   /* CS on to ADV on delay */
+
+        /* XXX: check the possibility of combining
+         * cyc_aavhd_oe & cyc_aavdh_we
+         */
+        u8 cyc_aavdh_oe;/* read address hold time in cycles */
+        u8 cyc_aavdh_we;/* write address hold time in cycles */
+        u8 cyc_oe;      /* access time from OE assertion in cycles */
+        u8 cyc_wpl;     /* write deassertion time in cycles */
+        u32 cyc_iaa;    /* initial access time in cycles */
+
+        /* extra delays */
+        bool ce_xdelay;
+        bool avd_xdelay;
+        bool oe_xdelay;
+        bool we_xdelay;
+};
+
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
+extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
+
+struct gpmc_nand_regs;
+struct device_node;
+
+extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+extern int gpmc_get_client_irq(unsigned irq_config);
+
+extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
+
+extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
+extern int gpmc_calc_divider(unsigned int sync_clk);
+extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
+extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
+extern void gpmc_cs_free(int cs);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
+
+extern void omap3_gpmc_save_context(void);
+extern void omap3_gpmc_restore_context(void);
+
+struct gpmc_timings;
+struct omap_nand_platform_data;
+struct omap_onenand_platform_data;
+
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
+extern int gpmc_nand_init(struct omap_nand_platform_data *d,
+                          struct gpmc_timings *gpmc_t);
+#else
+static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
+                                 struct gpmc_timings *gpmc_t)
+{
+        return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
+extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
+#else
+#define board_onenand_data      NULL
+static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
+{
+}
+#endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5be8db45e368..4c8ac5fcc224 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -331,6 +331,7 @@ struct pci_dev {
         unsigned int    is_added:1;
         unsigned int    is_busmaster:1; /* device is busmaster */
         unsigned int    no_msi:1;       /* device may not use msi */
+        unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
         unsigned int    block_cfg_access:1;     /* config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1fa99a301817..97fb9f69aaed 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -522,6 +522,8 @@
 #define PCI_DEVICE_ID_AMD_15H_M10H_F3   0x1403
 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d
 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e
+#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573
+#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F4 0x1574
 #define PCI_DEVICE_ID_AMD_15H_NB_F0     0x1600
 #define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
 #define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 893a0d07986f..486e84ccb1f9 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -79,7 +79,7 @@ struct perf_branch_stack {
         struct perf_branch_entry        entries[0];
 };
 
-struct perf_regs_user {
+struct perf_regs {
         __u64           abi;
         struct pt_regs  *regs;
 };
@@ -580,34 +580,40 @@ extern u64 perf_event_read_value(struct perf_event *event,
 
 
 struct perf_sample_data {
-        u64                             type;
+        /*
+         * Fields set by perf_sample_data_init(), group so as to
+         * minimize the cachelines touched.
+         */
+        u64                             addr;
+        struct perf_raw_record          *raw;
+        struct perf_branch_stack        *br_stack;
+        u64                             period;
+        u64                             weight;
+        u64                             txn;
+        union  perf_mem_data_src        data_src;
 
+        /*
+         * The other fields, optionally {set,used} by
+         * perf_{prepare,output}_sample().
+         */
+        u64                             type;
         u64                             ip;
         struct {
                 u32     pid;
                 u32     tid;
         }                               tid_entry;
         u64                             time;
-        u64                             addr;
         u64                             id;
         u64                             stream_id;
         struct {
                 u32     cpu;
                 u32     reserved;
         }                               cpu_entry;
-        u64                             period;
-        union  perf_mem_data_src        data_src;
         struct perf_callchain_entry     *callchain;
-        struct perf_raw_record          *raw;
-        struct perf_branch_stack        *br_stack;
-        struct perf_regs_user           regs_user;
+        struct perf_regs                regs_user;
+        struct perf_regs                regs_intr;
         u64                             stack_user_size;
-        u64                             weight;
-        /*
-         * Transaction flags for abort events:
-         */
-        u64                             txn;
-};
+} ____cacheline_aligned;
 
 /* default value for data source */
 #define PERF_MEM_NA (PERF_MEM_S(OP, NA)   |\
@@ -624,9 +630,6 @@ static inline void perf_sample_data_init(struct perf_sample_data *data,
         data->raw  = NULL;
         data->br_stack = NULL;
         data->period = period;
-        data->regs_user.abi = PERF_SAMPLE_REGS_ABI_NONE;
-        data->regs_user.regs = NULL;
-        data->stack_user_size = 0;
         data->weight = 0;
         data->data_src.val = PERF_MEM_NA;
         data->txn = 0;
diff --git a/include/linux/platform_data/hsmmc-omap.h b/include/linux/platform_data/hsmmc-omap.h
new file mode 100644
index 000000000000..67bbcf0785f6
--- /dev/null
+++ b/include/linux/platform_data/hsmmc-omap.h
@@ -0,0 +1,90 @@
+/*
+ * MMC definitions for OMAP2
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * struct omap_hsmmc_dev_attr.flags possibilities
+ *
+ * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
+ *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
+ *    should be set if this is the case.  See for example Section 22.5.3
+ *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
+ *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
+ *
+ * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
+ *    don't work correctly on some MMC controller instances on some
+ *    OMAP3 SoCs; this flag should be set if this is the case.  See
+ *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
+ *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
+ *    Revision F (October 2010) (SPRZ278F).
+ */
+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
+#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ       BIT(1)
+#define OMAP_HSMMC_SWAKEUP_MISSING              BIT(2)
+
+struct omap_hsmmc_dev_attr {
+        u8 flags;
+};
+
+struct mmc_card;
+
+struct omap_hsmmc_platform_data {
+        /* back-link to device */
+        struct device *dev;
+
+        /* set if your board has components or wiring that limits the
+         * maximum frequency on the MMC bus */
+        unsigned int max_freq;
+
+        /* Integrating attributes from the omap_hwmod layer */
+        u8 controller_flags;
+
+        /* Register offset deviation */
+        u16 reg_offset;
+
+        /*
+         * 4/8 wires and any additional host capabilities
+         * need to OR'd all capabilities (ref. linux/mmc/host.h)
+         */
+        u32 caps;       /* Used for the MMC driver on 2430 and later */
+        u32 pm_caps;    /* PM capabilities of the mmc */
+
+        /* switch pin can be for card detect (default) or card cover */
+        unsigned cover:1;
+
+        /* use the internal clock */
+        unsigned internal_clock:1;
+
+        /* nonremovable e.g. eMMC */
+        unsigned nonremovable:1;
+
+        /* eMMC does not handle power off when not in sleep state */
+        unsigned no_regulator_off_init:1;
+
+        /* we can put the features above into this variable */
+#define HSMMC_HAS_PBIAS         (1 << 0)
+#define HSMMC_HAS_UPDATED_RESET (1 << 1)
+#define HSMMC_HAS_HSPE_SUPPORT  (1 << 2)
+        unsigned features;
+
+        int switch_pin;                 /* gpio (card detect) */
+        int gpio_wp;                    /* gpio (write protect) */
+
+        int (*set_power)(struct device *dev, int power_on, int vdd);
+        void (*remux)(struct device *dev, int power_on);
+        /* Call back before enabling / disabling regulators */
+        void (*before_set_reg)(struct device *dev, int power_on, int vdd);
+        /* Call back after enabling / disabling regulators */
+        void (*after_set_reg)(struct device *dev, int power_on, int vdd);
+        /* if we have special card, init it using this callback */
+        void (*init_card)(struct mmc_card *card);
+
+        const char *name;
+        u32 ocr_mask;
+};
diff --git a/include/linux/platform_data/mmc-atmel-mci.h b/include/linux/platform_data/mmc-atmel-mci.h
new file mode 100644
index 000000000000..399a2d5a14bd
--- /dev/null
+++ b/include/linux/platform_data/mmc-atmel-mci.h
@@ -0,0 +1,22 @@
+#ifndef __MMC_ATMEL_MCI_H
+#define __MMC_ATMEL_MCI_H
+
+#include <linux/platform_data/dma-atmel.h>
+#include <linux/platform_data/dma-dw.h>
+
+/**
+ * struct mci_dma_data - DMA data for MCI interface
+ */
+struct mci_dma_data {
+#ifdef CONFIG_ARM
+        struct at_dma_slave     sdata;
+#else
+        struct dw_dma_slave     sdata;
+#endif
+};
+
+/* accessor macros */
+#define slave_data_ptr(s)       (&(s)->sdata)
+#define find_slave_dev(s)       ((s)->sdata.dma_dev)
+
+#endif /* __MMC_ATMEL_MCI_H */
diff --git a/include/linux/platform_data/mmc-omap.h b/include/linux/platform_data/mmc-omap.h
index 51e70cf25cbc..5c188f4e9bec 100644
--- a/include/linux/platform_data/mmc-omap.h
+++ b/include/linux/platform_data/mmc-omap.h
@@ -10,32 +10,8 @@
 
 #define OMAP_MMC_MAX_SLOTS      2
 
-/*
- * struct omap_mmc_dev_attr.flags possibilities
- *
- * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
- *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
- *    should be set if this is the case.  See for example Section 22.5.3
- *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
- *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
- *
- * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
- *    don't work correctly on some MMC controller instances on some
- *    OMAP3 SoCs; this flag should be set if this is the case.  See
- *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
- *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
- *    Revision F (October 2010) (SPRZ278F).
- */
-#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
-#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ       BIT(1)
-#define OMAP_HSMMC_SWAKEUP_MISSING              BIT(2)
-
 struct mmc_card;
 
-struct omap_mmc_dev_attr {
-        u8 flags;
-};
-
 struct omap_mmc_platform_data {
         /* back-link to device */
         struct device *dev;
@@ -106,9 +82,6 @@ struct omap_mmc_platform_data {
                 unsigned vcc_aux_disable_is_sleep:1;
 
                 /* we can put the features above into this variable */
-#define HSMMC_HAS_PBIAS         (1 << 0)
-#define HSMMC_HAS_UPDATED_RESET (1 << 1)
-#define HSMMC_HAS_HSPE_SUPPORT  (1 << 2)
 #define MMC_OMAP7XX             (1 << 3)
 #define MMC_OMAP15XX            (1 << 4)
 #define MMC_OMAP16XX            (1 << 5)
diff --git a/include/linux/platform_data/pxa_sdhci.h b/include/linux/platform_data/pxa_sdhci.h
index 27d3156d093a..9e20c2fb4ffd 100644
--- a/include/linux/platform_data/pxa_sdhci.h
+++ b/include/linux/platform_data/pxa_sdhci.h
@@ -55,9 +55,4 @@ struct sdhci_pxa_platdata {
         unsigned int    quirks2;
         unsigned int    pm_caps;
 };
-
-struct sdhci_pxa {
-        u8      clk_enable;
-        u8      power_mode;
-};
 #endif /* _PXA_SDHCI_H_ */
diff --git a/include/linux/platform_data/serial-omap.h b/include/linux/platform_data/serial-omap.h
index c860c1b314c0..d09275f3cde3 100644
--- a/include/linux/platform_data/serial-omap.h
+++ b/include/linux/platform_data/serial-omap.h
@@ -38,9 +38,6 @@ struct omap_uart_port_info {
         unsigned int            dma_rx_timeout;
         unsigned int            autosuspend_timeout;
         unsigned int            dma_rx_poll_rate;
-        int                     DTR_gpio;
-        int                     DTR_inverted;
-        int                     DTR_present;
 
         int (*get_context_loss_count)(struct device *);
         void (*enable_wakeup)(struct device *, bool);
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 53ff1a752d7e..ed4f5939a452 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -57,7 +57,7 @@ enum rcutorture_type {
         INVALID_RCU_FLAVOR
 };
 
-#if defined(CONFIG_TREE_RCU) || defined(CONFIG_TREE_PREEMPT_RCU)
+#if defined(CONFIG_TREE_RCU) || defined(CONFIG_PREEMPT_RCU)
 void rcutorture_get_gp_data(enum rcutorture_type test_type, int *flags,
                             unsigned long *gpnum, unsigned long *completed);
 void rcutorture_record_test_transition(void);
@@ -260,7 +260,7 @@ static inline int rcu_preempt_depth(void)
 void rcu_init(void);
 void rcu_sched_qs(void);
 void rcu_bh_qs(void);
-void rcu_check_callbacks(int cpu, int user);
+void rcu_check_callbacks(int user);
 struct notifier_block;
 void rcu_idle_enter(void);
 void rcu_idle_exit(void);
@@ -348,8 +348,8 @@ extern struct srcu_struct tasks_rcu_exit_srcu;
  */
 #define cond_resched_rcu_qs() \
 do { \
-        rcu_note_voluntary_context_switch(current); \
-        cond_resched(); \
+        if (!cond_resched()) \
+                rcu_note_voluntary_context_switch(current); \
 } while (0)
 
 #if defined(CONFIG_DEBUG_LOCK_ALLOC) || defined(CONFIG_RCU_TRACE) || defined(CONFIG_SMP)
@@ -365,7 +365,7 @@ typedef void call_rcu_func_t(struct rcu_head *head,
                              void (*func)(struct rcu_head *head));
 void wait_rcu_gp(call_rcu_func_t crf);
 
-#if defined(CONFIG_TREE_RCU) || defined(CONFIG_TREE_PREEMPT_RCU)
+#if defined(CONFIG_TREE_RCU) || defined(CONFIG_PREEMPT_RCU)
 #include <linux/rcutree.h>
 #elif defined(CONFIG_TINY_RCU)
 #include <linux/rcutiny.h>
@@ -867,7 +867,7 @@ static inline void rcu_preempt_sleep_check(void)
  *
  * In non-preemptible RCU implementations (TREE_RCU and TINY_RCU),
  * it is illegal to block while in an RCU read-side critical section.
- * In preemptible RCU implementations (TREE_PREEMPT_RCU) in CONFIG_PREEMPT
+ * In preemptible RCU implementations (PREEMPT_RCU) in CONFIG_PREEMPT
  * kernel builds, RCU read-side critical sections may be preempted,
  * but explicit blocking is illegal.  Finally, in preemptible RCU
  * implementations in real-time (with -rt patchset) kernel builds, RCU
@@ -902,7 +902,9 @@ static inline void rcu_read_lock(void)
  * Unfortunately, this function acquires the scheduler's runqueue and
  * priority-inheritance spinlocks.  This means that deadlock could result
  * if the caller of rcu_read_unlock() already holds one of these locks or
- * any lock that is ever acquired while holding them.
+ * any lock that is ever acquired while holding them; or any lock which
+ * can be taken from interrupt context because rcu_boost()->rt_mutex_lock()
+ * does not disable irqs while taking ->wait_lock.
  *
  * That said, RCU readers are never priority boosted unless they were
  * preempted.  Therefore, one way to avoid deadlock is to make sure
@@ -1062,6 +1064,7 @@ static inline notrace void rcu_read_unlock_sched_notrace(void)
  */
 #define RCU_INIT_POINTER(p, v) \
         do { \
+                rcu_dereference_sparse(p, __rcu); \
                 p = RCU_INITIALIZER(v); \
         } while (0)
 
@@ -1118,7 +1121,7 @@ static inline notrace void rcu_read_unlock_sched_notrace(void)
         __kfree_rcu(&((ptr)->rcu_head), offsetof(typeof(*(ptr)), rcu_head))
 
 #if defined(CONFIG_TINY_RCU) || defined(CONFIG_RCU_NOCB_CPU_ALL)
-static inline int rcu_needs_cpu(int cpu, unsigned long *delta_jiffies)
+static inline int rcu_needs_cpu(unsigned long *delta_jiffies)
 {
         *delta_jiffies = ULONG_MAX;
         return 0;
diff --git a/include/linux/rcutiny.h b/include/linux/rcutiny.h
index 38cc5b1e252d..0e5366200154 100644
--- a/include/linux/rcutiny.h
+++ b/include/linux/rcutiny.h
@@ -78,7 +78,7 @@ static inline void kfree_call_rcu(struct rcu_head *head,
         call_rcu(head, func);
 }
 
-static inline void rcu_note_context_switch(int cpu)
+static inline void rcu_note_context_switch(void)
 {
         rcu_sched_qs();
 }
diff --git a/include/linux/rcutree.h b/include/linux/rcutree.h
index 3e2f5d432743..52953790dcca 100644
--- a/include/linux/rcutree.h
+++ b/include/linux/rcutree.h
@@ -30,9 +30,9 @@
 #ifndef __LINUX_RCUTREE_H
 #define __LINUX_RCUTREE_H
 
-void rcu_note_context_switch(int cpu);
+void rcu_note_context_switch(void);
 #ifndef CONFIG_RCU_NOCB_CPU_ALL
-int rcu_needs_cpu(int cpu, unsigned long *delta_jiffies);
+int rcu_needs_cpu(unsigned long *delta_jiffies);
 #endif /* #ifndef CONFIG_RCU_NOCB_CPU_ALL */
 void rcu_cpu_stall_reset(void);
 
@@ -43,7 +43,7 @@ void rcu_cpu_stall_reset(void);
  */
 static inline void rcu_virt_note_context_switch(int cpu)
 {
-        rcu_note_context_switch(cpu);
+        rcu_note_context_switch();
 }
 
 void synchronize_rcu_bh(void);
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index c5ed83f49c4e..4419b99d8d6e 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -27,6 +27,7 @@ struct spmi_device;
 struct regmap;
 struct regmap_range_cfg;
 struct regmap_field;
+struct snd_ac97;
 
 /* An enum of all the supported cache types */
 enum regcache_type {
@@ -340,6 +341,8 @@ struct regmap *regmap_init_spmi_ext(struct spmi_device *dev,
 struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
                                     void __iomem *regs,
                                     const struct regmap_config *config);
+struct regmap *regmap_init_ac97(struct snd_ac97 *ac97,
+                                const struct regmap_config *config);
 
 struct regmap *devm_regmap_init(struct device *dev,
                                 const struct regmap_bus *bus,
@@ -356,6 +359,10 @@ struct regmap *devm_regmap_init_spmi_ext(struct spmi_device *dev,
 struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
                                          void __iomem *regs,
                                          const struct regmap_config *config);
+struct regmap *devm_regmap_init_ac97(struct snd_ac97 *ac97,
+                                     const struct regmap_config *config);
+
+bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg);
 
 /**
  * regmap_init_mmio(): Initialise register map
diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h
index f540b1496e2f..d17e1ff7ad01 100644
--- a/include/linux/regulator/consumer.h
+++ b/include/linux/regulator/consumer.h
@@ -101,6 +101,8 @@ struct regmap;
  *                      Data passed is "struct pre_voltage_change_data"
  * ABORT_VOLTAGE_CHANGE Regulator voltage change failed for some reason.
  *                      Data passed is old voltage cast to (void *).
+ * PRE_DISABLE    Regulator is about to be disabled
+ * ABORT_DISABLE  Regulator disable failed for some reason
  *
  * NOTE: These events can be OR'ed together when passed into handler.
  */
@@ -115,6 +117,8 @@ struct regmap;
 #define REGULATOR_EVENT_DISABLE                 0x80
 #define REGULATOR_EVENT_PRE_VOLTAGE_CHANGE      0x100
 #define REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE    0x200
+#define REGULATOR_EVENT_PRE_DISABLE             0x400
+#define REGULATOR_EVENT_ABORT_DISABLE           0x800
 
 /**
  * struct pre_voltage_change_data - Data sent with PRE_VOLTAGE_CHANGE event
@@ -284,7 +288,7 @@ devm_regulator_get(struct device *dev, const char *id)
 static inline struct regulator *__must_check
 regulator_get_exclusive(struct device *dev, const char *id)
 {
-        return NULL;
+        return ERR_PTR(-ENODEV);
 }
 
 static inline struct regulator *__must_check
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index fc0ee0ce8325..5f1e9ca47417 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -243,6 +243,8 @@ enum regulator_type {
  *
  * @enable_time: Time taken for initial enable of regulator (in uS).
  * @off_on_delay: guard time (in uS), before re-enabling a regulator
+ *
+ * @of_map_mode: Maps a hardware mode defined in a DeviceTree to a standard mode
  */
 struct regulator_desc {
         const char *name;
@@ -285,6 +287,8 @@ struct regulator_desc {
         unsigned int enable_time;
 
         unsigned int off_on_delay;
+
+        unsigned int (*of_map_mode)(unsigned int mode);
 };
 
 /**
@@ -301,6 +305,9 @@ struct regulator_desc {
  *           NULL).
  * @regmap: regmap to use for core regmap helpers if dev_get_regulator() is
  *          insufficient.
+ * @ena_gpio_initialized: GPIO controlling regulator enable was properly
+ *                        initialized, meaning that >= 0 is a valid gpio
+ *                        identifier and < 0 is a non existent gpio.
  * @ena_gpio: GPIO controlling regulator enable.
  * @ena_gpio_invert: Sense for GPIO enable control.
  * @ena_gpio_flags: Flags to use when calling gpio_request_one()
@@ -312,6 +319,7 @@ struct regulator_config {
         struct device_node *of_node;
         struct regmap *regmap;
 
+        bool ena_gpio_initialized;
         int ena_gpio;
         unsigned int ena_gpio_invert:1;
         unsigned int ena_gpio_flags;
diff --git a/include/linux/regulator/of_regulator.h b/include/linux/regulator/of_regulator.h
index f9217965aaa3..763953f7e3b8 100644
--- a/include/linux/regulator/of_regulator.h
+++ b/include/linux/regulator/of_regulator.h
@@ -6,24 +6,29 @@
 #ifndef __LINUX_OF_REG_H
 #define __LINUX_OF_REG_H
 
+struct regulator_desc;
+
 struct of_regulator_match {
         const char *name;
         void *driver_data;
         struct regulator_init_data *init_data;
         struct device_node *of_node;
+        const struct regulator_desc *desc;
 };
 
 #if defined(CONFIG_OF)
 extern struct regulator_init_data
         *of_get_regulator_init_data(struct device *dev,
-                                    struct device_node *node);
+                                    struct device_node *node,
+                                    const struct regulator_desc *desc);
 extern int of_regulator_match(struct device *dev, struct device_node *node,
                               struct of_regulator_match *matches,
                               unsigned int num_matches);
 #else
 static inline struct regulator_init_data
         *of_get_regulator_init_data(struct device *dev,
-                                    struct device_node *node)
+                                    struct device_node *node,
+                                    const struct regulator_desc *desc)
 {
         return NULL;
 }
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index 41a4695fde08..ce6b962ffed4 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -12,11 +12,13 @@ struct reset_controller_dev;
  *         things to reset the device
  * @assert: manually assert the reset line, if supported
  * @deassert: manually deassert the reset line, if supported
+ * @status: return the status of the reset line, if supported
  */
 struct reset_control_ops {
         int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
         int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
         int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
+        int (*status)(struct reset_controller_dev *rcdev, unsigned long id);
 };
 
 struct module;
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 349f150ae12c..da5602bd77d7 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -10,6 +10,7 @@ struct reset_control;
 int reset_control_reset(struct reset_control *rstc);
 int reset_control_assert(struct reset_control *rstc);
 int reset_control_deassert(struct reset_control *rstc);
+int reset_control_status(struct reset_control *rstc);
 
 struct reset_control *reset_control_get(struct device *dev, const char *id);
 void reset_control_put(struct reset_control *rstc);
@@ -57,6 +58,12 @@ static inline int reset_control_deassert(struct reset_control *rstc)
         return 0;
 }
 
+static inline int reset_control_status(struct reset_control *rstc)
+{
+        WARN_ON(1);
+        return 0;
+}
+
 static inline void reset_control_put(struct reset_control *rstc)
 {
         WARN_ON(1);
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 5e344bbe63ec..706a9f744909 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1278,9 +1278,9 @@ struct task_struct {
         union rcu_special rcu_read_unlock_special;
         struct list_head rcu_node_entry;
 #endif /* #ifdef CONFIG_PREEMPT_RCU */
-#ifdef CONFIG_TREE_PREEMPT_RCU
+#ifdef CONFIG_PREEMPT_RCU
         struct rcu_node *rcu_blocked_node;
-#endif /* #ifdef CONFIG_TREE_PREEMPT_RCU */
+#endif /* #ifdef CONFIG_PREEMPT_RCU */
 #ifdef CONFIG_TASKS_RCU
         unsigned long rcu_tasks_nvcsw;
         bool rcu_tasks_holdout;
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index a4c9547aae64..f8e76e08ebe4 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -15,8 +15,6 @@
 #define _LINUX_VEXPRESS_H
 
 #include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
 #include <linux/regmap.h>
 
 #define VEXPRESS_SITE_MB                0
@@ -24,13 +22,6 @@
 #define VEXPRESS_SITE_DB2               2
 #define VEXPRESS_SITE_MASTER            0xf
 
-#define VEXPRESS_RES_FUNC(_site, _func) \
-{                                       \
-        .start = (_site),               \
-        .end = (_func),                 \
-        .flags = IORESOURCE_BUS,        \
-}
-
 /* Config infrastructure */
 
 void vexpress_config_set_master(u32 site);
@@ -58,16 +49,6 @@ struct regmap *devm_regmap_init_vexpress_config(struct device *dev);
 
 /* Platform control */
 
-unsigned int vexpress_get_mci_cardin(struct device *dev);
-u32 vexpress_get_procid(int site);
-void *vexpress_get_24mhz_clock_base(void);
 void vexpress_flags_set(u32 data);
 
-void vexpress_sysreg_early_init(void __iomem *base);
-int vexpress_syscfg_device_register(struct platform_device *pdev);
-
-/* Clocks */
-
-void vexpress_clk_init(void __iomem *sp810_base);
-
 #endif
diff --git a/include/net/inet_common.h b/include/net/inet_common.h
index fe7994c48b75..b2828a06a5a6 100644
--- a/include/net/inet_common.h
+++ b/include/net/inet_common.h
@@ -37,6 +37,8 @@ int inet_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg);
 int inet_ctl_sock_create(struct sock **sk, unsigned short family,
                          unsigned short type, unsigned char protocol,
                          struct net *net);
+int inet_recv_error(struct sock *sk, struct msghdr *msg, int len,
+                    int *addr_len);
 
 static inline void inet_ctl_sock_destroy(struct sock *sk)
 {
diff --git a/include/scsi/libfc.h b/include/scsi/libfc.h
index 52beadf9a29b..93d14daf0994 100644
--- a/include/scsi/libfc.h
+++ b/include/scsi/libfc.h
@@ -1105,8 +1105,6 @@ int fc_eh_abort(struct scsi_cmnd *);
 int fc_eh_device_reset(struct scsi_cmnd *);
 int fc_eh_host_reset(struct scsi_cmnd *);
 int fc_slave_alloc(struct scsi_device *);
-int fc_change_queue_depth(struct scsi_device *, int qdepth, int reason);
-int fc_change_queue_type(struct scsi_device *, int tag_type);
 
 /*
  * ELS/CT interface
diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
index 728c9ad9feb0..4d1c46aac331 100644
--- a/include/scsi/libiscsi.h
+++ b/include/scsi/libiscsi.h
@@ -378,8 +378,6 @@ struct iscsi_host {
 /*
  * scsi host template
  */
-extern int iscsi_change_queue_depth(struct scsi_device *sdev, int depth,
-                                    int reason);
 extern int iscsi_eh_abort(struct scsi_cmnd *sc);
 extern int iscsi_eh_recover_target(struct scsi_cmnd *sc);
 extern int iscsi_eh_session_reset(struct scsi_cmnd *sc);
diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index ef7872c20da9..832dcc9f86ec 100644
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -365,12 +365,6 @@ struct asd_sas_phy {
 struct scsi_core {
         struct Scsi_Host *shost;
 
-        struct mutex      task_queue_flush;
-        spinlock_t        task_queue_lock;
-        struct list_head  task_queue;
-        int               task_queue_size;
-
-        struct task_struct *queue_thread;
 };
 
 struct sas_ha_event {
@@ -422,9 +416,6 @@ struct sas_ha_struct {
         struct asd_sas_port **sas_port; /* array of valid pointers, must be set */
         int             num_phys; /* must be set, gt 0, static */
 
-        /* The class calls this to send a task for execution. */
-        int lldd_max_execute_num;
-        int lldd_queue_size;
         int strict_wide_ports; /* both sas_addr and attached_sas_addr must match
                                 * their siblings when forming wide ports */
 
@@ -612,7 +603,6 @@ struct sas_ssp_task {
 
 struct sas_task {
         struct domain_device *dev;
-        struct list_head      list;
 
         spinlock_t   task_state_lock;
         unsigned     task_state_flags;
@@ -665,8 +655,7 @@ struct sas_domain_function_template {
         int  (*lldd_dev_found)(struct domain_device *);
         void (*lldd_dev_gone)(struct domain_device *);
 
-        int (*lldd_execute_task)(struct sas_task *, int num,
-                                 gfp_t gfp_flags);
+        int (*lldd_execute_task)(struct sas_task *, gfp_t gfp_flags);
 
         /* Task Management Functions. Must be called from process context. */
         int (*lldd_abort_task)(struct sas_task *);
@@ -700,12 +689,10 @@ extern void sas_suspend_ha(struct sas_ha_struct *sas_ha);
 int sas_set_phy_speed(struct sas_phy *phy,
                       struct sas_phy_linkrates *rates);
 int sas_phy_reset(struct sas_phy *phy, int hard_reset);
-int sas_queue_up(struct sas_task *task);
 extern int sas_queuecommand(struct Scsi_Host * ,struct scsi_cmnd *);
 extern int sas_target_alloc(struct scsi_target *);
 extern int sas_slave_configure(struct scsi_device *);
-extern int sas_change_queue_depth(struct scsi_device *, int new_depth,
-                                  int reason);
+extern int sas_change_queue_depth(struct scsi_device *, int new_depth);
 extern int sas_change_queue_type(struct scsi_device *, int qt);
 extern int sas_bios_param(struct scsi_device *,
                           struct block_device *,
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index d17178e6fcdd..8a7f8ad58aac 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -128,8 +128,10 @@ enum scsi_timeouts {
 #define MOVE_MEDIUM           0xa5
 #define EXCHANGE_MEDIUM       0xa6
 #define READ_12               0xa8
+#define SERVICE_ACTION_OUT_12 0xa9
 #define WRITE_12              0xaa
-#define READ_MEDIA_SERIAL_NUMBER 0xab
+#define READ_MEDIA_SERIAL_NUMBER 0xab /* Obsolete with SPC-2 */
+#define SERVICE_ACTION_IN_12  0xab
 #define WRITE_VERIFY_12       0xae
 #define VERIFY_12             0xaf
 #define SEARCH_HIGH_12        0xb0
@@ -151,7 +153,9 @@ enum scsi_timeouts {
 #define VERIFY_16             0x8f
 #define SYNCHRONIZE_CACHE_16  0x91
 #define WRITE_SAME_16         0x93
-#define SERVICE_ACTION_IN     0x9e
+#define SERVICE_ACTION_BIDIRECTIONAL 0x9d
+#define SERVICE_ACTION_IN_16  0x9e
+#define SERVICE_ACTION_OUT_16 0x9f
 /* values for service action in */
 #define SAI_READ_CAPACITY_16  0x10
 #define SAI_GET_LBA_STATUS    0x12
@@ -165,8 +169,8 @@ enum scsi_timeouts {
 #define MI_REPORT_ALIASES     0x0b
 #define MI_REPORT_SUPPORTED_OPERATION_CODES 0x0c
 #define MI_REPORT_SUPPORTED_TASK_MANAGEMENT_FUNCTIONS 0x0d
-#define MI_REPORT_PRIORITY   0x0e
-#define MI_REPORT_TIMESTAMP  0x0f
+#define MI_REPORT_PRIORITY    0x0e
+#define MI_REPORT_TIMESTAMP   0x0f
 #define MI_MANAGEMENT_PROTOCOL_IN 0x10
 /* value for MI_REPORT_TARGET_PGS ext header */
 #define MI_EXT_HDR_PARAM_FMT  0x20
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index 522a5f27f553..9fc1aecfc813 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -53,6 +53,9 @@ struct scsi_pointer {
         volatile int phase;
 };
 
+/* for scmd->flags */
+#define SCMD_TAGGED             (1 << 0)
+
 struct scsi_cmnd {
         struct scsi_device *device;
         struct list_head list;  /* scsi_cmnd participates in queue lists */
@@ -132,6 +135,7 @@ struct scsi_cmnd {
                                          * to be at an address < 16Mb). */
 
         int result;             /* Status code from lower level driver */
+        int flags;              /* Command flags */
 
         unsigned char tag;      /* SCSI-II queued command tag */
 };
@@ -159,7 +163,7 @@ extern void *scsi_kmap_atomic_sg(struct scatterlist *sg, int sg_count,
                                  size_t *offset, size_t *len);
 extern void scsi_kunmap_atomic_sg(void *virt);
 
-extern int scsi_init_io(struct scsi_cmnd *cmd, gfp_t gfp_mask);
+extern int scsi_init_io(struct scsi_cmnd *cmd);
 
 extern int scsi_dma_map(struct scsi_cmnd *cmd);
 extern void scsi_dma_unmap(struct scsi_cmnd *cmd);
diff --git a/include/scsi/scsi_dbg.h b/include/scsi/scsi_dbg.h
index e89844cc2cd3..7982795df595 100644
--- a/include/scsi/scsi_dbg.h
+++ b/include/scsi/scsi_dbg.h
@@ -2,23 +2,27 @@
 #define _SCSI_SCSI_DBG_H
 
 struct scsi_cmnd;
+struct scsi_device;
 struct scsi_sense_hdr;
 
 extern void scsi_print_command(struct scsi_cmnd *);
-extern void __scsi_print_command(unsigned char *);
-extern void scsi_show_extd_sense(unsigned char, unsigned char);
-extern void scsi_show_sense_hdr(struct scsi_sense_hdr *);
-extern void scsi_print_sense_hdr(const char *, struct scsi_sense_hdr *);
-extern void scsi_cmd_print_sense_hdr(struct scsi_cmnd *, const char *,
-                                     struct scsi_sense_hdr *);
-extern void scsi_print_sense(char *, struct scsi_cmnd *);
-extern void __scsi_print_sense(const char *name,
+extern void __scsi_print_command(const unsigned char *, size_t);
+extern void scsi_show_extd_sense(const struct scsi_device *, const char *,
+                                 unsigned char, unsigned char);
+extern void scsi_show_sense_hdr(const struct scsi_device *, const char *,
+                                const struct scsi_sense_hdr *);
+extern void scsi_print_sense_hdr(const struct scsi_device *, const char *,
+                                 const struct scsi_sense_hdr *);
+extern void scsi_print_sense(const struct scsi_cmnd *);
+extern void __scsi_print_sense(const struct scsi_device *, const char *name,
                                const unsigned char *sense_buffer,
                                int sense_len);
-extern void scsi_show_result(int);
-extern void scsi_print_result(struct scsi_cmnd *);
-extern void scsi_print_status(unsigned char);
+extern void scsi_print_result(struct scsi_cmnd *, const char *, int);
+extern const char *scsi_hostbyte_string(int);
+extern const char *scsi_driverbyte_string(int);
+extern const char *scsi_mlreturn_string(int);
 extern const char *scsi_sense_key_string(unsigned char);
-extern const char *scsi_extd_sense_format(unsigned char, unsigned char);
+extern const char *scsi_extd_sense_format(unsigned char, unsigned char,
+                                          const char **);
 
 #endif /* _SCSI_SCSI_DBG_H */
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index 27ecee73bd72..6364e23454dd 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -141,7 +141,6 @@ struct scsi_device {
         unsigned ppr:1;         /* Device supports PPR messages */
         unsigned tagged_supported:1;    /* Supports SCSI-II tagged queuing */
         unsigned simple_tags:1; /* simple queue tag messages are enabled */
-        unsigned ordered_tags:1;/* ordered queue tag messages are enabled */
         unsigned was_reset:1;   /* There was a bus reset on the bus for 
                                  * this device */
         unsigned expecting_cc_ua:1; /* Expecting a CHECK_CONDITION/UNIT_ATTN
@@ -201,11 +200,6 @@ struct scsi_device {
         unsigned long           sdev_data[0];
 } __attribute__((aligned(sizeof(unsigned long))));
 
-struct scsi_dh_devlist {
-        char *vendor;
-        char *model;
-};
-
 typedef void (*activate_complete)(void *, int);
 struct scsi_device_handler {
         /* Used by the infrastructure */
@@ -214,9 +208,8 @@ struct scsi_device_handler {
         /* Filled by the hardware handler */
         struct module *module;
         const char *name;
-        const struct scsi_dh_devlist *devlist;
         int (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);
-        int (*attach)(struct scsi_device *);
+        struct scsi_dh_data *(*attach)(struct scsi_device *);
         void (*detach)(struct scsi_device *);
         int (*activate)(struct scsi_device *, activate_complete, void *);
         int (*prep_fn)(struct scsi_device *, struct request *);
@@ -228,7 +221,6 @@ struct scsi_dh_data {
         struct scsi_device_handler *scsi_dh;
         struct scsi_device *sdev;
         struct kref kref;
-        char buf[0];
 };
 
 #define to_scsi_device(d)       \
@@ -244,6 +236,15 @@ struct scsi_dh_data {
 #define sdev_dbg(sdev, fmt, a...) \
         dev_dbg(&(sdev)->sdev_gendev, fmt, ##a)
 
+/*
+ * like scmd_printk, but the device name is passed in
+ * as a string pointer
+ */
+#define sdev_prefix_printk(l, sdev, p, fmt, a...)                       \
+        (p) ?                                                           \
+        sdev_printk(l, sdev, "[%s] " fmt, p, ##a) :                     \
+        sdev_printk(l, sdev, fmt, ##a)
+
 #define scmd_printk(prefix, scmd, fmt, a...)                            \
         (scmd)->request->rq_disk ?                                      \
         sdev_printk(prefix, (scmd)->device, "[%s] " fmt,                \
@@ -379,7 +380,7 @@ extern struct scsi_device *__scsi_iterate_devices(struct Scsi_Host *,
 #define __shost_for_each_device(sdev, shost) \
         list_for_each_entry((sdev), &((shost)->__devices), siblings)
 
-extern void scsi_adjust_queue_depth(struct scsi_device *, int, int);
+extern int scsi_change_queue_depth(struct scsi_device *, int);
 extern int scsi_track_queue_full(struct scsi_device *, int);
 
 extern int scsi_set_medium_removal(struct scsi_device *, char);
diff --git a/include/scsi/scsi_driver.h b/include/scsi/scsi_driver.h
index c2b759809d8a..891a658aa867 100644
--- a/include/scsi/scsi_driver.h
+++ b/include/scsi/scsi_driver.h
@@ -9,7 +9,6 @@ struct scsi_cmnd;
 struct scsi_device;
 
 struct scsi_driver {
-        struct module           *owner;
         struct device_driver    gendrv;
 
         void (*rescan)(struct device *);
diff --git a/include/scsi/scsi_eh.h b/include/scsi/scsi_eh.h
index 06a8790893ef..1e1421b06565 100644
--- a/include/scsi/scsi_eh.h
+++ b/include/scsi/scsi_eh.h
@@ -27,10 +27,10 @@ struct scsi_sense_hdr {		/* See SPC-3 section 4.5 */
         u8 additional_length;   /* always 0 for fixed sense format */
 };
 
-static inline int scsi_sense_valid(struct scsi_sense_hdr *sshdr)
+static inline bool scsi_sense_valid(const struct scsi_sense_hdr *sshdr)
 {
         if (!sshdr)
-                return 0;
+                return false;
 
         return (sshdr->response_code & 0x70) == 0x70;
 }
@@ -42,12 +42,12 @@ extern void scsi_eh_flush_done_q(struct list_head *done_q);
 extern void scsi_report_bus_reset(struct Scsi_Host *, int);
 extern void scsi_report_device_reset(struct Scsi_Host *, int, int);
 extern int scsi_block_when_processing_errors(struct scsi_device *);
-extern int scsi_normalize_sense(const u8 *sense_buffer, int sb_len,
-                struct scsi_sense_hdr *sshdr);
-extern int scsi_command_normalize_sense(struct scsi_cmnd *cmd,
-                struct scsi_sense_hdr *sshdr);
+extern bool scsi_normalize_sense(const u8 *sense_buffer, int sb_len,
+                                 struct scsi_sense_hdr *sshdr);
+extern bool scsi_command_normalize_sense(const struct scsi_cmnd *cmd,
+                                         struct scsi_sense_hdr *sshdr);
 
-static inline int scsi_sense_is_deferred(struct scsi_sense_hdr *sshdr)
+static inline bool scsi_sense_is_deferred(const struct scsi_sense_hdr *sshdr)
 {
         return ((sshdr->response_code >= 0x70) && (sshdr->response_code & 1));
 }
@@ -60,15 +60,7 @@ extern int scsi_get_sense_info_fld(const u8 * sense_buffer, int sb_len,
 
 extern void scsi_build_sense_buffer(int desc, u8 *buf, u8 key, u8 asc, u8 ascq);
 
-/*
- * Reset request from external source
- */
-#define SCSI_TRY_RESET_DEVICE   1
-#define SCSI_TRY_RESET_BUS      2
-#define SCSI_TRY_RESET_HOST     3
-#define SCSI_TRY_RESET_TARGET   4
-
-extern int scsi_reset_provider(struct scsi_device *, int);
+extern int scsi_ioctl_reset(struct scsi_device *, int __user *);
 
 struct scsi_eh_save {
         /* saved state */
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index 5e362489ee88..c8a462ef9a4e 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -46,12 +46,6 @@ struct blk_queue_tags;
 #define DISABLE_CLUSTERING 0
 #define ENABLE_CLUSTERING 1
 
-enum {
-        SCSI_QDEPTH_DEFAULT,    /* default requested change, e.g. from sysfs */
-        SCSI_QDEPTH_QFULL,      /* scsi-ml requested due to queue full */
-        SCSI_QDEPTH_RAMP_UP,    /* scsi-ml requested due to threshold event */
-};
-
 struct scsi_host_template {
         struct module *module;
         const char *name;
@@ -195,7 +189,7 @@ struct scsi_host_template {
          * Things currently recommended to be handled at this time include:
          *
          * 1.  Setting the device queue depth.  Proper setting of this is
-         *     described in the comments for scsi_adjust_queue_depth.
+         *     described in the comments for scsi_change_queue_depth.
          * 2.  Determining if the device supports the various synchronous
          *     negotiation protocols.  The device struct will already have
          *     responded to INQUIRY and the results of the standard items
@@ -281,7 +275,7 @@ struct scsi_host_template {
          *
          * Status: OPTIONAL
          */
-        int (* change_queue_depth)(struct scsi_device *, int, int);
+        int (* change_queue_depth)(struct scsi_device *, int);
 
         /*
          * Fill in this function to allow the changing of tag types
@@ -422,6 +416,16 @@ struct scsi_host_template {
         unsigned char present;
 
         /*
+         * Let the block layer assigns tags to all commands.
+         */
+        unsigned use_blk_tags:1;
+
+        /*
+         * Track QUEUE_FULL events and reduce queue depth on demand.
+         */
+        unsigned track_queue_depth:1;
+
+        /*
          * This specifies the mode that a LLD supports.
          */
         unsigned supported_mode:2;
@@ -451,11 +455,6 @@ struct scsi_host_template {
          */
         unsigned skip_settle_delay:1;
 
-        /*
-         * True if we are using ordered write support.
-         */
-        unsigned ordered_tag:1;
-
         /* True if the controller does not support WRITE SAME */
         unsigned no_write_same:1;
 
@@ -638,6 +637,14 @@ struct Scsi_Host {
         short unsigned int sg_prot_tablesize;
         unsigned int max_sectors;
         unsigned long dma_boundary;
+        /*
+         * In scsi-mq mode, the number of hardware queues supported by the LLD.
+         *
+         * Note: it is assumed that each hardware queue has a queue depth of
+         * can_queue. In other words, the total queue depth per host
+         * is nr_hw_queues * can_queue.
+         */
+        unsigned nr_hw_queues;
         /* 
          * Used to assign serial numbers to the cmds.
          * Protected by the host lock.
@@ -647,7 +654,6 @@ struct Scsi_Host {
         unsigned active_mode:2;
         unsigned unchecked_isa_dma:1;
         unsigned use_clustering:1;
-        unsigned use_blk_tcq:1;
 
         /*
          * Host has requested that no further requests come through for the
@@ -662,11 +668,6 @@ struct Scsi_Host {
          */
         unsigned reverse_ordering:1;
 
-        /*
-         * Ordered write support
-         */
-        unsigned ordered_tag:1;
-
         /* Task mgmt function in progress */
         unsigned tmf_in_progress:1;
 
diff --git a/include/scsi/scsi_ioctl.h b/include/scsi/scsi_ioctl.h
index b9006848b813..8d19d1d233c3 100644
--- a/include/scsi/scsi_ioctl.h
+++ b/include/scsi/scsi_ioctl.h
@@ -40,9 +40,9 @@ typedef struct scsi_fctargaddress {
         unsigned char host_wwn[8]; // include NULL term.
 } Scsi_FCTargAddress;
 
+int scsi_ioctl_block_when_processing_errors(struct scsi_device *sdev,
+                int cmd, bool ndelay);
 extern int scsi_ioctl(struct scsi_device *, int, void __user *);
-extern int scsi_nonblockable_ioctl(struct scsi_device *sdev, int cmd,
-                                   void __user *arg, int ndelay);
 
 #endif /* __KERNEL__ */
 #endif /* _SCSI_IOCTL_H */
diff --git a/include/scsi/scsi_tcq.h b/include/scsi/scsi_tcq.h
index 56ed843969ca..fe4a70299419 100644
--- a/include/scsi/scsi_tcq.h
+++ b/include/scsi/scsi_tcq.h
@@ -16,20 +16,16 @@
 
 #ifdef CONFIG_BLOCK
 
+int scsi_change_queue_type(struct scsi_device *sdev, int tag_type);
+
 /**
  * scsi_get_tag_type - get the type of tag the device supports
  * @sdev:       the scsi device
- *
- * Notes:
- *      If the drive only supports simple tags, returns MSG_SIMPLE_TAG
- *      if it supports all tag types, returns MSG_ORDERED_TAG.
  */
 static inline int scsi_get_tag_type(struct scsi_device *sdev)
 {
         if (!sdev->tagged_supported)
                 return 0;
-        if (sdev->ordered_tags)
-                return MSG_ORDERED_TAG;
         if (sdev->simple_tags)
                 return MSG_SIMPLE_TAG;
         return 0;
@@ -39,90 +35,33 @@ static inline void scsi_set_tag_type(struct scsi_device *sdev, int tag)
 {
         switch (tag) {
         case MSG_ORDERED_TAG:
-                sdev->ordered_tags = 1;
-                /* fall through */
         case MSG_SIMPLE_TAG:
                 sdev->simple_tags = 1;
                 break;
         case 0:
                 /* fall through */
         default:
-                sdev->ordered_tags = 0;
                 sdev->simple_tags = 0;
                 break;
         }
 }
-/**
- * scsi_activate_tcq - turn on tag command queueing
- * @SDpnt:      device to turn on TCQ for
- * @depth:      queue depth
- *
- * Notes:
- *      Eventually, I hope depth would be the maximum depth
- *      the device could cope with and the real queue depth
- *      would be adjustable from 0 to depth.
- **/
-static inline void scsi_activate_tcq(struct scsi_device *sdev, int depth)
-{
-        if (!sdev->tagged_supported)
-                return;
-
-        if (shost_use_blk_mq(sdev->host))
-                queue_flag_set_unlocked(QUEUE_FLAG_QUEUED, sdev->request_queue);
-        else if (!blk_queue_tagged(sdev->request_queue))
-                blk_queue_init_tags(sdev->request_queue, depth,
-                                    sdev->host->bqt);
-
-        scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth);
-}
-
-/**
- * scsi_deactivate_tcq - turn off tag command queueing
- * @SDpnt:      device to turn off TCQ for
- **/
-static inline void scsi_deactivate_tcq(struct scsi_device *sdev, int depth)
-{
-        if (blk_queue_tagged(sdev->request_queue))
-                blk_queue_free_tags(sdev->request_queue);
-        scsi_adjust_queue_depth(sdev, 0, depth);
-}
-
-/**
- * scsi_populate_tag_msg - place a tag message in a buffer
- * @SCpnt:      pointer to the Scsi_Cmnd for the tag
- * @msg:        pointer to the area to place the tag
- *
- * Notes:
- *      designed to create the correct type of tag message for the 
- *      particular request.  Returns the size of the tag message.
- *      May return 0 if TCQ is disabled for this device.
- **/
-static inline int scsi_populate_tag_msg(struct scsi_cmnd *cmd, char *msg)
-{
-        struct request *req = cmd->request;
-
-        if (blk_rq_tagged(req)) {
-                *msg++ = MSG_SIMPLE_TAG;
-                *msg++ = req->tag;
-                return 2;
-        }
-
-        return 0;
-}
 
 static inline struct scsi_cmnd *scsi_mq_find_tag(struct Scsi_Host *shost,
-                unsigned int hw_ctx, int tag)
+                                                 int unique_tag)
 {
-        struct request *req;
+        u16 hwq = blk_mq_unique_tag_to_hwq(unique_tag);
+        struct request *req = NULL;
 
-        req = blk_mq_tag_to_rq(shost->tag_set.tags[hw_ctx], tag);
+        if (hwq < shost->tag_set.nr_hw_queues)
+                req = blk_mq_tag_to_rq(shost->tag_set.tags[hwq],
+                                       blk_mq_unique_tag_to_tag(unique_tag));
         return req ? (struct scsi_cmnd *)req->special : NULL;
 }
 
 /**
  * scsi_find_tag - find a tagged command by device
  * @SDpnt:      pointer to the ScSI device
- * @tag:        the tag number
+ * @tag:        tag generated by blk_mq_unique_tag()
  *
  * Notes:
  *      Only works with tags allocated by the generic blk layer.
@@ -133,9 +72,9 @@ static inline struct scsi_cmnd *scsi_find_tag(struct scsi_device *sdev, int tag)
 
         if (tag != SCSI_NO_TAG) {
                 if (shost_use_blk_mq(sdev->host))
-                        return scsi_mq_find_tag(sdev->host, 0, tag);
+                        return scsi_mq_find_tag(sdev->host, tag);
 
-                req = blk_queue_find_tag(sdev->request_queue, tag);
+                req = blk_queue_find_tag(sdev->request_queue, tag);
                 return req ? (struct scsi_cmnd *)req->special : NULL;
         }
 
@@ -174,7 +113,7 @@ static inline int scsi_init_shared_tag_map(struct Scsi_Host *shost, int depth)
 /**
  * scsi_host_find_tag - find the tagged command by host
  * @shost:      pointer to scsi_host
- * @tag:        tag of the scsi_cmnd
+ * @tag:        tag generated by blk_mq_unique_tag()
  *
  * Notes:
  *      Only works with tags allocated by the generic blk layer.
@@ -186,7 +125,7 @@ static inline struct scsi_cmnd *scsi_host_find_tag(struct Scsi_Host *shost,
 
         if (tag != SCSI_NO_TAG) {
                 if (shost_use_blk_mq(shost))
-                        return scsi_mq_find_tag(shost, 0, tag);
+                        return scsi_mq_find_tag(shost, tag);
                 req = blk_map_queue_find_tag(shost->bqt, tag);
                 return req ? (struct scsi_cmnd *)req->special : NULL;
         }
diff --git a/include/scsi/scsi_transport_spi.h b/include/scsi/scsi_transport_spi.h
index 7497a383b1a4..a4fa52b4d5c5 100644
--- a/include/scsi/scsi_transport_spi.h
+++ b/include/scsi/scsi_transport_spi.h
@@ -157,5 +157,6 @@ int spi_populate_width_msg(unsigned char *msg, int width);
 int spi_populate_sync_msg(unsigned char *msg, int period, int offset);
 int spi_populate_ppr_msg(unsigned char *msg, int period, int offset, int width,
                 int options);
+int spi_populate_tag_msg(unsigned char *msg, struct scsi_cmnd *cmd);
 
 #endif /* SCSI_TRANSPORT_SPI_H */
diff --git a/include/scsi/sg.h b/include/scsi/sg.h
index 750e5db7c6bf..3afec7032448 100644
--- a/include/scsi/sg.h
+++ b/include/scsi/sg.h
@@ -164,12 +164,15 @@ typedef struct sg_req_info { /* used by SG_GET_REQUEST_TABLE ioctl() */
 
 /* Returns -EBUSY if occupied. 3rd argument pointer to int (see next) */
 #define SG_SCSI_RESET 0x2284
-/* Associated values that can be given to SG_SCSI_RESET follow */
+/* Associated values that can be given to SG_SCSI_RESET follow.
+ * SG_SCSI_RESET_NO_ESCALATE may be OR-ed to the _DEVICE, _TARGET, _BUS
+ * or _HOST reset value so only that action is attempted. */
 #define         SG_SCSI_RESET_NOTHING   0
 #define         SG_SCSI_RESET_DEVICE    1
 #define         SG_SCSI_RESET_BUS       2
 #define         SG_SCSI_RESET_HOST      3
 #define         SG_SCSI_RESET_TARGET    4
+#define         SG_SCSI_RESET_NO_ESCALATE       0x100
 
 /* synchronous SCSI command ioctl, (only in version 3 interface) */
 #define SG_IO 0x2285   /* similar effect as write() followed by read() */
diff --git a/include/soc/at91/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h
new file mode 100644
index 000000000000..aa047f458f1b
--- /dev/null
+++ b/include/soc/at91/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (SDRAMC only) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SDRAMC_H
+#define AT91RM9200_SDRAMC_H
+
+/* SDRAM Controller registers */
+#define AT91RM9200_SDRAMC_MR            0x90                    /* Mode Register */
+#define         AT91RM9200_SDRAMC_MODE  (0xf << 0)              /* Command Mode */
+#define                 AT91RM9200_SDRAMC_MODE_NORMAL           (0 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_NOP              (1 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_PRECHARGE        (2 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_LMR              (3 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_REFRESH  (4 << 0)
+#define         AT91RM9200_SDRAMC_DBW           (1   << 4)              /* Data Bus Width */
+#define                 AT91RM9200_SDRAMC_DBW_32        (0 << 4)
+#define                 AT91RM9200_SDRAMC_DBW_16        (1 << 4)
+
+#define AT91RM9200_SDRAMC_TR            0x94                    /* Refresh Timer Register */
+#define         AT91RM9200_SDRAMC_COUNT (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91RM9200_SDRAMC_CR            0x98                    /* Configuration Register */
+#define         AT91RM9200_SDRAMC_NC            (3   <<  0)             /* Number of Column Bits */
+#define                 AT91RM9200_SDRAMC_NC_8  (0 << 0)
+#define                 AT91RM9200_SDRAMC_NC_9  (1 << 0)
+#define                 AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define                 AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define         AT91RM9200_SDRAMC_NR            (3   <<  2)             /* Number of Row Bits */
+#define                 AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define                 AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define                 AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define         AT91RM9200_SDRAMC_NB            (1   <<  4)             /* Number of Banks */
+#define                 AT91RM9200_SDRAMC_NB_2  (0 << 4)
+#define                 AT91RM9200_SDRAMC_NB_4  (1 << 4)
+#define         AT91RM9200_SDRAMC_CAS           (3   <<  5)             /* CAS Latency */
+#define                 AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define         AT91RM9200_SDRAMC_TWR           (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91RM9200_SDRAMC_TRC           (0xf << 11)             /* Row Cycle Delay */
+#define         AT91RM9200_SDRAMC_TRP           (0xf << 15)             /* Row Precharge Delay */
+#define         AT91RM9200_SDRAMC_TRCD  (0xf << 19)             /* Row to Column Delay */
+#define         AT91RM9200_SDRAMC_TRAS  (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91RM9200_SDRAMC_TXSR  (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91RM9200_SDRAMC_SRR           0x9c                    /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR           0xa0                    /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER           0xa4                    /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR           0xa8                    /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR           0xac                    /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR           0xb0                    /* Interrupt Status Register */
+
+#endif
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..0210797abf2e
--- /dev/null
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -0,0 +1,124 @@
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ *      Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_DDRSDR_H
+#define AT91SAM9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL        0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define                 AT91_DDRSDRC_NR_14      (3 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define         AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL [SAM9 Only] */
+#define         AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver [SAM9 Only] */
+#define         AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared [SAM9 Only] */
+#define         AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
+
+#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_T2PR       0x14    /* Timing 2 Register [SAM9 Only] */
+#define         AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
+#define         AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
+#define         AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
+#define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
+
+#define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define         AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
+#define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
+
+#define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define                 AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
+#define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
+#define                 AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
+#define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
+
+#define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+
+#define AT91_DDRSDRC_HS         0x2C    /* High Speed Register [SAM9 Only] */
+#define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
+
+#define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
+
+#define AT91_DDRSDRC_WPMR       0xE4    /* Write Protect Mode Register [SAM9 Only] */
+#define         AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
+#define         AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
+#define         AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
+
+#define AT91_DDRSDRC_WPSR       0xE8    /* Write Protect Status Register [SAM9 Only] */
+#define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
+#define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
+
+#endif
diff --git a/include/soc/at91/at91sam9_sdramc.h b/include/soc/at91/at91sam9_sdramc.h
new file mode 100644
index 000000000000..3d085a9a7450
--- /dev/null
+++ b/include/soc/at91/at91sam9_sdramc.h
@@ -0,0 +1,85 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR          0x00    /* SDRAM Controller Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         0
+#define                 AT91_SDRAMC_MODE_NOP            1
+#define                 AT91_SDRAMC_MODE_PRECHARGE      2
+#define                 AT91_SDRAMC_MODE_LMR            3
+#define                 AT91_SDRAMC_MODE_REFRESH        4
+#define                 AT91_SDRAMC_MODE_EXT_LMR        5
+#define                 AT91_SDRAMC_MODE_DEEP           6
+
+#define AT91_SDRAMC_TR          0x04    /* SDRAM Controller Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR          0x08    /* SDRAM Controller Configuration Register */
+#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_1       (1 << 5)
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define                 AT91_SDRAMC_CAS_3       (3 << 5)
+#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 7)
+#define                 AT91_SDRAMC_DBW_16      (1 << 7)
+#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR         0x10    /* SDRAM Controller Low Power Register */
+#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
+#define                 AT91_SDRAMC_LPCB_DISABLE                0
+#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
+#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
+#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
+#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
+
+#define AT91_SDRAMC_IER         0x14    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         0x18    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         0x1C    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         0x20    /* SDRAM Controller Interrupt Status Register */
+#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR         0x24    /* SDRAM Memory Device Register */
+#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
+#define                 AT91_SDRAMC_MD_SDRAM            0
+#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
+
+#endif
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
new file mode 100644
index 000000000000..63deb8d9f82a
--- /dev/null
+++ b/include/soc/tegra/mc.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_MC_H__
+#define __SOC_TEGRA_MC_H__
+
+#include <linux/types.h>
+
+struct clk;
+struct device;
+struct page;
+
+struct tegra_smmu_enable {
+        unsigned int reg;
+        unsigned int bit;
+};
+
+/* latency allowance */
+struct tegra_mc_la {
+        unsigned int reg;
+        unsigned int shift;
+        unsigned int mask;
+        unsigned int def;
+};
+
+struct tegra_mc_client {
+        unsigned int id;
+        const char *name;
+        unsigned int swgroup;
+
+        unsigned int fifo_size;
+
+        struct tegra_smmu_enable smmu;
+        struct tegra_mc_la la;
+};
+
+struct tegra_smmu_swgroup {
+        unsigned int swgroup;
+        unsigned int reg;
+};
+
+struct tegra_smmu_ops {
+        void (*flush_dcache)(struct page *page, unsigned long offset,
+                             size_t size);
+};
+
+struct tegra_smmu_soc {
+        const struct tegra_mc_client *clients;
+        unsigned int num_clients;
+
+        const struct tegra_smmu_swgroup *swgroups;
+        unsigned int num_swgroups;
+
+        bool supports_round_robin_arbitration;
+        bool supports_request_limit;
+
+        unsigned int num_asids;
+
+        const struct tegra_smmu_ops *ops;
+};
+
+struct tegra_mc;
+struct tegra_smmu;
+
+#ifdef CONFIG_TEGRA_IOMMU_SMMU
+struct tegra_smmu *tegra_smmu_probe(struct device *dev,
+                                    const struct tegra_smmu_soc *soc,
+                                    struct tegra_mc *mc);
+#else
+static inline struct tegra_smmu *
+tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
+                 struct tegra_mc *mc)
+{
+        return NULL;
+}
+#endif
+
+struct tegra_mc_soc {
+        const struct tegra_mc_client *clients;
+        unsigned int num_clients;
+
+        const unsigned int *emem_regs;
+        unsigned int num_emem_regs;
+
+        unsigned int num_address_bits;
+        unsigned int atom_size;
+
+        const struct tegra_smmu_soc *smmu;
+};
+
+struct tegra_mc {
+        struct device *dev;
+        struct tegra_smmu *smmu;
+        void __iomem *regs;
+        struct clk *clk;
+        int irq;
+
+        const struct tegra_mc_soc *soc;
+        unsigned long tick;
+};
+
+#endif /* __SOC_TEGRA_MC_H__ */
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index e862497f7556..8bb00a27e219 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -184,6 +184,8 @@ struct snd_pcm_ops {
 #define SNDRV_PCM_FMTBIT_DSD_U8         _SNDRV_PCM_FMTBIT(DSD_U8)
 #define SNDRV_PCM_FMTBIT_DSD_U16_LE     _SNDRV_PCM_FMTBIT(DSD_U16_LE)
 #define SNDRV_PCM_FMTBIT_DSD_U32_LE     _SNDRV_PCM_FMTBIT(DSD_U32_LE)
+#define SNDRV_PCM_FMTBIT_DSD_U16_BE     _SNDRV_PCM_FMTBIT(DSD_U16_BE)
+#define SNDRV_PCM_FMTBIT_DSD_U32_BE     _SNDRV_PCM_FMTBIT(DSD_U32_BE)
 
 #ifdef SNDRV_LITTLE_ENDIAN
 #define SNDRV_PCM_FMTBIT_S16            SNDRV_PCM_FMTBIT_S16_LE
diff --git a/include/trace/events/rcu.h b/include/trace/events/rcu.h
index e335e7d8c6c2..c78e88ce5ea3 100644
--- a/include/trace/events/rcu.h
+++ b/include/trace/events/rcu.h
@@ -36,7 +36,7 @@ TRACE_EVENT(rcu_utilization,
 
 #ifdef CONFIG_RCU_TRACE
 
-#if defined(CONFIG_TREE_RCU) || defined(CONFIG_TREE_PREEMPT_RCU)
+#if defined(CONFIG_TREE_RCU) || defined(CONFIG_PREEMPT_RCU)
 
 /*
  * Tracepoint for grace-period events.  Takes a string identifying the
@@ -345,7 +345,7 @@ TRACE_EVENT(rcu_fqs,
                   __entry->cpu, __entry->qsevent)
 );
 
-#endif /* #if defined(CONFIG_TREE_RCU) || defined(CONFIG_TREE_PREEMPT_RCU) */
+#endif /* #if defined(CONFIG_TREE_RCU) || defined(CONFIG_PREEMPT_RCU) */
 
 /*
  * Tracepoint for dyntick-idle entry/exit events.  These take a string
diff --git a/include/trace/events/scsi.h b/include/trace/events/scsi.h
index db6c93510f74..079bd10a01b4 100644
--- a/include/trace/events/scsi.h
+++ b/include/trace/events/scsi.h
@@ -94,7 +94,7 @@
                 scsi_opcode_name(WRITE_16),                     \
                 scsi_opcode_name(VERIFY_16),                    \
                 scsi_opcode_name(WRITE_SAME_16),                \
-                scsi_opcode_name(SERVICE_ACTION_IN),            \
+                scsi_opcode_name(SERVICE_ACTION_IN_16),         \
                 scsi_opcode_name(SAI_READ_CAPACITY_16),         \
                 scsi_opcode_name(SAI_GET_LBA_STATUS),           \
                 scsi_opcode_name(MI_REPORT_TARGET_PGS),         \
diff --git a/include/trace/events/target.h b/include/trace/events/target.h
index da9cc0f05c93..45403443dd82 100644
--- a/include/trace/events/target.h
+++ b/include/trace/events/target.h
@@ -96,7 +96,7 @@
                 scsi_opcode_name(WRITE_16),                     \
                 scsi_opcode_name(VERIFY_16),                    \
                 scsi_opcode_name(WRITE_SAME_16),                \
-                scsi_opcode_name(SERVICE_ACTION_IN),            \
+                scsi_opcode_name(SERVICE_ACTION_IN_16),         \
                 scsi_opcode_name(SAI_READ_CAPACITY_16),         \
                 scsi_opcode_name(SAI_GET_LBA_STATUS),           \
                 scsi_opcode_name(MI_REPORT_TARGET_PGS),         \
diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
index 4c94f31a8c99..8523f9bb72f2 100644
--- a/include/uapi/linux/Kbuild
+++ b/include/uapi/linux/Kbuild
@@ -427,7 +427,7 @@ header-y += virtio_net.h
 header-y += virtio_pci.h
 header-y += virtio_ring.h
 header-y += virtio_rng.h
-header=y += vm_sockets.h
+header-y += vm_sockets.h
 header-y += vt.h
 header-y += wait.h
 header-y += wanrouter.h
diff --git a/include/uapi/linux/dm-ioctl.h b/include/uapi/linux/dm-ioctl.h
index 3315ab21f728..a570d7b5796c 100644
--- a/include/uapi/linux/dm-ioctl.h
+++ b/include/uapi/linux/dm-ioctl.h
@@ -267,9 +267,9 @@ enum {
 #define DM_DEV_SET_GEOMETRY     _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)
 
 #define DM_VERSION_MAJOR        4
-#define DM_VERSION_MINOR        28
+#define DM_VERSION_MINOR        29
 #define DM_VERSION_PATCHLEVEL   0
-#define DM_VERSION_EXTRA        "-ioctl (2014-09-17)"
+#define DM_VERSION_EXTRA        "-ioctl (2014-10-28)"
 
 /* Status bits */
 #define DM_READONLY_FLAG        (1 << 0) /* In/Out */
@@ -352,4 +352,9 @@ enum {
  */
 #define DM_DEFERRED_REMOVE              (1 << 17) /* In/Out */
 
+/*
+ * If set, the device is suspended internally.
+ */
+#define DM_INTERNAL_SUSPEND_FLAG        (1 << 18) /* Out */
+
 #endif                          /* _LINUX_DM_IOCTL_H */
diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
index aa90bc98b6e2..ae99f7743cf4 100644
--- a/include/uapi/linux/elf-em.h
+++ b/include/uapi/linux/elf-em.h
@@ -34,6 +34,7 @@
 #define EM_MN10300      89      /* Panasonic/MEI MN10300, AM33 */
 #define EM_OPENRISC     92     /* OpenRISC 32-bit embedded processor */
 #define EM_BLACKFIN     106     /* ADI Blackfin Processor */
+#define EM_ALTERA_NIOS2 113     /* Altera Nios II soft-core processor */
 #define EM_TI_C6000     140     /* TI C6X DSPs */
 #define EM_AARCH64      183     /* ARM 64 bit */
 #define EM_FRV          0x5441  /* Fujitsu FR-V */
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf2561b9e..71e1d0ed92f7 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -397,6 +397,7 @@ typedef struct elf64_shdr {
 #define NT_ARM_TLS      0x401           /* ARM TLS register */
 #define NT_ARM_HW_BREAK 0x402           /* ARM hardware breakpoint registers */
 #define NT_ARM_HW_WATCH 0x403           /* ARM hardware watchpoint registers */
+#define NT_ARM_SYSTEM_CALL      0x404   /* ARM system call number */
 #define NT_METAG_CBUF   0x500           /* Metag catch buffer registers */
 #define NT_METAG_RPIPE  0x501           /* Metag read pipeline state */
 #define NT_METAG_TLS    0x502           /* Metag TLS pointer */
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9d845404d875..9b79abbd1ab8 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -137,8 +137,9 @@ enum perf_event_sample_format {
         PERF_SAMPLE_DATA_SRC                    = 1U << 15,
         PERF_SAMPLE_IDENTIFIER                  = 1U << 16,
         PERF_SAMPLE_TRANSACTION                 = 1U << 17,
+        PERF_SAMPLE_REGS_INTR                   = 1U << 18,
 
-        PERF_SAMPLE_MAX = 1U << 18,             /* non-ABI */
+        PERF_SAMPLE_MAX = 1U << 19,             /* non-ABI */
 };
 
 /*
@@ -238,6 +239,7 @@ enum perf_event_read_format {
 #define PERF_ATTR_SIZE_VER2     80      /* add: branch_sample_type */
 #define PERF_ATTR_SIZE_VER3     96      /* add: sample_regs_user */
                                         /* add: sample_stack_user */
+#define PERF_ATTR_SIZE_VER4     104     /* add: sample_regs_intr */
 
 /*
  * Hardware event_id to monitor via a performance monitoring event:
@@ -334,6 +336,15 @@ struct perf_event_attr {
 
         /* Align to u64. */
         __u32   __reserved_2;
+        /*
+         * Defines set of regs to dump for each sample
+         * state captured on:
+         *  - precise = 0: PMU interrupt
+         *  - precise > 0: sampled instruction
+         *
+         * See asm/perf_regs.h for details.
+         */
+        __u64   sample_regs_intr;
 };
 
 #define perf_flags(attr)        (*(&(attr)->read_format + 1))
@@ -686,6 +697,8 @@ enum perf_event_type {
          *      { u64                   weight;   } && PERF_SAMPLE_WEIGHT
          *      { u64                   data_src; } && PERF_SAMPLE_DATA_SRC
          *      { u64                   transaction; } && PERF_SAMPLE_TRANSACTION
+         *      { u64                   abi; # enum perf_sample_regs_abi
+         *        u64                   regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
          * };
          */
         PERF_RECORD_SAMPLE                      = 9,
diff --git a/include/uapi/sound/asound.h b/include/uapi/sound/asound.h
index 6ee586728df9..941d32f007dc 100644
--- a/include/uapi/sound/asound.h
+++ b/include/uapi/sound/asound.h
@@ -220,7 +220,9 @@ typedef int __bitwise snd_pcm_format_t;
 #define SNDRV_PCM_FORMAT_DSD_U8         ((__force snd_pcm_format_t) 48) /* DSD, 1-byte samples DSD (x8) */
 #define SNDRV_PCM_FORMAT_DSD_U16_LE     ((__force snd_pcm_format_t) 49) /* DSD, 2-byte samples DSD (x16), little endian */
 #define SNDRV_PCM_FORMAT_DSD_U32_LE     ((__force snd_pcm_format_t) 50) /* DSD, 4-byte samples DSD (x32), little endian */
-#define SNDRV_PCM_FORMAT_LAST           SNDRV_PCM_FORMAT_DSD_U32_LE
+#define SNDRV_PCM_FORMAT_DSD_U16_BE     ((__force snd_pcm_format_t) 51) /* DSD, 2-byte samples DSD (x16), big endian */
+#define SNDRV_PCM_FORMAT_DSD_U32_BE     ((__force snd_pcm_format_t) 52) /* DSD, 4-byte samples DSD (x32), big endian */
+#define SNDRV_PCM_FORMAT_LAST           SNDRV_PCM_FORMAT_DSD_U32_BE
 
 #ifdef SNDRV_LITTLE_ENDIAN
 #define SNDRV_PCM_FORMAT_S16            SNDRV_PCM_FORMAT_S16_LE