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authorJack Morgenstein <jackm@dev.mellanox.co.il>2009-06-05 13:36:24 -0400
committerRoland Dreier <rolandd@cisco.com>2009-06-05 13:36:24 -0400
commit2ac6bf4ddc87c3b6b609f8fa82f6ebbffeac12f4 (patch)
tree7de468eac9f948f85faebb2f86efbfd66737d8d9 /include
parentab6bf42e2339580b5d87746d0ff4da4b1578b03e (diff)
IB/mlx4: Add strong ordering to local inval and fast reg work requests
The ConnectX Programmer's Reference Manual states that the "SO" bit must be set when posting Fast Register and Local Invalidate send work requests. When this bit is set, the work request will be executed only after all previous work requests on the send queue have been executed. (If the bit is not set, Fast Register and Local Invalidate WQEs may begin execution too early, which violates the defined semantics for these operations) This fixes the issue with NFS/RDMA reported in <http://lists.openfabrics.org/pipermail/general/2009-April/059253.html> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Cc: <stable@kernel.org> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/qp.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index bf8f11982dae..9f29d86e5dc9 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -165,6 +165,7 @@ enum {
165 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 165 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
166 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 166 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
167 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 167 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
168 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
168}; 169};
169 170
170struct mlx4_wqe_ctrl_seg { 171struct mlx4_wqe_ctrl_seg {