diff options
author | Vinod Koul <vinod.koul@intel.com> | 2013-09-02 08:12:35 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2013-09-02 08:12:35 -0400 |
commit | 265d9c673d47fcd5812d69dc07104b706285de56 (patch) | |
tree | ebb686a2ecbf702c4a5cab975cf86fbc10dac5e7 /include | |
parent | 592745e2f8afbaeafcf72645f0a2b0285644e091 (diff) | |
parent | e5ffa401eacd0e74178e20ba932200fc9fe41c07 (diff) |
Merge branch 'topic/sh' into for-linus
Conflicts:
drivers/dma/sh/Kconfig
drivers/dma/sh/shdmac.c
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/sh_dma.h | 55 | ||||
-rw-r--r-- | include/linux/shdma-base.h | 3 |
2 files changed, 34 insertions, 24 deletions
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h index 4e83f3e034f3..b7b43b82231e 100644 --- a/include/linux/sh_dma.h +++ b/include/linux/sh_dma.h | |||
@@ -33,13 +33,44 @@ struct sh_dmae_slave_config { | |||
33 | char mid_rid; | 33 | char mid_rid; |
34 | }; | 34 | }; |
35 | 35 | ||
36 | /** | ||
37 | * struct sh_dmae_channel - DMAC channel platform data | ||
38 | * @offset: register offset within the main IOMEM resource | ||
39 | * @dmars: channel DMARS register offset | ||
40 | * @chclr_offset: channel CHCLR register offset | ||
41 | * @dmars_bit: channel DMARS field offset within the register | ||
42 | * @chclr_bit: bit position, to be set to reset the channel | ||
43 | */ | ||
36 | struct sh_dmae_channel { | 44 | struct sh_dmae_channel { |
37 | unsigned int offset; | 45 | unsigned int offset; |
38 | unsigned int dmars; | 46 | unsigned int dmars; |
39 | unsigned int dmars_bit; | ||
40 | unsigned int chclr_offset; | 47 | unsigned int chclr_offset; |
48 | unsigned char dmars_bit; | ||
49 | unsigned char chclr_bit; | ||
41 | }; | 50 | }; |
42 | 51 | ||
52 | /** | ||
53 | * struct sh_dmae_pdata - DMAC platform data | ||
54 | * @slave: array of slaves | ||
55 | * @slave_num: number of slaves in the above array | ||
56 | * @channel: array of DMA channels | ||
57 | * @channel_num: number of channels in the above array | ||
58 | * @ts_low_shift: shift of the low part of the TS field | ||
59 | * @ts_low_mask: low TS field mask | ||
60 | * @ts_high_shift: additional shift of the high part of the TS field | ||
61 | * @ts_high_mask: high TS field mask | ||
62 | * @ts_shift: array of Transfer Size shifts, indexed by TS value | ||
63 | * @ts_shift_num: number of shifts in the above array | ||
64 | * @dmaor_init: DMAOR initialisation value | ||
65 | * @chcr_offset: CHCR address offset | ||
66 | * @chcr_ie_bit: CHCR Interrupt Enable bit | ||
67 | * @dmaor_is_32bit: DMAOR is a 32-bit register | ||
68 | * @needs_tend_set: the TEND register has to be set | ||
69 | * @no_dmars: DMAC has no DMARS registers | ||
70 | * @chclr_present: DMAC has one or several CHCLR registers | ||
71 | * @chclr_bitwise: channel CHCLR registers are bitwise | ||
72 | * @slave_only: DMAC cannot be used for MEMCPY | ||
73 | */ | ||
43 | struct sh_dmae_pdata { | 74 | struct sh_dmae_pdata { |
44 | const struct sh_dmae_slave_config *slave; | 75 | const struct sh_dmae_slave_config *slave; |
45 | int slave_num; | 76 | int slave_num; |
@@ -59,42 +90,22 @@ struct sh_dmae_pdata { | |||
59 | unsigned int needs_tend_set:1; | 90 | unsigned int needs_tend_set:1; |
60 | unsigned int no_dmars:1; | 91 | unsigned int no_dmars:1; |
61 | unsigned int chclr_present:1; | 92 | unsigned int chclr_present:1; |
93 | unsigned int chclr_bitwise:1; | ||
62 | unsigned int slave_only:1; | 94 | unsigned int slave_only:1; |
63 | }; | 95 | }; |
64 | 96 | ||
65 | /* DMA register */ | ||
66 | #define SAR 0x00 | ||
67 | #define DAR 0x04 | ||
68 | #define TCR 0x08 | ||
69 | #define CHCR 0x0C | ||
70 | #define DMAOR 0x40 | ||
71 | |||
72 | #define TEND 0x18 /* USB-DMAC */ | ||
73 | |||
74 | /* DMAOR definitions */ | 97 | /* DMAOR definitions */ |
75 | #define DMAOR_AE 0x00000004 | 98 | #define DMAOR_AE 0x00000004 |
76 | #define DMAOR_NMIF 0x00000002 | 99 | #define DMAOR_NMIF 0x00000002 |
77 | #define DMAOR_DME 0x00000001 | 100 | #define DMAOR_DME 0x00000001 |
78 | 101 | ||
79 | /* Definitions for the SuperH DMAC */ | 102 | /* Definitions for the SuperH DMAC */ |
80 | #define REQ_L 0x00000000 | ||
81 | #define REQ_E 0x00080000 | ||
82 | #define RACK_H 0x00000000 | ||
83 | #define RACK_L 0x00040000 | ||
84 | #define ACK_R 0x00000000 | ||
85 | #define ACK_W 0x00020000 | ||
86 | #define ACK_H 0x00000000 | ||
87 | #define ACK_L 0x00010000 | ||
88 | #define DM_INC 0x00004000 | 103 | #define DM_INC 0x00004000 |
89 | #define DM_DEC 0x00008000 | 104 | #define DM_DEC 0x00008000 |
90 | #define DM_FIX 0x0000c000 | 105 | #define DM_FIX 0x0000c000 |
91 | #define SM_INC 0x00001000 | 106 | #define SM_INC 0x00001000 |
92 | #define SM_DEC 0x00002000 | 107 | #define SM_DEC 0x00002000 |
93 | #define SM_FIX 0x00003000 | 108 | #define SM_FIX 0x00003000 |
94 | #define RS_IN 0x00000200 | ||
95 | #define RS_OUT 0x00000300 | ||
96 | #define TS_BLK 0x00000040 | ||
97 | #define TM_BUR 0x00000020 | ||
98 | #define CHCR_DE 0x00000001 | 109 | #define CHCR_DE 0x00000001 |
99 | #define CHCR_TE 0x00000002 | 110 | #define CHCR_TE 0x00000002 |
100 | #define CHCR_IE 0x00000004 | 111 | #define CHCR_IE 0x00000004 |
diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h index 5b1c9848124c..f92c0a43c54c 100644 --- a/include/linux/shdma-base.h +++ b/include/linux/shdma-base.h | |||
@@ -96,7 +96,7 @@ struct shdma_ops { | |||
96 | dma_addr_t (*slave_addr)(struct shdma_chan *); | 96 | dma_addr_t (*slave_addr)(struct shdma_chan *); |
97 | int (*desc_setup)(struct shdma_chan *, struct shdma_desc *, | 97 | int (*desc_setup)(struct shdma_chan *, struct shdma_desc *, |
98 | dma_addr_t, dma_addr_t, size_t *); | 98 | dma_addr_t, dma_addr_t, size_t *); |
99 | int (*set_slave)(struct shdma_chan *, int, bool); | 99 | int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool); |
100 | void (*setup_xfer)(struct shdma_chan *, int); | 100 | void (*setup_xfer)(struct shdma_chan *, int); |
101 | void (*start_xfer)(struct shdma_chan *, struct shdma_desc *); | 101 | void (*start_xfer)(struct shdma_chan *, struct shdma_desc *); |
102 | struct shdma_desc *(*embedded_desc)(void *, int); | 102 | struct shdma_desc *(*embedded_desc)(void *, int); |
@@ -116,7 +116,6 @@ struct shdma_dev { | |||
116 | 116 | ||
117 | int shdma_request_irq(struct shdma_chan *, int, | 117 | int shdma_request_irq(struct shdma_chan *, int, |
118 | unsigned long, const char *); | 118 | unsigned long, const char *); |
119 | void shdma_free_irq(struct shdma_chan *); | ||
120 | bool shdma_reset(struct shdma_dev *sdev); | 119 | bool shdma_reset(struct shdma_dev *sdev); |
121 | void shdma_chan_probe(struct shdma_dev *sdev, | 120 | void shdma_chan_probe(struct shdma_dev *sdev, |
122 | struct shdma_chan *schan, int id); | 121 | struct shdma_chan *schan, int id); |