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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /include
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/gpio.h6
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h2
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h2
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h84
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h16
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h46
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h281
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h60
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h341
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h763
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h1281
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h14
-rw-r--r--include/asm-blackfin/mach-bf548/gpio.h212
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h174
-rw-r--r--include/asm-blackfin/mach-bf561/dma.h3
17 files changed, 603 insertions, 2688 deletions
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index d98d77ad71f7..bc0cca02850b 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -204,6 +204,10 @@
204 204
205#endif 205#endif
206 206
207#ifdef BF548_FAMILY
208#include <asm-blackfin/mach-bf548/gpio.h>
209#endif
210
207#ifdef BF561_FAMILY 211#ifdef BF561_FAMILY
208#define MAX_BLACKFIN_GPIOS 48 212#define MAX_BLACKFIN_GPIOS 48
209#define PORT_FIO0 GPIO_0 213#define PORT_FIO0 GPIO_0
@@ -264,6 +268,7 @@ unsigned short get_gpiop_maska(unsigned short);
264unsigned short get_gpiop_maskb(unsigned short); 268unsigned short get_gpiop_maskb(unsigned short);
265unsigned short get_gpiop_data(unsigned short); 269unsigned short get_gpiop_data(unsigned short);
266 270
271#ifndef BF548_FAMILY
267struct gpio_port_t { 272struct gpio_port_t {
268 unsigned short data; 273 unsigned short data;
269 unsigned short dummy1; 274 unsigned short dummy1;
@@ -299,6 +304,7 @@ struct gpio_port_t {
299 unsigned short dummy16; 304 unsigned short dummy16;
300 unsigned short inen; 305 unsigned short inen;
301}; 306};
307#endif
302 308
303#ifdef CONFIG_PM 309#ifdef CONFIG_PM
304#define PM_WAKE_RISING 0x1 310#define PM_WAKE_RISING 0x1
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
index bd9d5e94307d..16c672c01d80 100644
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -51,4 +51,7 @@
51#define CH_MEM_STREAM1_DEST 10 /* TX */ 51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */ 52#define CH_MEM_STREAM1_SRC 11 /* RX */
53 53
54extern int channel2irq(unsigned int channel);
55extern struct dma_register *base_addr[];
56
54#endif 57#endif
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
index 7a964040870a..021991984e6e 100644
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -52,4 +52,7 @@
52#define CH_MEM_STREAM1_DEST 14 /* TX */ 52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */ 53#define CH_MEM_STREAM1_SRC 15 /* RX */
54 54
55extern int channel2irq(unsigned int channel);
56extern struct dma_register *base_addr[];
57
55#endif 58#endif
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index ddc150e6fb0f..aca1d4ba145c 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -47,6 +47,8 @@
47 SPORT external receive and transmit clocks. */ 47 SPORT external receive and transmit clocks. */
48#define ANOMALY_05000272 /* Certain data cache write through modes fail for 48#define ANOMALY_05000272 /* Certain data cache write through modes fail for
49 VDDint <=0.9V */ 49 VDDint <=0.9V */
50#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
51 not restored */
50#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the 52#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
51 Boundary of Reserved Memory */ 53 Boundary of Reserved Memory */
52#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and 54#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 0b211020443d..163c79e3d230 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -30,6 +30,8 @@
30#ifndef __MACH_BF548_H__ 30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__ 31#define __MACH_BF548_H__
32 32
33#define SUPPORTED_REVID 0
34
33/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ 35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
34 36
35#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ 37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 8f5d9c4d8d5b..2f4afc90db11 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -1,34 +1,35 @@
1#include <linux/serial.h> 1#include <linux/serial.h>
2#include <asm/dma.h> 2#include <asm/dma.h>
3 3
4#define NR_PORTS 2 4#define NR_PORTS 4
5 5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 6#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 7#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 8#define OFFSET_GCTL 0x08 /* Global Control Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */ 9#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */ 10#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */ 11#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */ 12#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 13#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */ 14#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
15#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
16#define OFFSET_THR 0x28 /* Transmit Holding register */
17#define OFFSET_RBR 0x2C /* Receive Buffer register */
18 18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 21#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 23#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) 24#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 25#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27 26
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 27#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 28#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 29#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
30#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 33#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 34#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34 35
@@ -112,9 +113,29 @@ struct bfin_serial_res bfin_serial_resource[] = {
112 CH_UART1_TX, 113 CH_UART1_TX,
113 CH_UART1_RX, 114 CH_UART1_RX,
114#endif 115#endif
115#ifdef CONFIG_BFIN_UART1_CTSRTS 116 },
116 CONFIG_UART1_CTS_PIN, 117#endif
117 CONFIG_UART1_RTS_PIN, 118#ifdef CONFIG_SERIAL_BFIN_UART2
119 {
120 0xFFC02100,
121 IRQ_UART2_RX,
122#ifdef CONFIG_SERIAL_BFIN_DMA
123 CH_UART2_TX,
124 CH_UART2_RX,
125#endif
126#ifdef CONFIG_BFIN_UART2_CTSRTS
127 CONFIG_UART2_CTS_PIN,
128 CONFIG_UART2_RTS_PIN,
129#endif
130 },
131#endif
132#ifdef CONFIG_SERIAL_BFIN_UART3
133 {
134 0xFFC03100,
135 IRQ_UART3_RX,
136#ifdef CONFIG_SERIAL_BFIN_DMA
137 CH_UART3_TX,
138 CH_UART3_RX,
118#endif 139#endif
119 }, 140 },
120#endif 141#endif
@@ -124,15 +145,40 @@ int nr_ports = ARRAY_SIZE(bfin_serial_resource);
124 145
125static void bfin_serial_hw_init(struct bfin_serial_port *uart) 146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
126{ 147{
127 unsigned short val; 148#ifdef CONFIG_SERIAL_BFIN_UART0
128 val = bfin_read16(BFIN_PORT_MUX); 149 /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
129 val &= ~(PFDE | PFTE); 150 bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
130 bfin_write16(BFIN_PORT_MUX, val); 151 bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_UART1
155 /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
156 bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
157 bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
158#ifdef CONFIG_BFIN_UART1_CTSRTS
159 /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
160 bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
161 bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
162#endif
163#endif
131 164
132 val = bfin_read16(PORTF_FER); 165#ifdef CONFIG_SERIAL_BFIN_UART2
133 val |= 0xF; 166 /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
134 bfin_write16(PORTF_FER, val); 167 bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
168 bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
169#endif
135 170
171#ifdef CONFIG_SERIAL_BFIN_UART3
172 /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
173 bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
174 bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
175#ifdef CONFIG_BFIN_UART3_CTSRTS
176 /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
177 bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
178 bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
179#endif
180#endif
181 SSYNC();
136#ifdef CONFIG_SERIAL_BFIN_CTSRTS 182#ifdef CONFIG_SERIAL_BFIN_CTSRTS
137 if (uart->cts_pin >= 0) { 183 if (uart->cts_pin >= 0) {
138 gpio_request(uart->cts_pin, NULL); 184 gpio_request(uart->cts_pin, NULL);
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 094c41a63194..791218fe7d94 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -34,24 +34,26 @@
34 34
35#define BF548_FAMILY 35#define BF548_FAMILY
36 36
37#include "bf548.h"
38#include "mem_map.h"
39#include "anomaly.h"
40
37#ifdef CONFIG_BF542 41#ifdef CONFIG_BF542
38#include "bf542.h" 42#include "defBF542.h"
43#endif
39 44
40#ifdef CONFIG_BF544 45#ifdef CONFIG_BF544
41#include "bf544.h" 46#include "defBF544.h"
42#endif 47#endif
43 48
44#ifdef CONFIG_BF548 49#ifdef CONFIG_BF548
45#include "bf548.h" 50#include "defBF548.h"
46#endif 51#endif
47 52
48#ifdef CONFIG_BF549 53#ifdef CONFIG_BF549
49#include "bf549.h" 54#include "defBF549.h"
50#endif 55#endif
51 56
52#include "mem_map.h"
53#include "anomaly.h"
54
55#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) 57#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
56#ifdef CONFIG_BF542 58#ifdef CONFIG_BF542
57#include "cdefBF542.h" 59#include "cdefBF542.h"
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 6bbcefeb3627..b1338000e27b 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -31,7 +31,7 @@
31#ifndef _CDEF_BF54X_H 31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H 32#define _CDEF_BF54X_H
33 33
34#include <defBF54x_base.h> 34#include "defBF54x_base.h"
35 35
36/* ************************************************************** */ 36/* ************************************************************** */
37/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 37/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@@ -70,12 +70,18 @@
70#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) 70#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
71#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) 71#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
72#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) 72#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
73#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
74#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
75
73#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 76#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
74#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 77#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
75#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) 78#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
76#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) 79#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
77#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) 80#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
78#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) 81#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
82#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
83#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
84
79#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 85#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
80#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 86#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
81#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) 87#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
@@ -710,21 +716,21 @@
710#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 716#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
711#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) 717#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
712#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 718#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
713#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) 719#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
714#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 720#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
715#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) 721#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
716#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) 722#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
717#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) 723#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
718#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) 724#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
719#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) 725#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
720#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) 726#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
721#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) 727#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
722#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) 728#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
723#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) 729#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
724#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) 730#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
725#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) 731#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
726#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) 732#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
727#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) 733#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
728#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) 734#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
729#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) 735#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
730#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) 736#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
@@ -734,23 +740,23 @@
734#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) 740#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
735#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) 741#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
736#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) 742#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
737#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) 743#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
738#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) 744#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
739#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) 745#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
740#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) 746#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
741#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) 747#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
742#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) 748#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
743#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) 749#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
744#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) 750#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
745#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) 751#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
746#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) 752#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
747#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) 753#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
748#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) 754#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
749#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) 755#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
750#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) 756#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
751#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) 757#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
752#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) 758#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
753#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) 759#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
754#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) 760#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
755#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) 761#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
756#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) 762#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
@@ -763,9 +769,9 @@
763/* MDMA Stream 1 Registers */ 769/* MDMA Stream 1 Registers */
764 770
765#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) 771#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
766#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) 772#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
767#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) 773#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
768#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) 774#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
769#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) 775#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
770#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) 776#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
771#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 777#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
@@ -777,9 +783,9 @@
777#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 783#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
778#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) 784#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
779#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 785#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
780#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) 786#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
781#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 787#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
782#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) 788#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
783#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) 789#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
784#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) 790#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
785#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) 791#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
@@ -789,9 +795,9 @@
789#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) 795#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
790#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) 796#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
791#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) 797#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
792#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) 798#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
793#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) 799#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
794#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) 800#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
795#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) 801#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
796#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) 802#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
797#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 803#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
@@ -803,9 +809,9 @@
803#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 809#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
804#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) 810#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
805#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 811#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
806#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) 812#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
807#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 813#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
808#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) 814#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
809#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) 815#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
810#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) 816#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
811#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) 817#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index ac968fca5cc5..32d07130200c 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -362,7 +362,6 @@
362/* Bit masks for KPAD_CTL */ 362/* Bit masks for KPAD_CTL */
363 363
364#define KPAD_EN 0x1 /* Keypad Enable */ 364#define KPAD_EN 0x1 /* Keypad Enable */
365#define nKPAD_EN 0x0
366#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 365#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
367#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 366#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
368#define KPAD_COLEN 0xe000 /* Column Enable Width */ 367#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -384,29 +383,21 @@
384/* Bit masks for KPAD_STAT */ 383/* Bit masks for KPAD_STAT */
385 384
386#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 385#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
387#define nKPAD_IRQ 0x0
388#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 386#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
389#define KPAD_PRESSED 0x8 /* Key press current status */ 387#define KPAD_PRESSED 0x8 /* Key press current status */
390#define nKPAD_PRESSED 0x0
391 388
392/* Bit masks for KPAD_SOFTEVAL */ 389/* Bit masks for KPAD_SOFTEVAL */
393 390
394#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 391#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
395#define nKPAD_SOFTEVAL_E 0x0
396 392
397/* Bit masks for SDH_COMMAND */ 393/* Bit masks for SDH_COMMAND */
398 394
399#define CMD_IDX 0x3f /* Command Index */ 395#define CMD_IDX 0x3f /* Command Index */
400#define CMD_RSP 0x40 /* Response */ 396#define CMD_RSP 0x40 /* Response */
401#define nCMD_RSP 0x0
402#define CMD_L_RSP 0x80 /* Long Response */ 397#define CMD_L_RSP 0x80 /* Long Response */
403#define nCMD_L_RSP 0x0
404#define CMD_INT_E 0x100 /* Command Interrupt */ 398#define CMD_INT_E 0x100 /* Command Interrupt */
405#define nCMD_INT_E 0x0
406#define CMD_PEND_E 0x200 /* Command Pending */ 399#define CMD_PEND_E 0x200 /* Command Pending */
407#define nCMD_PEND_E 0x0
408#define CMD_E 0x400 /* Command Enable */ 400#define CMD_E 0x400 /* Command Enable */
409#define nCMD_E 0x0
410 401
411/* Bit masks for SDH_PWR_CTL */ 402/* Bit masks for SDH_PWR_CTL */
412 403
@@ -415,21 +406,15 @@
415#define TBD 0x3c /* TBD */ 406#define TBD 0x3c /* TBD */
416#endif 407#endif
417#define SD_CMD_OD 0x40 /* Open Drain Output */ 408#define SD_CMD_OD 0x40 /* Open Drain Output */
418#define nSD_CMD_OD 0x0
419#define ROD_CTL 0x80 /* Rod Control */ 409#define ROD_CTL 0x80 /* Rod Control */
420#define nROD_CTL 0x0
421 410
422/* Bit masks for SDH_CLK_CTL */ 411/* Bit masks for SDH_CLK_CTL */
423 412
424#define CLKDIV 0xff /* MC_CLK Divisor */ 413#define CLKDIV 0xff /* MC_CLK Divisor */
425#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 414#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
426#define nCLK_E 0x0
427#define PWR_SV_E 0x200 /* Power Save Enable */ 415#define PWR_SV_E 0x200 /* Power Save Enable */
428#define nPWR_SV_E 0x0
429#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 416#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
430#define nCLKDIV_BYPASS 0x0
431#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 417#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
432#define nWIDE_BUS 0x0
433 418
434/* Bit masks for SDH_RESP_CMD */ 419/* Bit masks for SDH_RESP_CMD */
435 420
@@ -438,133 +423,74 @@
438/* Bit masks for SDH_DATA_CTL */ 423/* Bit masks for SDH_DATA_CTL */
439 424
440#define DTX_E 0x1 /* Data Transfer Enable */ 425#define DTX_E 0x1 /* Data Transfer Enable */
441#define nDTX_E 0x0
442#define DTX_DIR 0x2 /* Data Transfer Direction */ 426#define DTX_DIR 0x2 /* Data Transfer Direction */
443#define nDTX_DIR 0x0
444#define DTX_MODE 0x4 /* Data Transfer Mode */ 427#define DTX_MODE 0x4 /* Data Transfer Mode */
445#define nDTX_MODE 0x0
446#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 428#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
447#define nDTX_DMA_E 0x0
448#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 429#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
449 430
450/* Bit masks for SDH_STATUS */ 431/* Bit masks for SDH_STATUS */
451 432
452#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
453#define nCMD_CRC_FAIL 0x0
454#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
455#define nDAT_CRC_FAIL 0x0
456#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 435#define CMD_TIMEOUT 0x4 /* CMD Time Out */
457#define nCMD_TIMEOUT 0x0
458#define DAT_TIMEOUT 0x8 /* Data Time Out */ 436#define DAT_TIMEOUT 0x8 /* Data Time Out */
459#define nDAT_TIMEOUT 0x0
460#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
461#define nTX_UNDERRUN 0x0
462#define RX_OVERRUN 0x20 /* Receive Overrun */ 438#define RX_OVERRUN 0x20 /* Receive Overrun */
463#define nRX_OVERRUN 0x0
464#define CMD_RESP_END 0x40 /* CMD Response End */ 439#define CMD_RESP_END 0x40 /* CMD Response End */
465#define nCMD_RESP_END 0x0
466#define CMD_SENT 0x80 /* CMD Sent */ 440#define CMD_SENT 0x80 /* CMD Sent */
467#define nCMD_SENT 0x0
468#define DAT_END 0x100 /* Data End */ 441#define DAT_END 0x100 /* Data End */
469#define nDAT_END 0x0
470#define START_BIT_ERR 0x200 /* Start Bit Error */ 442#define START_BIT_ERR 0x200 /* Start Bit Error */
471#define nSTART_BIT_ERR 0x0
472#define DAT_BLK_END 0x400 /* Data Block End */ 443#define DAT_BLK_END 0x400 /* Data Block End */
473#define nDAT_BLK_END 0x0
474#define CMD_ACT 0x800 /* CMD Active */ 444#define CMD_ACT 0x800 /* CMD Active */
475#define nCMD_ACT 0x0
476#define TX_ACT 0x1000 /* Transmit Active */ 445#define TX_ACT 0x1000 /* Transmit Active */
477#define nTX_ACT 0x0
478#define RX_ACT 0x2000 /* Receive Active */ 446#define RX_ACT 0x2000 /* Receive Active */
479#define nRX_ACT 0x0
480#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 447#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
481#define nTX_FIFO_STAT 0x0
482#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 448#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
483#define nRX_FIFO_STAT 0x0
484#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 449#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
485#define nTX_FIFO_FULL 0x0
486#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 450#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
487#define nRX_FIFO_FULL 0x0
488#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 451#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
489#define nTX_FIFO_ZERO 0x0
490#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 452#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
491#define nRX_DAT_ZERO 0x0
492#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 453#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
493#define nTX_DAT_RDY 0x0
494#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 454#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
495#define nRX_FIFO_RDY 0x0
496 455
497/* Bit masks for SDH_STATUS_CLR */ 456/* Bit masks for SDH_STATUS_CLR */
498 457
499#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 458#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
500#define nCMD_CRC_FAIL_STAT 0x0
501#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 459#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
502#define nDAT_CRC_FAIL_STAT 0x0
503#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 460#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
504#define nCMD_TIMEOUT_STAT 0x0
505#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 461#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
506#define nDAT_TIMEOUT_STAT 0x0
507#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 462#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
508#define nTX_UNDERRUN_STAT 0x0
509#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 463#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
510#define nRX_OVERRUN_STAT 0x0
511#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 464#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
512#define nCMD_RESP_END_STAT 0x0
513#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 465#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
514#define nCMD_SENT_STAT 0x0
515#define DAT_END_STAT 0x100 /* Data End Status */ 466#define DAT_END_STAT 0x100 /* Data End Status */
516#define nDAT_END_STAT 0x0
517#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 467#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
518#define nSTART_BIT_ERR_STAT 0x0
519#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 468#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
520#define nDAT_BLK_END_STAT 0x0
521 469
522/* Bit masks for SDH_MASK0 */ 470/* Bit masks for SDH_MASK0 */
523 471
524#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 472#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
525#define nCMD_CRC_FAIL_MASK 0x0
526#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 473#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
527#define nDAT_CRC_FAIL_MASK 0x0
528#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 474#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
529#define nCMD_TIMEOUT_MASK 0x0
530#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 475#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
531#define nDAT_TIMEOUT_MASK 0x0
532#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 476#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
533#define nTX_UNDERRUN_MASK 0x0
534#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 477#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
535#define nRX_OVERRUN_MASK 0x0
536#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 478#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
537#define nCMD_RESP_END_MASK 0x0
538#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 479#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
539#define nCMD_SENT_MASK 0x0
540#define DAT_END_MASK 0x100 /* Data End Mask */ 480#define DAT_END_MASK 0x100 /* Data End Mask */
541#define nDAT_END_MASK 0x0
542#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 481#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
543#define nSTART_BIT_ERR_MASK 0x0
544#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 482#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
545#define nDAT_BLK_END_MASK 0x0
546#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 483#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
547#define nCMD_ACT_MASK 0x0
548#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 484#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
549#define nTX_ACT_MASK 0x0
550#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 485#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
551#define nRX_ACT_MASK 0x0
552#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 486#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
553#define nTX_FIFO_STAT_MASK 0x0
554#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 487#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
555#define nRX_FIFO_STAT_MASK 0x0
556#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 488#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
557#define nTX_FIFO_FULL_MASK 0x0
558#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 489#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
559#define nRX_FIFO_FULL_MASK 0x0
560#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 490#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
561#define nTX_FIFO_ZERO_MASK 0x0
562#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 491#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
563#define nRX_DAT_ZERO_MASK 0x0
564#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 492#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
565#define nTX_DAT_RDY_MASK 0x0
566#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 493#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
567#define nRX_FIFO_RDY_MASK 0x0
568 494
569/* Bit masks for SDH_FIFO_CNT */ 495/* Bit masks for SDH_FIFO_CNT */
570 496
@@ -573,73 +499,47 @@
573/* Bit masks for SDH_E_STATUS */ 499/* Bit masks for SDH_E_STATUS */
574 500
575#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 501#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
576#define nSDIO_INT_DET 0x0
577#define SD_CARD_DET 0x10 /* SD Card Detect */ 502#define SD_CARD_DET 0x10 /* SD Card Detect */
578#define nSD_CARD_DET 0x0
579 503
580/* Bit masks for SDH_E_MASK */ 504/* Bit masks for SDH_E_MASK */
581 505
582#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 506#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
583#define nSDIO_MSK 0x0
584#define SCD_MSK 0x40 /* Mask Card Detect */ 507#define SCD_MSK 0x40 /* Mask Card Detect */
585#define nSCD_MSK 0x0
586 508
587/* Bit masks for SDH_CFG */ 509/* Bit masks for SDH_CFG */
588 510
589#define CLKS_EN 0x1 /* Clocks Enable */ 511#define CLKS_EN 0x1 /* Clocks Enable */
590#define nCLKS_EN 0x0
591#define SD4E 0x4 /* SDIO 4-Bit Enable */ 512#define SD4E 0x4 /* SDIO 4-Bit Enable */
592#define nSD4E 0x0
593#define MWE 0x8 /* Moving Window Enable */ 513#define MWE 0x8 /* Moving Window Enable */
594#define nMWE 0x0
595#define SD_RST 0x10 /* SDMMC Reset */ 514#define SD_RST 0x10 /* SDMMC Reset */
596#define nSD_RST 0x0
597#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 515#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
598#define nPUP_SDDAT 0x0
599#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 516#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
600#define nPUP_SDDAT3 0x0
601#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 517#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
602#define nPD_SDDAT3 0x0
603 518
604/* Bit masks for SDH_RD_WAIT_EN */ 519/* Bit masks for SDH_RD_WAIT_EN */
605 520
606#define RWR 0x1 /* Read Wait Request */ 521#define RWR 0x1 /* Read Wait Request */
607#define nRWR 0x0
608 522
609/* Bit masks for ATAPI_CONTROL */ 523/* Bit masks for ATAPI_CONTROL */
610 524
611#define PIO_START 0x1 /* Start PIO/Reg Op */ 525#define PIO_START 0x1 /* Start PIO/Reg Op */
612#define nPIO_START 0x0
613#define MULTI_START 0x2 /* Start Multi-DMA Op */ 526#define MULTI_START 0x2 /* Start Multi-DMA Op */
614#define nMULTI_START 0x0
615#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 527#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
616#define nULTRA_START 0x0
617#define XFER_DIR 0x8 /* Transfer Direction */ 528#define XFER_DIR 0x8 /* Transfer Direction */
618#define nXFER_DIR 0x0
619#define IORDY_EN 0x10 /* IORDY Enable */ 529#define IORDY_EN 0x10 /* IORDY Enable */
620#define nIORDY_EN 0x0
621#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 530#define FIFO_FLUSH 0x20 /* Flush FIFOs */
622#define nFIFO_FLUSH 0x0
623#define SOFT_RST 0x40 /* Soft Reset */ 531#define SOFT_RST 0x40 /* Soft Reset */
624#define nSOFT_RST 0x0
625#define DEV_RST 0x80 /* Device Reset */ 532#define DEV_RST 0x80 /* Device Reset */
626#define nDEV_RST 0x0
627#define TFRCNT_RST 0x100 /* Trans Count Reset */ 533#define TFRCNT_RST 0x100 /* Trans Count Reset */
628#define nTFRCNT_RST 0x0
629#define END_ON_TERM 0x200 /* End/Terminate Select */ 534#define END_ON_TERM 0x200 /* End/Terminate Select */
630#define nEND_ON_TERM 0x0
631#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 535#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
632#define nPIO_USE_DMA 0x0
633#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 536#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
634 537
635/* Bit masks for ATAPI_STATUS */ 538/* Bit masks for ATAPI_STATUS */
636 539
637#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 540#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
638#define nPIO_XFER_ON 0x0
639#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 541#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
640#define nMULTI_XFER_ON 0x0
641#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 542#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
642#define nULTRA_XFER_ON 0x0
643#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 543#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
644 544
645/* Bit masks for ATAPI_DEV_ADDR */ 545/* Bit masks for ATAPI_DEV_ADDR */
@@ -649,66 +549,39 @@
649/* Bit masks for ATAPI_INT_MASK */ 549/* Bit masks for ATAPI_INT_MASK */
650 550
651#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 551#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
652#define nATAPI_DEV_INT_MASK 0x0
653#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 552#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
654#define nPIO_DONE_MASK 0x0
655#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 553#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
656#define nMULTI_DONE_MASK 0x0
657#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 554#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
658#define nUDMAIN_DONE_MASK 0x0
659#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 555#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
660#define nUDMAOUT_DONE_MASK 0x0
661#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 556#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
662#define nHOST_TERM_XFER_MASK 0x0
663#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 557#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
664#define nMULTI_TERM_MASK 0x0
665#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 558#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
666#define nUDMAIN_TERM_MASK 0x0
667#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 559#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
668#define nUDMAOUT_TERM_MASK 0x0
669 560
670/* Bit masks for ATAPI_INT_STATUS */ 561/* Bit masks for ATAPI_INT_STATUS */
671 562
672#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 563#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
673#define nATAPI_DEV_INT 0x0
674#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 564#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
675#define nPIO_DONE_INT 0x0
676#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 565#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
677#define nMULTI_DONE_INT 0x0
678#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 566#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
679#define nUDMAIN_DONE_INT 0x0
680#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 567#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
681#define nUDMAOUT_DONE_INT 0x0
682#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 568#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
683#define nHOST_TERM_XFER_INT 0x0
684#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 569#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
685#define nMULTI_TERM_INT 0x0
686#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 570#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
687#define nUDMAIN_TERM_INT 0x0
688#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 571#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
689#define nUDMAOUT_TERM_INT 0x0
690 572
691/* Bit masks for ATAPI_LINE_STATUS */ 573/* Bit masks for ATAPI_LINE_STATUS */
692 574
693#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 575#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
694#define nATAPI_INTR 0x0
695#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 576#define ATAPI_DASP 0x2 /* Device dasp to host line status */
696#define nATAPI_DASP 0x0
697#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 577#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
698#define nATAPI_CS0N 0x0
699#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 578#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
700#define nATAPI_CS1N 0x0
701#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 579#define ATAPI_ADDR 0x70 /* ATAPI address line status */
702#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 580#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703#define nATAPI_DMAREQ 0x0
704#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 581#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
705#define nATAPI_DMAACKN 0x0
706#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 582#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
707#define nATAPI_DIOWN 0x0
708#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 583#define ATAPI_DIORN 0x400 /* ATAPI read line status */
709#define nATAPI_DIORN 0x0
710#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 584#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
711#define nATAPI_IORDY 0x0
712 585
713/* Bit masks for ATAPI_SM_STATE */ 586/* Bit masks for ATAPI_SM_STATE */
714 587
@@ -720,7 +593,6 @@
720/* Bit masks for ATAPI_TERMINATE */ 593/* Bit masks for ATAPI_TERMINATE */
721 594
722#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 595#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
723#define nATAPI_HOST_TERM 0x0
724 596
725/* Bit masks for ATAPI_REG_TIM_0 */ 597/* Bit masks for ATAPI_REG_TIM_0 */
726 598
@@ -779,131 +651,77 @@
779/* Bit masks for USB_POWER */ 651/* Bit masks for USB_POWER */
780 652
781#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 653#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
782#define nENABLE_SUSPENDM 0x0
783#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 654#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
784#define nSUSPEND_MODE 0x0
785#define RESUME_MODE 0x4 /* DMA Mode */ 655#define RESUME_MODE 0x4 /* DMA Mode */
786#define nRESUME_MODE 0x0
787#define RESET 0x8 /* Reset indicator */ 656#define RESET 0x8 /* Reset indicator */
788#define nRESET 0x0
789#define HS_MODE 0x10 /* High Speed mode indicator */ 657#define HS_MODE 0x10 /* High Speed mode indicator */
790#define nHS_MODE 0x0
791#define HS_ENABLE 0x20 /* high Speed Enable */ 658#define HS_ENABLE 0x20 /* high Speed Enable */
792#define nHS_ENABLE 0x0
793#define SOFT_CONN 0x40 /* Soft connect */ 659#define SOFT_CONN 0x40 /* Soft connect */
794#define nSOFT_CONN 0x0
795#define ISO_UPDATE 0x80 /* Isochronous update */ 660#define ISO_UPDATE 0x80 /* Isochronous update */
796#define nISO_UPDATE 0x0
797 661
798/* Bit masks for USB_INTRTX */ 662/* Bit masks for USB_INTRTX */
799 663
800#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 664#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
801#define nEP0_TX 0x0
802#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 665#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
803#define nEP1_TX 0x0
804#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 666#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
805#define nEP2_TX 0x0
806#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 667#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
807#define nEP3_TX 0x0
808#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 668#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
809#define nEP4_TX 0x0
810#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 669#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
811#define nEP5_TX 0x0
812#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 670#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
813#define nEP6_TX 0x0
814#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 671#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
815#define nEP7_TX 0x0
816 672
817/* Bit masks for USB_INTRRX */ 673/* Bit masks for USB_INTRRX */
818 674
819#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 675#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
820#define nEP1_RX 0x0
821#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 676#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
822#define nEP2_RX 0x0
823#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 677#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
824#define nEP3_RX 0x0
825#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 678#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
826#define nEP4_RX 0x0
827#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 679#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
828#define nEP5_RX 0x0
829#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 680#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
830#define nEP6_RX 0x0
831#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 681#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
832#define nEP7_RX 0x0
833 682
834/* Bit masks for USB_INTRTXE */ 683/* Bit masks for USB_INTRTXE */
835 684
836#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 685#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
837#define nEP0_TX_E 0x0
838#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 686#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
839#define nEP1_TX_E 0x0
840#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 687#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
841#define nEP2_TX_E 0x0
842#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 688#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
843#define nEP3_TX_E 0x0
844#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 689#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
845#define nEP4_TX_E 0x0
846#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 690#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
847#define nEP5_TX_E 0x0
848#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 691#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
849#define nEP6_TX_E 0x0
850#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 692#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
851#define nEP7_TX_E 0x0
852 693
853/* Bit masks for USB_INTRRXE */ 694/* Bit masks for USB_INTRRXE */
854 695
855#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 696#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
856#define nEP1_RX_E 0x0
857#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 697#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
858#define nEP2_RX_E 0x0
859#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 698#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
860#define nEP3_RX_E 0x0
861#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 699#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
862#define nEP4_RX_E 0x0
863#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 700#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
864#define nEP5_RX_E 0x0
865#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 701#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
866#define nEP6_RX_E 0x0
867#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 702#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
868#define nEP7_RX_E 0x0
869 703
870/* Bit masks for USB_INTRUSB */ 704/* Bit masks for USB_INTRUSB */
871 705
872#define SUSPEND_B 0x1 /* Suspend indicator */ 706#define SUSPEND_B 0x1 /* Suspend indicator */
873#define nSUSPEND_B 0x0
874#define RESUME_B 0x2 /* Resume indicator */ 707#define RESUME_B 0x2 /* Resume indicator */
875#define nRESUME_B 0x0
876#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 708#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
877#define nRESET_OR_BABLE_B 0x0
878#define SOF_B 0x8 /* Start of frame */ 709#define SOF_B 0x8 /* Start of frame */
879#define nSOF_B 0x0
880#define CONN_B 0x10 /* Connection indicator */ 710#define CONN_B 0x10 /* Connection indicator */
881#define nCONN_B 0x0
882#define DISCON_B 0x20 /* Disconnect indicator */ 711#define DISCON_B 0x20 /* Disconnect indicator */
883#define nDISCON_B 0x0
884#define SESSION_REQ_B 0x40 /* Session Request */ 712#define SESSION_REQ_B 0x40 /* Session Request */
885#define nSESSION_REQ_B 0x0
886#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 713#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
887#define nVBUS_ERROR_B 0x0
888 714
889/* Bit masks for USB_INTRUSBE */ 715/* Bit masks for USB_INTRUSBE */
890 716
891#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 717#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
892#define nSUSPEND_BE 0x0
893#define RESUME_BE 0x2 /* Resume indicator int enable */ 718#define RESUME_BE 0x2 /* Resume indicator int enable */
894#define nRESUME_BE 0x0
895#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 719#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
896#define nRESET_OR_BABLE_BE 0x0
897#define SOF_BE 0x8 /* Start of frame int enable */ 720#define SOF_BE 0x8 /* Start of frame int enable */
898#define nSOF_BE 0x0
899#define CONN_BE 0x10 /* Connection indicator int enable */ 721#define CONN_BE 0x10 /* Connection indicator int enable */
900#define nCONN_BE 0x0
901#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 722#define DISCON_BE 0x20 /* Disconnect indicator int enable */
902#define nDISCON_BE 0x0
903#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 723#define SESSION_REQ_BE 0x40 /* Session Request int enable */
904#define nSESSION_REQ_BE 0x0
905#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 724#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
906#define nVBUS_ERROR_BE 0x0
907 725
908/* Bit masks for USB_FRAME */ 726/* Bit masks for USB_FRAME */
909 727
@@ -916,117 +734,67 @@
916/* Bit masks for USB_GLOBAL_CTL */ 734/* Bit masks for USB_GLOBAL_CTL */
917 735
918#define GLOBAL_ENA 0x1 /* enables USB module */ 736#define GLOBAL_ENA 0x1 /* enables USB module */
919#define nGLOBAL_ENA 0x0
920#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 737#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
921#define nEP1_TX_ENA 0x0
922#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 738#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
923#define nEP2_TX_ENA 0x0
924#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 739#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
925#define nEP3_TX_ENA 0x0
926#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 740#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
927#define nEP4_TX_ENA 0x0
928#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 741#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
929#define nEP5_TX_ENA 0x0
930#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 742#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
931#define nEP6_TX_ENA 0x0
932#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 743#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
933#define nEP7_TX_ENA 0x0
934#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 744#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
935#define nEP1_RX_ENA 0x0
936#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 745#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
937#define nEP2_RX_ENA 0x0
938#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 746#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
939#define nEP3_RX_ENA 0x0
940#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 747#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
941#define nEP4_RX_ENA 0x0
942#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 748#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
943#define nEP5_RX_ENA 0x0
944#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 749#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
945#define nEP6_RX_ENA 0x0
946#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 750#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
947#define nEP7_RX_ENA 0x0
948 751
949/* Bit masks for USB_OTG_DEV_CTL */ 752/* Bit masks for USB_OTG_DEV_CTL */
950 753
951#define SESSION 0x1 /* session indicator */ 754#define SESSION 0x1 /* session indicator */
952#define nSESSION 0x0
953#define HOST_REQ 0x2 /* Host negotiation request */ 755#define HOST_REQ 0x2 /* Host negotiation request */
954#define nHOST_REQ 0x0
955#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 756#define HOST_MODE 0x4 /* indicates USBDRC is a host */
956#define nHOST_MODE 0x0
957#define VBUS0 0x8 /* Vbus level indicator[0] */ 757#define VBUS0 0x8 /* Vbus level indicator[0] */
958#define nVBUS0 0x0
959#define VBUS1 0x10 /* Vbus level indicator[1] */ 758#define VBUS1 0x10 /* Vbus level indicator[1] */
960#define nVBUS1 0x0
961#define LSDEV 0x20 /* Low-speed indicator */ 759#define LSDEV 0x20 /* Low-speed indicator */
962#define nLSDEV 0x0
963#define FSDEV 0x40 /* Full or High-speed indicator */ 760#define FSDEV 0x40 /* Full or High-speed indicator */
964#define nFSDEV 0x0
965#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 761#define B_DEVICE 0x80 /* A' or 'B' device indicator */
966#define nB_DEVICE 0x0
967 762
968/* Bit masks for USB_OTG_VBUS_IRQ */ 763/* Bit masks for USB_OTG_VBUS_IRQ */
969 764
970#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 765#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
971#define nDRIVE_VBUS_ON 0x0
972#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 766#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
973#define nDRIVE_VBUS_OFF 0x0
974#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 767#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
975#define nCHRG_VBUS_START 0x0
976#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 768#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
977#define nCHRG_VBUS_END 0x0
978#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 769#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
979#define nDISCHRG_VBUS_START 0x0
980#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 770#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
981#define nDISCHRG_VBUS_END 0x0
982 771
983/* Bit masks for USB_OTG_VBUS_MASK */ 772/* Bit masks for USB_OTG_VBUS_MASK */
984 773
985#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 774#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
986#define nDRIVE_VBUS_ON_ENA 0x0
987#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 775#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
988#define nDRIVE_VBUS_OFF_ENA 0x0
989#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 776#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
990#define nCHRG_VBUS_START_ENA 0x0
991#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 777#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
992#define nCHRG_VBUS_END_ENA 0x0
993#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 778#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
994#define nDISCHRG_VBUS_START_ENA 0x0
995#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 779#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
996#define nDISCHRG_VBUS_END_ENA 0x0
997 780
998/* Bit masks for USB_CSR0 */ 781/* Bit masks for USB_CSR0 */
999 782
1000#define RXPKTRDY 0x1 /* data packet receive indicator */ 783#define RXPKTRDY 0x1 /* data packet receive indicator */
1001#define nRXPKTRDY 0x0
1002#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 784#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1003#define nTXPKTRDY 0x0
1004#define STALL_SENT 0x4 /* STALL handshake sent */ 785#define STALL_SENT 0x4 /* STALL handshake sent */
1005#define nSTALL_SENT 0x0
1006#define DATAEND 0x8 /* Data end indicator */ 786#define DATAEND 0x8 /* Data end indicator */
1007#define nDATAEND 0x0
1008#define SETUPEND 0x10 /* Setup end */ 787#define SETUPEND 0x10 /* Setup end */
1009#define nSETUPEND 0x0
1010#define SENDSTALL 0x20 /* Send STALL handshake */ 788#define SENDSTALL 0x20 /* Send STALL handshake */
1011#define nSENDSTALL 0x0
1012#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 789#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1013#define nSERVICED_RXPKTRDY 0x0
1014#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 790#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1015#define nSERVICED_SETUPEND 0x0
1016#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 791#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1017#define nFLUSHFIFO 0x0
1018#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 792#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1019#define nSTALL_RECEIVED_H 0x0
1020#define SETUPPKT_H 0x8 /* send Setup token host mode */ 793#define SETUPPKT_H 0x8 /* send Setup token host mode */
1021#define nSETUPPKT_H 0x0
1022#define ERROR_H 0x10 /* timeout error indicator host mode */ 794#define ERROR_H 0x10 /* timeout error indicator host mode */
1023#define nERROR_H 0x0
1024#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 795#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1025#define nREQPKT_H 0x0
1026#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 796#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1027#define nSTATUSPKT_H 0x0
1028#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 797#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1029#define nNAK_TIMEOUT_H 0x0
1030 798
1031/* Bit masks for USB_COUNT0 */ 799/* Bit masks for USB_COUNT0 */
1032 800
@@ -1047,37 +815,21 @@
1047/* Bit masks for USB_TXCSR */ 815/* Bit masks for USB_TXCSR */
1048 816
1049#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 817#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1050#define nTXPKTRDY_T 0x0
1051#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 818#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1052#define nFIFO_NOT_EMPTY_T 0x0
1053#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 819#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1054#define nUNDERRUN_T 0x0
1055#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 820#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1056#define nFLUSHFIFO_T 0x0
1057#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 821#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1058#define nSTALL_SEND_T 0x0
1059#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 822#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1060#define nSTALL_SENT_T 0x0
1061#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 823#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1062#define nCLEAR_DATATOGGLE_T 0x0
1063#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 824#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1064#define nINCOMPTX_T 0x0
1065#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 825#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1066#define nDMAREQMODE_T 0x0
1067#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 826#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1068#define nFORCE_DATATOGGLE_T 0x0
1069#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 827#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1070#define nDMAREQ_ENA_T 0x0
1071#define ISO_T 0x4000 /* enable Isochronous transfers */ 828#define ISO_T 0x4000 /* enable Isochronous transfers */
1072#define nISO_T 0x0
1073#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 829#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1074#define nAUTOSET_T 0x0
1075#define ERROR_TH 0x4 /* error condition host mode */ 830#define ERROR_TH 0x4 /* error condition host mode */
1076#define nERROR_TH 0x0
1077#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 831#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1078#define nSTALL_RECEIVED_TH 0x0
1079#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 832#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1080#define nNAK_TIMEOUT_TH 0x0
1081 833
1082/* Bit masks for USB_TXCOUNT */ 834/* Bit masks for USB_TXCOUNT */
1083 835
@@ -1086,45 +838,25 @@
1086/* Bit masks for USB_RXCSR */ 838/* Bit masks for USB_RXCSR */
1087 839
1088#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 840#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1089#define nRXPKTRDY_R 0x0
1090#define FIFO_FULL_R 0x2 /* FIFO not empty */ 841#define FIFO_FULL_R 0x2 /* FIFO not empty */
1091#define nFIFO_FULL_R 0x0
1092#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 842#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1093#define nOVERRUN_R 0x0
1094#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 843#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1095#define nDATAERROR_R 0x0
1096#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 844#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1097#define nFLUSHFIFO_R 0x0
1098#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 845#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1099#define nSTALL_SEND_R 0x0
1100#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 846#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1101#define nSTALL_SENT_R 0x0
1102#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 847#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1103#define nCLEAR_DATATOGGLE_R 0x0
1104#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 848#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1105#define nINCOMPRX_R 0x0
1106#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 849#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1107#define nDMAREQMODE_R 0x0
1108#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 850#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1109#define nDISNYET_R 0x0
1110#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 851#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1111#define nDMAREQ_ENA_R 0x0
1112#define ISO_R 0x4000 /* enable Isochronous transfers */ 852#define ISO_R 0x4000 /* enable Isochronous transfers */
1113#define nISO_R 0x0
1114#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 853#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1115#define nAUTOCLEAR_R 0x0
1116#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 854#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1117#define nERROR_RH 0x0
1118#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 855#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1119#define nREQPKT_RH 0x0
1120#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 856#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1121#define nSTALL_RECEIVED_RH 0x0
1122#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 857#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1123#define nINCOMPRX_RH 0x0
1124#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 858#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1125#define nDMAREQMODE_RH 0x0
1126#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 859#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1127#define nAUTOREQ_RH 0x0
1128 860
1129/* Bit masks for USB_RXCOUNT */ 861/* Bit masks for USB_RXCOUNT */
1130 862
@@ -1151,35 +883,22 @@
1151/* Bit masks for USB_DMA_INTERRUPT */ 883/* Bit masks for USB_DMA_INTERRUPT */
1152 884
1153#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 885#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1154#define nDMA0_INT 0x0
1155#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 886#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1156#define nDMA1_INT 0x0
1157#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 887#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1158#define nDMA2_INT 0x0
1159#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 888#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1160#define nDMA3_INT 0x0
1161#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 889#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1162#define nDMA4_INT 0x0
1163#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 890#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1164#define nDMA5_INT 0x0
1165#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 891#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1166#define nDMA6_INT 0x0
1167#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 892#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1168#define nDMA7_INT 0x0
1169 893
1170/* Bit masks for USB_DMAxCONTROL */ 894/* Bit masks for USB_DMAxCONTROL */
1171 895
1172#define DMA_ENA 0x1 /* DMA enable */ 896#define DMA_ENA 0x1 /* DMA enable */
1173#define nDMA_ENA 0x0
1174#define DIRECTION 0x2 /* direction of DMA transfer */ 897#define DIRECTION 0x2 /* direction of DMA transfer */
1175#define nDIRECTION 0x0
1176#define MODE 0x4 /* DMA Bus error */ 898#define MODE 0x4 /* DMA Bus error */
1177#define nMODE 0x0
1178#define INT_ENA 0x8 /* Interrupt enable */ 899#define INT_ENA 0x8 /* Interrupt enable */
1179#define nINT_ENA 0x0
1180#define EPNUM 0xf0 /* EP number */ 900#define EPNUM 0xf0 /* EP number */
1181#define BUSERROR 0x100 /* DMA Bus error */ 901#define BUSERROR 0x100 /* DMA Bus error */
1182#define nBUSERROR 0x0
1183 902
1184/* Bit masks for USB_DMAxADDRHIGH */ 903/* Bit masks for USB_DMAxADDRHIGH */
1185 904
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 8fc77ea12aa9..dd955dcd39b8 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -538,21 +538,13 @@
538/* Bit masks for PIXC_CTL */ 538/* Bit masks for PIXC_CTL */
539 539
540#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 540#define PIXC_EN 0x1 /* Pixel Compositor Enable */
541#define nPIXC_EN 0x0
542#define OVR_A_EN 0x2 /* Overlay A Enable */ 541#define OVR_A_EN 0x2 /* Overlay A Enable */
543#define nOVR_A_EN 0x0
544#define OVR_B_EN 0x4 /* Overlay B Enable */ 542#define OVR_B_EN 0x4 /* Overlay B Enable */
545#define nOVR_B_EN 0x0
546#define IMG_FORM 0x8 /* Image Data Format */ 543#define IMG_FORM 0x8 /* Image Data Format */
547#define nIMG_FORM 0x0
548#define OVR_FORM 0x10 /* Overlay Data Format */ 544#define OVR_FORM 0x10 /* Overlay Data Format */
549#define nOVR_FORM 0x0
550#define OUT_FORM 0x20 /* Output Data Format */ 545#define OUT_FORM 0x20 /* Output Data Format */
551#define nOUT_FORM 0x0
552#define UDS_MOD 0x40 /* Resampling Mode */ 546#define UDS_MOD 0x40 /* Resampling Mode */
553#define nUDS_MOD 0x0
554#define TC_EN 0x80 /* Transparent Color Enable */ 547#define TC_EN 0x80 /* Transparent Color Enable */
555#define nTC_EN 0x0
556#define IMG_STAT 0x300 /* Image FIFO Status */ 548#define IMG_STAT 0x300 /* Image FIFO Status */
557#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 549#define OVR_STAT 0xc00 /* Overlay FIFO Status */
558#define WM_LVL 0x3000 /* FIFO Watermark Level */ 550#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -600,13 +592,9 @@
600/* Bit masks for PIXC_INTRSTAT */ 592/* Bit masks for PIXC_INTRSTAT */
601 593
602#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 594#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
603#define nOVR_INT_EN 0x0
604#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 595#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
605#define nFRM_INT_EN 0x0
606#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 596#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
607#define nOVR_INT_STAT 0x0
608#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 597#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
609#define nFRM_INT_STAT 0x0
610 598
611/* Bit masks for PIXC_RYCON */ 599/* Bit masks for PIXC_RYCON */
612 600
@@ -614,7 +602,6 @@
614#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 602#define A12 0xffc00 /* A12 in the Coefficient Matrix */
615#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 603#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
616#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 604#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
617#define nRY_MULT4 0x0
618 605
619/* Bit masks for PIXC_GUCON */ 606/* Bit masks for PIXC_GUCON */
620 607
@@ -622,7 +609,6 @@
622#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 609#define A22 0xffc00 /* A22 in the Coefficient Matrix */
623#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 610#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
624#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 611#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
625#define nGU_MULT4 0x0
626 612
627/* Bit masks for PIXC_BVCON */ 613/* Bit masks for PIXC_BVCON */
628 614
@@ -630,7 +616,6 @@
630#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 616#define A32 0xffc00 /* A32 in the Coefficient Matrix */
631#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 617#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
632#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 618#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
633#define nBV_MULT4 0x0
634 619
635/* Bit masks for PIXC_CCBIAS */ 620/* Bit masks for PIXC_CCBIAS */
636 621
@@ -647,48 +632,28 @@
647/* Bit masks for HOST_CONTROL */ 632/* Bit masks for HOST_CONTROL */
648 633
649#define HOST_EN 0x1 /* Host Enable */ 634#define HOST_EN 0x1 /* Host Enable */
650#define nHOST_EN 0x0
651#define HOST_END 0x2 /* Host Endianess */ 635#define HOST_END 0x2 /* Host Endianess */
652#define nHOST_END 0x0
653#define DATA_SIZE 0x4 /* Data Size */ 636#define DATA_SIZE 0x4 /* Data Size */
654#define nDATA_SIZE 0x0
655#define HOST_RST 0x8 /* Host Reset */ 637#define HOST_RST 0x8 /* Host Reset */
656#define nHOST_RST 0x0
657#define HRDY_OVR 0x20 /* Host Ready Override */ 638#define HRDY_OVR 0x20 /* Host Ready Override */
658#define nHRDY_OVR 0x0
659#define INT_MODE 0x40 /* Interrupt Mode */ 639#define INT_MODE 0x40 /* Interrupt Mode */
660#define nINT_MODE 0x0
661#define BT_EN 0x80 /* Bus Timeout Enable */ 640#define BT_EN 0x80 /* Bus Timeout Enable */
662#define nBT_EN 0x0
663#define EHW 0x100 /* Enable Host Write */ 641#define EHW 0x100 /* Enable Host Write */
664#define nEHW 0x0
665#define EHR 0x200 /* Enable Host Read */ 642#define EHR 0x200 /* Enable Host Read */
666#define nEHR 0x0
667#define BDR 0x400 /* Burst DMA Requests */ 643#define BDR 0x400 /* Burst DMA Requests */
668#define nBDR 0x0
669 644
670/* Bit masks for HOST_STATUS */ 645/* Bit masks for HOST_STATUS */
671 646
672#define READY 0x1 /* DMA Ready */ 647#define READY 0x1 /* DMA Ready */
673#define nREADY 0x0
674#define FIFOFULL 0x2 /* FIFO Full */ 648#define FIFOFULL 0x2 /* FIFO Full */
675#define nFIFOFULL 0x0
676#define FIFOEMPTY 0x4 /* FIFO Empty */ 649#define FIFOEMPTY 0x4 /* FIFO Empty */
677#define nFIFOEMPTY 0x0
678#define COMPLETE 0x8 /* DMA Complete */ 650#define COMPLETE 0x8 /* DMA Complete */
679#define nCOMPLETE 0x0
680#define HSHK 0x10 /* Host Handshake */ 651#define HSHK 0x10 /* Host Handshake */
681#define nHSHK 0x0
682#define TIMEOUT 0x20 /* Host Timeout */ 652#define TIMEOUT 0x20 /* Host Timeout */
683#define nTIMEOUT 0x0
684#define HIRQ 0x40 /* Host Interrupt Request */ 653#define HIRQ 0x40 /* Host Interrupt Request */
685#define nHIRQ 0x0
686#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 654#define ALLOW_CNFG 0x80 /* Allow New Configuration */
687#define nALLOW_CNFG 0x0
688#define DMA_DIR 0x100 /* DMA Direction */ 655#define DMA_DIR 0x100 /* DMA Direction */
689#define nDMA_DIR 0x0
690#define BTE 0x200 /* Bus Timeout Enabled */ 656#define BTE 0x200 /* Bus Timeout Enabled */
691#define nBTE 0x0
692 657
693/* Bit masks for HOST_TIMEOUT */ 658/* Bit masks for HOST_TIMEOUT */
694 659
@@ -697,67 +662,42 @@
697/* Bit masks for TIMER_ENABLE1 */ 662/* Bit masks for TIMER_ENABLE1 */
698 663
699#define TIMEN8 0x1 /* Timer 8 Enable */ 664#define TIMEN8 0x1 /* Timer 8 Enable */
700#define nTIMEN8 0x0
701#define TIMEN9 0x2 /* Timer 9 Enable */ 665#define TIMEN9 0x2 /* Timer 9 Enable */
702#define nTIMEN9 0x0
703#define TIMEN10 0x4 /* Timer 10 Enable */ 666#define TIMEN10 0x4 /* Timer 10 Enable */
704#define nTIMEN10 0x0
705 667
706/* Bit masks for TIMER_DISABLE1 */ 668/* Bit masks for TIMER_DISABLE1 */
707 669
708#define TIMDIS8 0x1 /* Timer 8 Disable */ 670#define TIMDIS8 0x1 /* Timer 8 Disable */
709#define nTIMDIS8 0x0
710#define TIMDIS9 0x2 /* Timer 9 Disable */ 671#define TIMDIS9 0x2 /* Timer 9 Disable */
711#define nTIMDIS9 0x0
712#define TIMDIS10 0x4 /* Timer 10 Disable */ 672#define TIMDIS10 0x4 /* Timer 10 Disable */
713#define nTIMDIS10 0x0
714 673
715/* Bit masks for TIMER_STATUS1 */ 674/* Bit masks for TIMER_STATUS1 */
716 675
717#define TIMIL8 0x1 /* Timer 8 Interrupt */ 676#define TIMIL8 0x1 /* Timer 8 Interrupt */
718#define nTIMIL8 0x0
719#define TIMIL9 0x2 /* Timer 9 Interrupt */ 677#define TIMIL9 0x2 /* Timer 9 Interrupt */
720#define nTIMIL9 0x0
721#define TIMIL10 0x4 /* Timer 10 Interrupt */ 678#define TIMIL10 0x4 /* Timer 10 Interrupt */
722#define nTIMIL10 0x0
723#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 679#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
724#define nTOVF_ERR8 0x0
725#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 680#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
726#define nTOVF_ERR9 0x0
727#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 681#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
728#define nTOVF_ERR10 0x0
729#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 682#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
730#define nTRUN8 0x0
731#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 683#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
732#define nTRUN9 0x0
733#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 684#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
734#define nTRUN10 0x0
735 685
736/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 686/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
737 687
738/* Bit masks for HMDMAx_CONTROL */ 688/* Bit masks for HMDMAx_CONTROL */
739 689
740#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 690#define HMDMAEN 0x1 /* Handshake MDMA Enable */
741#define nHMDMAEN 0x0
742#define REP 0x2 /* Handshake MDMA Request Polarity */ 691#define REP 0x2 /* Handshake MDMA Request Polarity */
743#define nREP 0x0
744#define UTE 0x8 /* Urgency Threshold Enable */ 692#define UTE 0x8 /* Urgency Threshold Enable */
745#define nUTE 0x0
746#define OIE 0x10 /* Overflow Interrupt Enable */ 693#define OIE 0x10 /* Overflow Interrupt Enable */
747#define nOIE 0x0
748#define BDIE 0x20 /* Block Done Interrupt Enable */ 694#define BDIE 0x20 /* Block Done Interrupt Enable */
749#define nBDIE 0x0
750#define MBDI 0x40 /* Mask Block Done Interrupt */ 695#define MBDI 0x40 /* Mask Block Done Interrupt */
751#define nMBDI 0x0
752#define DRQ 0x300 /* Handshake MDMA Request Type */ 696#define DRQ 0x300 /* Handshake MDMA Request Type */
753#define RBC 0x1000 /* Force Reload of BCOUNT */ 697#define RBC 0x1000 /* Force Reload of BCOUNT */
754#define nRBC 0x0
755#define PS 0x2000 /* Pin Status */ 698#define PS 0x2000 /* Pin Status */
756#define nPS 0x0
757#define OI 0x4000 /* Overflow Interrupt Generated */ 699#define OI 0x4000 /* Overflow Interrupt Generated */
758#define nOI 0x0
759#define BDI 0x8000 /* Block Done Interrupt Generated */ 700#define BDI 0x8000 /* Block Done Interrupt Generated */
760#define nBDI 0x0
761 701
762/* ******************************************* */ 702/* ******************************************* */
763/* MULTI BIT MACRO ENUMERATIONS */ 703/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index d9e3062a9117..8d4214e0807c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -899,21 +899,13 @@
899/* Bit masks for PIXC_CTL */ 899/* Bit masks for PIXC_CTL */
900 900
901#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 901#define PIXC_EN 0x1 /* Pixel Compositor Enable */
902#define nPIXC_EN 0x0
903#define OVR_A_EN 0x2 /* Overlay A Enable */ 902#define OVR_A_EN 0x2 /* Overlay A Enable */
904#define nOVR_A_EN 0x0
905#define OVR_B_EN 0x4 /* Overlay B Enable */ 903#define OVR_B_EN 0x4 /* Overlay B Enable */
906#define nOVR_B_EN 0x0
907#define IMG_FORM 0x8 /* Image Data Format */ 904#define IMG_FORM 0x8 /* Image Data Format */
908#define nIMG_FORM 0x0
909#define OVR_FORM 0x10 /* Overlay Data Format */ 905#define OVR_FORM 0x10 /* Overlay Data Format */
910#define nOVR_FORM 0x0
911#define OUT_FORM 0x20 /* Output Data Format */ 906#define OUT_FORM 0x20 /* Output Data Format */
912#define nOUT_FORM 0x0
913#define UDS_MOD 0x40 /* Resampling Mode */ 907#define UDS_MOD 0x40 /* Resampling Mode */
914#define nUDS_MOD 0x0
915#define TC_EN 0x80 /* Transparent Color Enable */ 908#define TC_EN 0x80 /* Transparent Color Enable */
916#define nTC_EN 0x0
917#define IMG_STAT 0x300 /* Image FIFO Status */ 909#define IMG_STAT 0x300 /* Image FIFO Status */
918#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 910#define OVR_STAT 0xc00 /* Overlay FIFO Status */
919#define WM_LVL 0x3000 /* FIFO Watermark Level */ 911#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -961,13 +953,9 @@
961/* Bit masks for PIXC_INTRSTAT */ 953/* Bit masks for PIXC_INTRSTAT */
962 954
963#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 955#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
964#define nOVR_INT_EN 0x0
965#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 956#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
966#define nFRM_INT_EN 0x0
967#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 957#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
968#define nOVR_INT_STAT 0x0
969#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 958#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
970#define nFRM_INT_STAT 0x0
971 959
972/* Bit masks for PIXC_RYCON */ 960/* Bit masks for PIXC_RYCON */
973 961
@@ -975,7 +963,6 @@
975#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 963#define A12 0xffc00 /* A12 in the Coefficient Matrix */
976#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 964#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
977#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 965#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
978#define nRY_MULT4 0x0
979 966
980/* Bit masks for PIXC_GUCON */ 967/* Bit masks for PIXC_GUCON */
981 968
@@ -983,7 +970,6 @@
983#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 970#define A22 0xffc00 /* A22 in the Coefficient Matrix */
984#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 971#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
985#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 972#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
986#define nGU_MULT4 0x0
987 973
988/* Bit masks for PIXC_BVCON */ 974/* Bit masks for PIXC_BVCON */
989 975
@@ -991,7 +977,6 @@
991#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 977#define A32 0xffc00 /* A32 in the Coefficient Matrix */
992#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 978#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
993#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 979#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
994#define nBV_MULT4 0x0
995 980
996/* Bit masks for PIXC_CCBIAS */ 981/* Bit masks for PIXC_CCBIAS */
997 982
@@ -1008,48 +993,28 @@
1008/* Bit masks for HOST_CONTROL */ 993/* Bit masks for HOST_CONTROL */
1009 994
1010#define HOST_EN 0x1 /* Host Enable */ 995#define HOST_EN 0x1 /* Host Enable */
1011#define nHOST_EN 0x0
1012#define HOST_END 0x2 /* Host Endianess */ 996#define HOST_END 0x2 /* Host Endianess */
1013#define nHOST_END 0x0
1014#define DATA_SIZE 0x4 /* Data Size */ 997#define DATA_SIZE 0x4 /* Data Size */
1015#define nDATA_SIZE 0x0
1016#define HOST_RST 0x8 /* Host Reset */ 998#define HOST_RST 0x8 /* Host Reset */
1017#define nHOST_RST 0x0
1018#define HRDY_OVR 0x20 /* Host Ready Override */ 999#define HRDY_OVR 0x20 /* Host Ready Override */
1019#define nHRDY_OVR 0x0
1020#define INT_MODE 0x40 /* Interrupt Mode */ 1000#define INT_MODE 0x40 /* Interrupt Mode */
1021#define nINT_MODE 0x0
1022#define BT_EN 0x80 /* Bus Timeout Enable */ 1001#define BT_EN 0x80 /* Bus Timeout Enable */
1023#define nBT_EN 0x0
1024#define EHW 0x100 /* Enable Host Write */ 1002#define EHW 0x100 /* Enable Host Write */
1025#define nEHW 0x0
1026#define EHR 0x200 /* Enable Host Read */ 1003#define EHR 0x200 /* Enable Host Read */
1027#define nEHR 0x0
1028#define BDR 0x400 /* Burst DMA Requests */ 1004#define BDR 0x400 /* Burst DMA Requests */
1029#define nBDR 0x0
1030 1005
1031/* Bit masks for HOST_STATUS */ 1006/* Bit masks for HOST_STATUS */
1032 1007
1033#define READY 0x1 /* DMA Ready */ 1008#define READY 0x1 /* DMA Ready */
1034#define nREADY 0x0
1035#define FIFOFULL 0x2 /* FIFO Full */ 1009#define FIFOFULL 0x2 /* FIFO Full */
1036#define nFIFOFULL 0x0
1037#define FIFOEMPTY 0x4 /* FIFO Empty */ 1010#define FIFOEMPTY 0x4 /* FIFO Empty */
1038#define nFIFOEMPTY 0x0
1039#define COMPLETE 0x8 /* DMA Complete */ 1011#define COMPLETE 0x8 /* DMA Complete */
1040#define nCOMPLETE 0x0
1041#define HSHK 0x10 /* Host Handshake */ 1012#define HSHK 0x10 /* Host Handshake */
1042#define nHSHK 0x0
1043#define TIMEOUT 0x20 /* Host Timeout */ 1013#define TIMEOUT 0x20 /* Host Timeout */
1044#define nTIMEOUT 0x0
1045#define HIRQ 0x40 /* Host Interrupt Request */ 1014#define HIRQ 0x40 /* Host Interrupt Request */
1046#define nHIRQ 0x0
1047#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 1015#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1048#define nALLOW_CNFG 0x0
1049#define DMA_DIR 0x100 /* DMA Direction */ 1016#define DMA_DIR 0x100 /* DMA Direction */
1050#define nDMA_DIR 0x0
1051#define BTE 0x200 /* Bus Timeout Enabled */ 1017#define BTE 0x200 /* Bus Timeout Enabled */
1052#define nBTE 0x0
1053 1018
1054/* Bit masks for HOST_TIMEOUT */ 1019/* Bit masks for HOST_TIMEOUT */
1055 1020
@@ -1058,7 +1023,6 @@
1058/* Bit masks for KPAD_CTL */ 1023/* Bit masks for KPAD_CTL */
1059 1024
1060#define KPAD_EN 0x1 /* Keypad Enable */ 1025#define KPAD_EN 0x1 /* Keypad Enable */
1061#define nKPAD_EN 0x0
1062#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 1026#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1063#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 1027#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1064#define KPAD_COLEN 0xe000 /* Column Enable Width */ 1028#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -1080,29 +1044,21 @@
1080/* Bit masks for KPAD_STAT */ 1044/* Bit masks for KPAD_STAT */
1081 1045
1082#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 1046#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1083#define nKPAD_IRQ 0x0
1084#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 1047#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1085#define KPAD_PRESSED 0x8 /* Key press current status */ 1048#define KPAD_PRESSED 0x8 /* Key press current status */
1086#define nKPAD_PRESSED 0x0
1087 1049
1088/* Bit masks for KPAD_SOFTEVAL */ 1050/* Bit masks for KPAD_SOFTEVAL */
1089 1051
1090#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 1052#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1091#define nKPAD_SOFTEVAL_E 0x0
1092 1053
1093/* Bit masks for SDH_COMMAND */ 1054/* Bit masks for SDH_COMMAND */
1094 1055
1095#define CMD_IDX 0x3f /* Command Index */ 1056#define CMD_IDX 0x3f /* Command Index */
1096#define CMD_RSP 0x40 /* Response */ 1057#define CMD_RSP 0x40 /* Response */
1097#define nCMD_RSP 0x0
1098#define CMD_L_RSP 0x80 /* Long Response */ 1058#define CMD_L_RSP 0x80 /* Long Response */
1099#define nCMD_L_RSP 0x0
1100#define CMD_INT_E 0x100 /* Command Interrupt */ 1059#define CMD_INT_E 0x100 /* Command Interrupt */
1101#define nCMD_INT_E 0x0
1102#define CMD_PEND_E 0x200 /* Command Pending */ 1060#define CMD_PEND_E 0x200 /* Command Pending */
1103#define nCMD_PEND_E 0x0
1104#define CMD_E 0x400 /* Command Enable */ 1061#define CMD_E 0x400 /* Command Enable */
1105#define nCMD_E 0x0
1106 1062
1107/* Bit masks for SDH_PWR_CTL */ 1063/* Bit masks for SDH_PWR_CTL */
1108 1064
@@ -1111,21 +1067,15 @@
1111#define TBD 0x3c /* TBD */ 1067#define TBD 0x3c /* TBD */
1112#endif 1068#endif
1113#define SD_CMD_OD 0x40 /* Open Drain Output */ 1069#define SD_CMD_OD 0x40 /* Open Drain Output */
1114#define nSD_CMD_OD 0x0
1115#define ROD_CTL 0x80 /* Rod Control */ 1070#define ROD_CTL 0x80 /* Rod Control */
1116#define nROD_CTL 0x0
1117 1071
1118/* Bit masks for SDH_CLK_CTL */ 1072/* Bit masks for SDH_CLK_CTL */
1119 1073
1120#define CLKDIV 0xff /* MC_CLK Divisor */ 1074#define CLKDIV 0xff /* MC_CLK Divisor */
1121#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 1075#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1122#define nCLK_E 0x0
1123#define PWR_SV_E 0x200 /* Power Save Enable */ 1076#define PWR_SV_E 0x200 /* Power Save Enable */
1124#define nPWR_SV_E 0x0
1125#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 1077#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1126#define nCLKDIV_BYPASS 0x0
1127#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 1078#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1128#define nWIDE_BUS 0x0
1129 1079
1130/* Bit masks for SDH_RESP_CMD */ 1080/* Bit masks for SDH_RESP_CMD */
1131 1081
@@ -1134,133 +1084,74 @@
1134/* Bit masks for SDH_DATA_CTL */ 1084/* Bit masks for SDH_DATA_CTL */
1135 1085
1136#define DTX_E 0x1 /* Data Transfer Enable */ 1086#define DTX_E 0x1 /* Data Transfer Enable */
1137#define nDTX_E 0x0
1138#define DTX_DIR 0x2 /* Data Transfer Direction */ 1087#define DTX_DIR 0x2 /* Data Transfer Direction */
1139#define nDTX_DIR 0x0
1140#define DTX_MODE 0x4 /* Data Transfer Mode */ 1088#define DTX_MODE 0x4 /* Data Transfer Mode */
1141#define nDTX_MODE 0x0
1142#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 1089#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1143#define nDTX_DMA_E 0x0
1144#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 1090#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1145 1091
1146/* Bit masks for SDH_STATUS */ 1092/* Bit masks for SDH_STATUS */
1147 1093
1148#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 1094#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1149#define nCMD_CRC_FAIL 0x0
1150#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 1095#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1151#define nDAT_CRC_FAIL 0x0
1152#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 1096#define CMD_TIMEOUT 0x4 /* CMD Time Out */
1153#define nCMD_TIMEOUT 0x0
1154#define DAT_TIMEOUT 0x8 /* Data Time Out */ 1097#define DAT_TIMEOUT 0x8 /* Data Time Out */
1155#define nDAT_TIMEOUT 0x0
1156#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 1098#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1157#define nTX_UNDERRUN 0x0
1158#define RX_OVERRUN 0x20 /* Receive Overrun */ 1099#define RX_OVERRUN 0x20 /* Receive Overrun */
1159#define nRX_OVERRUN 0x0
1160#define CMD_RESP_END 0x40 /* CMD Response End */ 1100#define CMD_RESP_END 0x40 /* CMD Response End */
1161#define nCMD_RESP_END 0x0
1162#define CMD_SENT 0x80 /* CMD Sent */ 1101#define CMD_SENT 0x80 /* CMD Sent */
1163#define nCMD_SENT 0x0
1164#define DAT_END 0x100 /* Data End */ 1102#define DAT_END 0x100 /* Data End */
1165#define nDAT_END 0x0
1166#define START_BIT_ERR 0x200 /* Start Bit Error */ 1103#define START_BIT_ERR 0x200 /* Start Bit Error */
1167#define nSTART_BIT_ERR 0x0
1168#define DAT_BLK_END 0x400 /* Data Block End */ 1104#define DAT_BLK_END 0x400 /* Data Block End */
1169#define nDAT_BLK_END 0x0
1170#define CMD_ACT 0x800 /* CMD Active */ 1105#define CMD_ACT 0x800 /* CMD Active */
1171#define nCMD_ACT 0x0
1172#define TX_ACT 0x1000 /* Transmit Active */ 1106#define TX_ACT 0x1000 /* Transmit Active */
1173#define nTX_ACT 0x0
1174#define RX_ACT 0x2000 /* Receive Active */ 1107#define RX_ACT 0x2000 /* Receive Active */
1175#define nRX_ACT 0x0
1176#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 1108#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1177#define nTX_FIFO_STAT 0x0
1178#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 1109#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1179#define nRX_FIFO_STAT 0x0
1180#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 1110#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1181#define nTX_FIFO_FULL 0x0
1182#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 1111#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1183#define nRX_FIFO_FULL 0x0
1184#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 1112#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1185#define nTX_FIFO_ZERO 0x0
1186#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 1113#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1187#define nRX_DAT_ZERO 0x0
1188#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 1114#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1189#define nTX_DAT_RDY 0x0
1190#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 1115#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1191#define nRX_FIFO_RDY 0x0
1192 1116
1193/* Bit masks for SDH_STATUS_CLR */ 1117/* Bit masks for SDH_STATUS_CLR */
1194 1118
1195#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 1119#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1196#define nCMD_CRC_FAIL_STAT 0x0
1197#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 1120#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1198#define nDAT_CRC_FAIL_STAT 0x0
1199#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 1121#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1200#define nCMD_TIMEOUT_STAT 0x0
1201#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 1122#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1202#define nDAT_TIMEOUT_STAT 0x0
1203#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 1123#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1204#define nTX_UNDERRUN_STAT 0x0
1205#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 1124#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1206#define nRX_OVERRUN_STAT 0x0
1207#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 1125#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1208#define nCMD_RESP_END_STAT 0x0
1209#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 1126#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1210#define nCMD_SENT_STAT 0x0
1211#define DAT_END_STAT 0x100 /* Data End Status */ 1127#define DAT_END_STAT 0x100 /* Data End Status */
1212#define nDAT_END_STAT 0x0
1213#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 1128#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1214#define nSTART_BIT_ERR_STAT 0x0
1215#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 1129#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1216#define nDAT_BLK_END_STAT 0x0
1217 1130
1218/* Bit masks for SDH_MASK0 */ 1131/* Bit masks for SDH_MASK0 */
1219 1132
1220#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 1133#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1221#define nCMD_CRC_FAIL_MASK 0x0
1222#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 1134#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1223#define nDAT_CRC_FAIL_MASK 0x0
1224#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 1135#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1225#define nCMD_TIMEOUT_MASK 0x0
1226#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 1136#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1227#define nDAT_TIMEOUT_MASK 0x0
1228#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 1137#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1229#define nTX_UNDERRUN_MASK 0x0
1230#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 1138#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1231#define nRX_OVERRUN_MASK 0x0
1232#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 1139#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1233#define nCMD_RESP_END_MASK 0x0
1234#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 1140#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1235#define nCMD_SENT_MASK 0x0
1236#define DAT_END_MASK 0x100 /* Data End Mask */ 1141#define DAT_END_MASK 0x100 /* Data End Mask */
1237#define nDAT_END_MASK 0x0
1238#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 1142#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1239#define nSTART_BIT_ERR_MASK 0x0
1240#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 1143#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1241#define nDAT_BLK_END_MASK 0x0
1242#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 1144#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1243#define nCMD_ACT_MASK 0x0
1244#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 1145#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1245#define nTX_ACT_MASK 0x0
1246#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 1146#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1247#define nRX_ACT_MASK 0x0
1248#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 1147#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1249#define nTX_FIFO_STAT_MASK 0x0
1250#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 1148#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1251#define nRX_FIFO_STAT_MASK 0x0
1252#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 1149#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1253#define nTX_FIFO_FULL_MASK 0x0
1254#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 1150#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1255#define nRX_FIFO_FULL_MASK 0x0
1256#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 1151#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1257#define nTX_FIFO_ZERO_MASK 0x0
1258#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 1152#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1259#define nRX_DAT_ZERO_MASK 0x0
1260#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 1153#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1261#define nTX_DAT_RDY_MASK 0x0
1262#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 1154#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1263#define nRX_FIFO_RDY_MASK 0x0
1264 1155
1265/* Bit masks for SDH_FIFO_CNT */ 1156/* Bit masks for SDH_FIFO_CNT */
1266 1157
@@ -1269,73 +1160,47 @@
1269/* Bit masks for SDH_E_STATUS */ 1160/* Bit masks for SDH_E_STATUS */
1270 1161
1271#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 1162#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1272#define nSDIO_INT_DET 0x0
1273#define SD_CARD_DET 0x10 /* SD Card Detect */ 1163#define SD_CARD_DET 0x10 /* SD Card Detect */
1274#define nSD_CARD_DET 0x0
1275 1164
1276/* Bit masks for SDH_E_MASK */ 1165/* Bit masks for SDH_E_MASK */
1277 1166
1278#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 1167#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1279#define nSDIO_MSK 0x0
1280#define SCD_MSK 0x40 /* Mask Card Detect */ 1168#define SCD_MSK 0x40 /* Mask Card Detect */
1281#define nSCD_MSK 0x0
1282 1169
1283/* Bit masks for SDH_CFG */ 1170/* Bit masks for SDH_CFG */
1284 1171
1285#define CLKS_EN 0x1 /* Clocks Enable */ 1172#define CLKS_EN 0x1 /* Clocks Enable */
1286#define nCLKS_EN 0x0
1287#define SD4E 0x4 /* SDIO 4-Bit Enable */ 1173#define SD4E 0x4 /* SDIO 4-Bit Enable */
1288#define nSD4E 0x0
1289#define MWE 0x8 /* Moving Window Enable */ 1174#define MWE 0x8 /* Moving Window Enable */
1290#define nMWE 0x0
1291#define SD_RST 0x10 /* SDMMC Reset */ 1175#define SD_RST 0x10 /* SDMMC Reset */
1292#define nSD_RST 0x0
1293#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 1176#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1294#define nPUP_SDDAT 0x0
1295#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 1177#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1296#define nPUP_SDDAT3 0x0
1297#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 1178#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1298#define nPD_SDDAT3 0x0
1299 1179
1300/* Bit masks for SDH_RD_WAIT_EN */ 1180/* Bit masks for SDH_RD_WAIT_EN */
1301 1181
1302#define RWR 0x1 /* Read Wait Request */ 1182#define RWR 0x1 /* Read Wait Request */
1303#define nRWR 0x0
1304 1183
1305/* Bit masks for ATAPI_CONTROL */ 1184/* Bit masks for ATAPI_CONTROL */
1306 1185
1307#define PIO_START 0x1 /* Start PIO/Reg Op */ 1186#define PIO_START 0x1 /* Start PIO/Reg Op */
1308#define nPIO_START 0x0
1309#define MULTI_START 0x2 /* Start Multi-DMA Op */ 1187#define MULTI_START 0x2 /* Start Multi-DMA Op */
1310#define nMULTI_START 0x0
1311#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 1188#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1312#define nULTRA_START 0x0
1313#define XFER_DIR 0x8 /* Transfer Direction */ 1189#define XFER_DIR 0x8 /* Transfer Direction */
1314#define nXFER_DIR 0x0
1315#define IORDY_EN 0x10 /* IORDY Enable */ 1190#define IORDY_EN 0x10 /* IORDY Enable */
1316#define nIORDY_EN 0x0
1317#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 1191#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1318#define nFIFO_FLUSH 0x0
1319#define SOFT_RST 0x40 /* Soft Reset */ 1192#define SOFT_RST 0x40 /* Soft Reset */
1320#define nSOFT_RST 0x0
1321#define DEV_RST 0x80 /* Device Reset */ 1193#define DEV_RST 0x80 /* Device Reset */
1322#define nDEV_RST 0x0
1323#define TFRCNT_RST 0x100 /* Trans Count Reset */ 1194#define TFRCNT_RST 0x100 /* Trans Count Reset */
1324#define nTFRCNT_RST 0x0
1325#define END_ON_TERM 0x200 /* End/Terminate Select */ 1195#define END_ON_TERM 0x200 /* End/Terminate Select */
1326#define nEND_ON_TERM 0x0
1327#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 1196#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1328#define nPIO_USE_DMA 0x0
1329#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 1197#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1330 1198
1331/* Bit masks for ATAPI_STATUS */ 1199/* Bit masks for ATAPI_STATUS */
1332 1200
1333#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 1201#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1334#define nPIO_XFER_ON 0x0
1335#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 1202#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1336#define nMULTI_XFER_ON 0x0
1337#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 1203#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1338#define nULTRA_XFER_ON 0x0
1339#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 1204#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1340 1205
1341/* Bit masks for ATAPI_DEV_ADDR */ 1206/* Bit masks for ATAPI_DEV_ADDR */
@@ -1345,66 +1210,39 @@
1345/* Bit masks for ATAPI_INT_MASK */ 1210/* Bit masks for ATAPI_INT_MASK */
1346 1211
1347#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 1212#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1348#define nATAPI_DEV_INT_MASK 0x0
1349#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 1213#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1350#define nPIO_DONE_MASK 0x0
1351#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 1214#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1352#define nMULTI_DONE_MASK 0x0
1353#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 1215#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1354#define nUDMAIN_DONE_MASK 0x0
1355#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 1216#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1356#define nUDMAOUT_DONE_MASK 0x0
1357#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 1217#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1358#define nHOST_TERM_XFER_MASK 0x0
1359#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 1218#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1360#define nMULTI_TERM_MASK 0x0
1361#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 1219#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1362#define nUDMAIN_TERM_MASK 0x0
1363#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 1220#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1364#define nUDMAOUT_TERM_MASK 0x0
1365 1221
1366/* Bit masks for ATAPI_INT_STATUS */ 1222/* Bit masks for ATAPI_INT_STATUS */
1367 1223
1368#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 1224#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1369#define nATAPI_DEV_INT 0x0
1370#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 1225#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1371#define nPIO_DONE_INT 0x0
1372#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 1226#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1373#define nMULTI_DONE_INT 0x0
1374#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 1227#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1375#define nUDMAIN_DONE_INT 0x0
1376#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 1228#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1377#define nUDMAOUT_DONE_INT 0x0
1378#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 1229#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1379#define nHOST_TERM_XFER_INT 0x0
1380#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 1230#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1381#define nMULTI_TERM_INT 0x0
1382#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 1231#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1383#define nUDMAIN_TERM_INT 0x0
1384#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 1232#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1385#define nUDMAOUT_TERM_INT 0x0
1386 1233
1387/* Bit masks for ATAPI_LINE_STATUS */ 1234/* Bit masks for ATAPI_LINE_STATUS */
1388 1235
1389#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 1236#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1390#define nATAPI_INTR 0x0
1391#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 1237#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1392#define nATAPI_DASP 0x0
1393#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 1238#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1394#define nATAPI_CS0N 0x0
1395#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 1239#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1396#define nATAPI_CS1N 0x0
1397#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 1240#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1398#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 1241#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1399#define nATAPI_DMAREQ 0x0
1400#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 1242#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1401#define nATAPI_DMAACKN 0x0
1402#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 1243#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1403#define nATAPI_DIOWN 0x0
1404#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 1244#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1405#define nATAPI_DIORN 0x0
1406#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 1245#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1407#define nATAPI_IORDY 0x0
1408 1246
1409/* Bit masks for ATAPI_SM_STATE */ 1247/* Bit masks for ATAPI_SM_STATE */
1410 1248
@@ -1416,7 +1254,6 @@
1416/* Bit masks for ATAPI_TERMINATE */ 1254/* Bit masks for ATAPI_TERMINATE */
1417 1255
1418#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 1256#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1419#define nATAPI_HOST_TERM 0x0
1420 1257
1421/* Bit masks for ATAPI_REG_TIM_0 */ 1258/* Bit masks for ATAPI_REG_TIM_0 */
1422 1259
@@ -1471,41 +1308,26 @@
1471/* Bit masks for TIMER_ENABLE1 */ 1308/* Bit masks for TIMER_ENABLE1 */
1472 1309
1473#define TIMEN8 0x1 /* Timer 8 Enable */ 1310#define TIMEN8 0x1 /* Timer 8 Enable */
1474#define nTIMEN8 0x0
1475#define TIMEN9 0x2 /* Timer 9 Enable */ 1311#define TIMEN9 0x2 /* Timer 9 Enable */
1476#define nTIMEN9 0x0
1477#define TIMEN10 0x4 /* Timer 10 Enable */ 1312#define TIMEN10 0x4 /* Timer 10 Enable */
1478#define nTIMEN10 0x0
1479 1313
1480/* Bit masks for TIMER_DISABLE1 */ 1314/* Bit masks for TIMER_DISABLE1 */
1481 1315
1482#define TIMDIS8 0x1 /* Timer 8 Disable */ 1316#define TIMDIS8 0x1 /* Timer 8 Disable */
1483#define nTIMDIS8 0x0
1484#define TIMDIS9 0x2 /* Timer 9 Disable */ 1317#define TIMDIS9 0x2 /* Timer 9 Disable */
1485#define nTIMDIS9 0x0
1486#define TIMDIS10 0x4 /* Timer 10 Disable */ 1318#define TIMDIS10 0x4 /* Timer 10 Disable */
1487#define nTIMDIS10 0x0
1488 1319
1489/* Bit masks for TIMER_STATUS1 */ 1320/* Bit masks for TIMER_STATUS1 */
1490 1321
1491#define TIMIL8 0x1 /* Timer 8 Interrupt */ 1322#define TIMIL8 0x1 /* Timer 8 Interrupt */
1492#define nTIMIL8 0x0
1493#define TIMIL9 0x2 /* Timer 9 Interrupt */ 1323#define TIMIL9 0x2 /* Timer 9 Interrupt */
1494#define nTIMIL9 0x0
1495#define TIMIL10 0x4 /* Timer 10 Interrupt */ 1324#define TIMIL10 0x4 /* Timer 10 Interrupt */
1496#define nTIMIL10 0x0
1497#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 1325#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1498#define nTOVF_ERR8 0x0
1499#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 1326#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1500#define nTOVF_ERR9 0x0
1501#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 1327#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1502#define nTOVF_ERR10 0x0
1503#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 1328#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1504#define nTRUN8 0x0
1505#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 1329#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1506#define nTRUN9 0x0
1507#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 1330#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1508#define nTRUN10 0x0
1509 1331
1510/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 1332/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1511 1333
@@ -1516,131 +1338,77 @@
1516/* Bit masks for USB_POWER */ 1338/* Bit masks for USB_POWER */
1517 1339
1518#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 1340#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1519#define nENABLE_SUSPENDM 0x0
1520#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 1341#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1521#define nSUSPEND_MODE 0x0
1522#define RESUME_MODE 0x4 /* DMA Mode */ 1342#define RESUME_MODE 0x4 /* DMA Mode */
1523#define nRESUME_MODE 0x0
1524#define RESET 0x8 /* Reset indicator */ 1343#define RESET 0x8 /* Reset indicator */
1525#define nRESET 0x0
1526#define HS_MODE 0x10 /* High Speed mode indicator */ 1344#define HS_MODE 0x10 /* High Speed mode indicator */
1527#define nHS_MODE 0x0
1528#define HS_ENABLE 0x20 /* high Speed Enable */ 1345#define HS_ENABLE 0x20 /* high Speed Enable */
1529#define nHS_ENABLE 0x0
1530#define SOFT_CONN 0x40 /* Soft connect */ 1346#define SOFT_CONN 0x40 /* Soft connect */
1531#define nSOFT_CONN 0x0
1532#define ISO_UPDATE 0x80 /* Isochronous update */ 1347#define ISO_UPDATE 0x80 /* Isochronous update */
1533#define nISO_UPDATE 0x0
1534 1348
1535/* Bit masks for USB_INTRTX */ 1349/* Bit masks for USB_INTRTX */
1536 1350
1537#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 1351#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1538#define nEP0_TX 0x0
1539#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 1352#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1540#define nEP1_TX 0x0
1541#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 1353#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1542#define nEP2_TX 0x0
1543#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 1354#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1544#define nEP3_TX 0x0
1545#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 1355#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1546#define nEP4_TX 0x0
1547#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 1356#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1548#define nEP5_TX 0x0
1549#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 1357#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1550#define nEP6_TX 0x0
1551#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 1358#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1552#define nEP7_TX 0x0
1553 1359
1554/* Bit masks for USB_INTRRX */ 1360/* Bit masks for USB_INTRRX */
1555 1361
1556#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 1362#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1557#define nEP1_RX 0x0
1558#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 1363#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1559#define nEP2_RX 0x0
1560#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 1364#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1561#define nEP3_RX 0x0
1562#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 1365#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1563#define nEP4_RX 0x0
1564#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 1366#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1565#define nEP5_RX 0x0
1566#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 1367#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1567#define nEP6_RX 0x0
1568#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 1368#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1569#define nEP7_RX 0x0
1570 1369
1571/* Bit masks for USB_INTRTXE */ 1370/* Bit masks for USB_INTRTXE */
1572 1371
1573#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 1372#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1574#define nEP0_TX_E 0x0
1575#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 1373#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1576#define nEP1_TX_E 0x0
1577#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 1374#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1578#define nEP2_TX_E 0x0
1579#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 1375#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1580#define nEP3_TX_E 0x0
1581#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 1376#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1582#define nEP4_TX_E 0x0
1583#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 1377#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1584#define nEP5_TX_E 0x0
1585#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 1378#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1586#define nEP6_TX_E 0x0
1587#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 1379#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1588#define nEP7_TX_E 0x0
1589 1380
1590/* Bit masks for USB_INTRRXE */ 1381/* Bit masks for USB_INTRRXE */
1591 1382
1592#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 1383#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1593#define nEP1_RX_E 0x0
1594#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 1384#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1595#define nEP2_RX_E 0x0
1596#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 1385#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1597#define nEP3_RX_E 0x0
1598#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 1386#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1599#define nEP4_RX_E 0x0
1600#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 1387#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1601#define nEP5_RX_E 0x0
1602#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 1388#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1603#define nEP6_RX_E 0x0
1604#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 1389#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1605#define nEP7_RX_E 0x0
1606 1390
1607/* Bit masks for USB_INTRUSB */ 1391/* Bit masks for USB_INTRUSB */
1608 1392
1609#define SUSPEND_B 0x1 /* Suspend indicator */ 1393#define SUSPEND_B 0x1 /* Suspend indicator */
1610#define nSUSPEND_B 0x0
1611#define RESUME_B 0x2 /* Resume indicator */ 1394#define RESUME_B 0x2 /* Resume indicator */
1612#define nRESUME_B 0x0
1613#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 1395#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1614#define nRESET_OR_BABLE_B 0x0
1615#define SOF_B 0x8 /* Start of frame */ 1396#define SOF_B 0x8 /* Start of frame */
1616#define nSOF_B 0x0
1617#define CONN_B 0x10 /* Connection indicator */ 1397#define CONN_B 0x10 /* Connection indicator */
1618#define nCONN_B 0x0
1619#define DISCON_B 0x20 /* Disconnect indicator */ 1398#define DISCON_B 0x20 /* Disconnect indicator */
1620#define nDISCON_B 0x0
1621#define SESSION_REQ_B 0x40 /* Session Request */ 1399#define SESSION_REQ_B 0x40 /* Session Request */
1622#define nSESSION_REQ_B 0x0
1623#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 1400#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1624#define nVBUS_ERROR_B 0x0
1625 1401
1626/* Bit masks for USB_INTRUSBE */ 1402/* Bit masks for USB_INTRUSBE */
1627 1403
1628#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 1404#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1629#define nSUSPEND_BE 0x0
1630#define RESUME_BE 0x2 /* Resume indicator int enable */ 1405#define RESUME_BE 0x2 /* Resume indicator int enable */
1631#define nRESUME_BE 0x0
1632#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 1406#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1633#define nRESET_OR_BABLE_BE 0x0
1634#define SOF_BE 0x8 /* Start of frame int enable */ 1407#define SOF_BE 0x8 /* Start of frame int enable */
1635#define nSOF_BE 0x0
1636#define CONN_BE 0x10 /* Connection indicator int enable */ 1408#define CONN_BE 0x10 /* Connection indicator int enable */
1637#define nCONN_BE 0x0
1638#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 1409#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1639#define nDISCON_BE 0x0
1640#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 1410#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1641#define nSESSION_REQ_BE 0x0
1642#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 1411#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1643#define nVBUS_ERROR_BE 0x0
1644 1412
1645/* Bit masks for USB_FRAME */ 1413/* Bit masks for USB_FRAME */
1646 1414
@@ -1653,117 +1421,67 @@
1653/* Bit masks for USB_GLOBAL_CTL */ 1421/* Bit masks for USB_GLOBAL_CTL */
1654 1422
1655#define GLOBAL_ENA 0x1 /* enables USB module */ 1423#define GLOBAL_ENA 0x1 /* enables USB module */
1656#define nGLOBAL_ENA 0x0
1657#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 1424#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1658#define nEP1_TX_ENA 0x0
1659#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 1425#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1660#define nEP2_TX_ENA 0x0
1661#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 1426#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1662#define nEP3_TX_ENA 0x0
1663#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 1427#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1664#define nEP4_TX_ENA 0x0
1665#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 1428#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1666#define nEP5_TX_ENA 0x0
1667#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 1429#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1668#define nEP6_TX_ENA 0x0
1669#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 1430#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1670#define nEP7_TX_ENA 0x0
1671#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 1431#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1672#define nEP1_RX_ENA 0x0
1673#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 1432#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1674#define nEP2_RX_ENA 0x0
1675#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 1433#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1676#define nEP3_RX_ENA 0x0
1677#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 1434#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1678#define nEP4_RX_ENA 0x0
1679#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 1435#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1680#define nEP5_RX_ENA 0x0
1681#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 1436#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1682#define nEP6_RX_ENA 0x0
1683#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 1437#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1684#define nEP7_RX_ENA 0x0
1685 1438
1686/* Bit masks for USB_OTG_DEV_CTL */ 1439/* Bit masks for USB_OTG_DEV_CTL */
1687 1440
1688#define SESSION 0x1 /* session indicator */ 1441#define SESSION 0x1 /* session indicator */
1689#define nSESSION 0x0
1690#define HOST_REQ 0x2 /* Host negotiation request */ 1442#define HOST_REQ 0x2 /* Host negotiation request */
1691#define nHOST_REQ 0x0
1692#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 1443#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1693#define nHOST_MODE 0x0
1694#define VBUS0 0x8 /* Vbus level indicator[0] */ 1444#define VBUS0 0x8 /* Vbus level indicator[0] */
1695#define nVBUS0 0x0
1696#define VBUS1 0x10 /* Vbus level indicator[1] */ 1445#define VBUS1 0x10 /* Vbus level indicator[1] */
1697#define nVBUS1 0x0
1698#define LSDEV 0x20 /* Low-speed indicator */ 1446#define LSDEV 0x20 /* Low-speed indicator */
1699#define nLSDEV 0x0
1700#define FSDEV 0x40 /* Full or High-speed indicator */ 1447#define FSDEV 0x40 /* Full or High-speed indicator */
1701#define nFSDEV 0x0
1702#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 1448#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1703#define nB_DEVICE 0x0
1704 1449
1705/* Bit masks for USB_OTG_VBUS_IRQ */ 1450/* Bit masks for USB_OTG_VBUS_IRQ */
1706 1451
1707#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 1452#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1708#define nDRIVE_VBUS_ON 0x0
1709#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 1453#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1710#define nDRIVE_VBUS_OFF 0x0
1711#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 1454#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1712#define nCHRG_VBUS_START 0x0
1713#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 1455#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1714#define nCHRG_VBUS_END 0x0
1715#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 1456#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1716#define nDISCHRG_VBUS_START 0x0
1717#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 1457#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1718#define nDISCHRG_VBUS_END 0x0
1719 1458
1720/* Bit masks for USB_OTG_VBUS_MASK */ 1459/* Bit masks for USB_OTG_VBUS_MASK */
1721 1460
1722#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 1461#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1723#define nDRIVE_VBUS_ON_ENA 0x0
1724#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 1462#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1725#define nDRIVE_VBUS_OFF_ENA 0x0
1726#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 1463#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1727#define nCHRG_VBUS_START_ENA 0x0
1728#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 1464#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1729#define nCHRG_VBUS_END_ENA 0x0
1730#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 1465#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1731#define nDISCHRG_VBUS_START_ENA 0x0
1732#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 1466#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1733#define nDISCHRG_VBUS_END_ENA 0x0
1734 1467
1735/* Bit masks for USB_CSR0 */ 1468/* Bit masks for USB_CSR0 */
1736 1469
1737#define RXPKTRDY 0x1 /* data packet receive indicator */ 1470#define RXPKTRDY 0x1 /* data packet receive indicator */
1738#define nRXPKTRDY 0x0
1739#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 1471#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1740#define nTXPKTRDY 0x0
1741#define STALL_SENT 0x4 /* STALL handshake sent */ 1472#define STALL_SENT 0x4 /* STALL handshake sent */
1742#define nSTALL_SENT 0x0
1743#define DATAEND 0x8 /* Data end indicator */ 1473#define DATAEND 0x8 /* Data end indicator */
1744#define nDATAEND 0x0
1745#define SETUPEND 0x10 /* Setup end */ 1474#define SETUPEND 0x10 /* Setup end */
1746#define nSETUPEND 0x0
1747#define SENDSTALL 0x20 /* Send STALL handshake */ 1475#define SENDSTALL 0x20 /* Send STALL handshake */
1748#define nSENDSTALL 0x0
1749#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 1476#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1750#define nSERVICED_RXPKTRDY 0x0
1751#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 1477#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1752#define nSERVICED_SETUPEND 0x0
1753#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 1478#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1754#define nFLUSHFIFO 0x0
1755#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 1479#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1756#define nSTALL_RECEIVED_H 0x0
1757#define SETUPPKT_H 0x8 /* send Setup token host mode */ 1480#define SETUPPKT_H 0x8 /* send Setup token host mode */
1758#define nSETUPPKT_H 0x0
1759#define ERROR_H 0x10 /* timeout error indicator host mode */ 1481#define ERROR_H 0x10 /* timeout error indicator host mode */
1760#define nERROR_H 0x0
1761#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 1482#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1762#define nREQPKT_H 0x0
1763#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 1483#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1764#define nSTATUSPKT_H 0x0
1765#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 1484#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1766#define nNAK_TIMEOUT_H 0x0
1767 1485
1768/* Bit masks for USB_COUNT0 */ 1486/* Bit masks for USB_COUNT0 */
1769 1487
@@ -1784,37 +1502,21 @@
1784/* Bit masks for USB_TXCSR */ 1502/* Bit masks for USB_TXCSR */
1785 1503
1786#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 1504#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1787#define nTXPKTRDY_T 0x0
1788#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 1505#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1789#define nFIFO_NOT_EMPTY_T 0x0
1790#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 1506#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1791#define nUNDERRUN_T 0x0
1792#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 1507#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1793#define nFLUSHFIFO_T 0x0
1794#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 1508#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1795#define nSTALL_SEND_T 0x0
1796#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 1509#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1797#define nSTALL_SENT_T 0x0
1798#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 1510#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1799#define nCLEAR_DATATOGGLE_T 0x0
1800#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 1511#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1801#define nINCOMPTX_T 0x0
1802#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 1512#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1803#define nDMAREQMODE_T 0x0
1804#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 1513#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1805#define nFORCE_DATATOGGLE_T 0x0
1806#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 1514#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1807#define nDMAREQ_ENA_T 0x0
1808#define ISO_T 0x4000 /* enable Isochronous transfers */ 1515#define ISO_T 0x4000 /* enable Isochronous transfers */
1809#define nISO_T 0x0
1810#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 1516#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1811#define nAUTOSET_T 0x0
1812#define ERROR_TH 0x4 /* error condition host mode */ 1517#define ERROR_TH 0x4 /* error condition host mode */
1813#define nERROR_TH 0x0
1814#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 1518#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1815#define nSTALL_RECEIVED_TH 0x0
1816#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 1519#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1817#define nNAK_TIMEOUT_TH 0x0
1818 1520
1819/* Bit masks for USB_TXCOUNT */ 1521/* Bit masks for USB_TXCOUNT */
1820 1522
@@ -1823,45 +1525,25 @@
1823/* Bit masks for USB_RXCSR */ 1525/* Bit masks for USB_RXCSR */
1824 1526
1825#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 1527#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1826#define nRXPKTRDY_R 0x0
1827#define FIFO_FULL_R 0x2 /* FIFO not empty */ 1528#define FIFO_FULL_R 0x2 /* FIFO not empty */
1828#define nFIFO_FULL_R 0x0
1829#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 1529#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1830#define nOVERRUN_R 0x0
1831#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 1530#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1832#define nDATAERROR_R 0x0
1833#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 1531#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1834#define nFLUSHFIFO_R 0x0
1835#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 1532#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1836#define nSTALL_SEND_R 0x0
1837#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 1533#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1838#define nSTALL_SENT_R 0x0
1839#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 1534#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1840#define nCLEAR_DATATOGGLE_R 0x0
1841#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 1535#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1842#define nINCOMPRX_R 0x0
1843#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 1536#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1844#define nDMAREQMODE_R 0x0
1845#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 1537#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1846#define nDISNYET_R 0x0
1847#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 1538#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1848#define nDMAREQ_ENA_R 0x0
1849#define ISO_R 0x4000 /* enable Isochronous transfers */ 1539#define ISO_R 0x4000 /* enable Isochronous transfers */
1850#define nISO_R 0x0
1851#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 1540#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1852#define nAUTOCLEAR_R 0x0
1853#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 1541#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1854#define nERROR_RH 0x0
1855#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 1542#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1856#define nREQPKT_RH 0x0
1857#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 1543#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1858#define nSTALL_RECEIVED_RH 0x0
1859#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 1544#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1860#define nINCOMPRX_RH 0x0
1861#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 1545#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1862#define nDMAREQMODE_RH 0x0
1863#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 1546#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1864#define nAUTOREQ_RH 0x0
1865 1547
1866/* Bit masks for USB_RXCOUNT */ 1548/* Bit masks for USB_RXCOUNT */
1867 1549
@@ -1888,35 +1570,22 @@
1888/* Bit masks for USB_DMA_INTERRUPT */ 1570/* Bit masks for USB_DMA_INTERRUPT */
1889 1571
1890#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 1572#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1891#define nDMA0_INT 0x0
1892#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 1573#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1893#define nDMA1_INT 0x0
1894#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 1574#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1895#define nDMA2_INT 0x0
1896#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 1575#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1897#define nDMA3_INT 0x0
1898#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 1576#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1899#define nDMA4_INT 0x0
1900#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 1577#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1901#define nDMA5_INT 0x0
1902#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 1578#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1903#define nDMA6_INT 0x0
1904#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 1579#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1905#define nDMA7_INT 0x0
1906 1580
1907/* Bit masks for USB_DMAxCONTROL */ 1581/* Bit masks for USB_DMAxCONTROL */
1908 1582
1909#define DMA_ENA 0x1 /* DMA enable */ 1583#define DMA_ENA 0x1 /* DMA enable */
1910#define nDMA_ENA 0x0
1911#define DIRECTION 0x2 /* direction of DMA transfer */ 1584#define DIRECTION 0x2 /* direction of DMA transfer */
1912#define nDIRECTION 0x0
1913#define MODE 0x4 /* DMA Bus error */ 1585#define MODE 0x4 /* DMA Bus error */
1914#define nMODE 0x0
1915#define INT_ENA 0x8 /* Interrupt enable */ 1586#define INT_ENA 0x8 /* Interrupt enable */
1916#define nINT_ENA 0x0
1917#define EPNUM 0xf0 /* EP number */ 1587#define EPNUM 0xf0 /* EP number */
1918#define BUSERROR 0x100 /* DMA Bus error */ 1588#define BUSERROR 0x100 /* DMA Bus error */
1919#define nBUSERROR 0x0
1920 1589
1921/* Bit masks for USB_DMAxADDRHIGH */ 1590/* Bit masks for USB_DMAxADDRHIGH */
1922 1591
@@ -1937,26 +1606,16 @@
1937/* Bit masks for HMDMAx_CONTROL */ 1606/* Bit masks for HMDMAx_CONTROL */
1938 1607
1939#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 1608#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1940#define nHMDMAEN 0x0
1941#define REP 0x2 /* Handshake MDMA Request Polarity */ 1609#define REP 0x2 /* Handshake MDMA Request Polarity */
1942#define nREP 0x0
1943#define UTE 0x8 /* Urgency Threshold Enable */ 1610#define UTE 0x8 /* Urgency Threshold Enable */
1944#define nUTE 0x0
1945#define OIE 0x10 /* Overflow Interrupt Enable */ 1611#define OIE 0x10 /* Overflow Interrupt Enable */
1946#define nOIE 0x0
1947#define BDIE 0x20 /* Block Done Interrupt Enable */ 1612#define BDIE 0x20 /* Block Done Interrupt Enable */
1948#define nBDIE 0x0
1949#define MBDI 0x40 /* Mask Block Done Interrupt */ 1613#define MBDI 0x40 /* Mask Block Done Interrupt */
1950#define nMBDI 0x0
1951#define DRQ 0x300 /* Handshake MDMA Request Type */ 1614#define DRQ 0x300 /* Handshake MDMA Request Type */
1952#define RBC 0x1000 /* Force Reload of BCOUNT */ 1615#define RBC 0x1000 /* Force Reload of BCOUNT */
1953#define nRBC 0x0
1954#define PS 0x2000 /* Pin Status */ 1616#define PS 0x2000 /* Pin Status */
1955#define nPS 0x0
1956#define OI 0x4000 /* Overflow Interrupt Generated */ 1617#define OI 0x4000 /* Overflow Interrupt Generated */
1957#define nOI 0x0
1958#define BDI 0x8000 /* Block Done Interrupt Generated */ 1618#define BDI 0x8000 /* Block Done Interrupt Generated */
1959#define nBDI 0x0
1960 1619
1961/* ******************************************* */ 1620/* ******************************************* */
1962/* MULTI BIT MACRO ENUMERATIONS */ 1621/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index b1cc1c073b41..c2f4734da48d 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -1070,21 +1070,13 @@
1070/* Bit masks for PIXC_CTL */ 1070/* Bit masks for PIXC_CTL */
1071 1071
1072#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 1072#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1073#define nPIXC_EN 0x0
1074#define OVR_A_EN 0x2 /* Overlay A Enable */ 1073#define OVR_A_EN 0x2 /* Overlay A Enable */
1075#define nOVR_A_EN 0x0
1076#define OVR_B_EN 0x4 /* Overlay B Enable */ 1074#define OVR_B_EN 0x4 /* Overlay B Enable */
1077#define nOVR_B_EN 0x0
1078#define IMG_FORM 0x8 /* Image Data Format */ 1075#define IMG_FORM 0x8 /* Image Data Format */
1079#define nIMG_FORM 0x0
1080#define OVR_FORM 0x10 /* Overlay Data Format */ 1076#define OVR_FORM 0x10 /* Overlay Data Format */
1081#define nOVR_FORM 0x0
1082#define OUT_FORM 0x20 /* Output Data Format */ 1077#define OUT_FORM 0x20 /* Output Data Format */
1083#define nOUT_FORM 0x0
1084#define UDS_MOD 0x40 /* Resampling Mode */ 1078#define UDS_MOD 0x40 /* Resampling Mode */
1085#define nUDS_MOD 0x0
1086#define TC_EN 0x80 /* Transparent Color Enable */ 1079#define TC_EN 0x80 /* Transparent Color Enable */
1087#define nTC_EN 0x0
1088#define IMG_STAT 0x300 /* Image FIFO Status */ 1080#define IMG_STAT 0x300 /* Image FIFO Status */
1089#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 1081#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1090#define WM_LVL 0x3000 /* FIFO Watermark Level */ 1082#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -1132,13 +1124,9 @@
1132/* Bit masks for PIXC_INTRSTAT */ 1124/* Bit masks for PIXC_INTRSTAT */
1133 1125
1134#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 1126#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1135#define nOVR_INT_EN 0x0
1136#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 1127#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1137#define nFRM_INT_EN 0x0
1138#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 1128#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1139#define nOVR_INT_STAT 0x0
1140#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 1129#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1141#define nFRM_INT_STAT 0x0
1142 1130
1143/* Bit masks for PIXC_RYCON */ 1131/* Bit masks for PIXC_RYCON */
1144 1132
@@ -1146,7 +1134,6 @@
1146#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 1134#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1147#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 1135#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1148#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 1136#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1149#define nRY_MULT4 0x0
1150 1137
1151/* Bit masks for PIXC_GUCON */ 1138/* Bit masks for PIXC_GUCON */
1152 1139
@@ -1154,7 +1141,6 @@
1154#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 1141#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1155#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 1142#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1156#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 1143#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1157#define nGU_MULT4 0x0
1158 1144
1159/* Bit masks for PIXC_BVCON */ 1145/* Bit masks for PIXC_BVCON */
1160 1146
@@ -1162,7 +1148,6 @@
1162#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 1148#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1163#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 1149#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1164#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 1150#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1165#define nBV_MULT4 0x0
1166 1151
1167/* Bit masks for PIXC_CCBIAS */ 1152/* Bit masks for PIXC_CCBIAS */
1168 1153
@@ -1179,48 +1164,28 @@
1179/* Bit masks for HOST_CONTROL */ 1164/* Bit masks for HOST_CONTROL */
1180 1165
1181#define HOST_EN 0x1 /* Host Enable */ 1166#define HOST_EN 0x1 /* Host Enable */
1182#define nHOST_EN 0x0
1183#define HOST_END 0x2 /* Host Endianess */ 1167#define HOST_END 0x2 /* Host Endianess */
1184#define nHOST_END 0x0
1185#define DATA_SIZE 0x4 /* Data Size */ 1168#define DATA_SIZE 0x4 /* Data Size */
1186#define nDATA_SIZE 0x0
1187#define HOST_RST 0x8 /* Host Reset */ 1169#define HOST_RST 0x8 /* Host Reset */
1188#define nHOST_RST 0x0
1189#define HRDY_OVR 0x20 /* Host Ready Override */ 1170#define HRDY_OVR 0x20 /* Host Ready Override */
1190#define nHRDY_OVR 0x0
1191#define INT_MODE 0x40 /* Interrupt Mode */ 1171#define INT_MODE 0x40 /* Interrupt Mode */
1192#define nINT_MODE 0x0
1193#define BT_EN 0x80 /* Bus Timeout Enable */ 1172#define BT_EN 0x80 /* Bus Timeout Enable */
1194#define nBT_EN 0x0
1195#define EHW 0x100 /* Enable Host Write */ 1173#define EHW 0x100 /* Enable Host Write */
1196#define nEHW 0x0
1197#define EHR 0x200 /* Enable Host Read */ 1174#define EHR 0x200 /* Enable Host Read */
1198#define nEHR 0x0
1199#define BDR 0x400 /* Burst DMA Requests */ 1175#define BDR 0x400 /* Burst DMA Requests */
1200#define nBDR 0x0
1201 1176
1202/* Bit masks for HOST_STATUS */ 1177/* Bit masks for HOST_STATUS */
1203 1178
1204#define READY 0x1 /* DMA Ready */ 1179#define READY 0x1 /* DMA Ready */
1205#define nREADY 0x0
1206#define FIFOFULL 0x2 /* FIFO Full */ 1180#define FIFOFULL 0x2 /* FIFO Full */
1207#define nFIFOFULL 0x0
1208#define FIFOEMPTY 0x4 /* FIFO Empty */ 1181#define FIFOEMPTY 0x4 /* FIFO Empty */
1209#define nFIFOEMPTY 0x0 1182#define DMA_COMPLETE 0x8 /* DMA Complete */
1210#define COMPLETE 0x8 /* DMA Complete */
1211#define nCOMPLETE 0x0
1212#define HSHK 0x10 /* Host Handshake */ 1183#define HSHK 0x10 /* Host Handshake */
1213#define nHSHK 0x0
1214#define TIMEOUT 0x20 /* Host Timeout */ 1184#define TIMEOUT 0x20 /* Host Timeout */
1215#define nTIMEOUT 0x0
1216#define HIRQ 0x40 /* Host Interrupt Request */ 1185#define HIRQ 0x40 /* Host Interrupt Request */
1217#define nHIRQ 0x0
1218#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 1186#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1219#define nALLOW_CNFG 0x0
1220#define DMA_DIR 0x100 /* DMA Direction */ 1187#define DMA_DIR 0x100 /* DMA Direction */
1221#define nDMA_DIR 0x0
1222#define BTE 0x200 /* Bus Timeout Enabled */ 1188#define BTE 0x200 /* Bus Timeout Enabled */
1223#define nBTE 0x0
1224 1189
1225/* Bit masks for HOST_TIMEOUT */ 1190/* Bit masks for HOST_TIMEOUT */
1226 1191
@@ -1229,71 +1194,41 @@
1229/* Bit masks for MXVR_CONFIG */ 1194/* Bit masks for MXVR_CONFIG */
1230 1195
1231#define MXVREN 0x1 /* MXVR Enable */ 1196#define MXVREN 0x1 /* MXVR Enable */
1232#define nMXVREN 0x0
1233#define MMSM 0x2 /* MXVR Master/Slave Mode Select */ 1197#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1234#define nMMSM 0x0
1235#define ACTIVE 0x4 /* Active Mode */ 1198#define ACTIVE 0x4 /* Active Mode */
1236#define nACTIVE 0x0
1237#define SDELAY 0x8 /* Synchronous Data Delay */ 1199#define SDELAY 0x8 /* Synchronous Data Delay */
1238#define nSDELAY 0x0
1239#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ 1200#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1240#define nNCMRXEN 0x0
1241#define RWRRXEN 0x20 /* Remote Write Receive Enable */ 1201#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1242#define nRWRRXEN 0x0
1243#define MTXEN 0x40 /* MXVR Transmit Data Enable */ 1202#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1244#define nMTXEN 0x0
1245#define MTXONB 0x80 /* MXVR Phy Transmitter On */ 1203#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1246#define nMTXONB 0x0
1247#define EPARITY 0x100 /* Even Parity Select */ 1204#define EPARITY 0x100 /* Even Parity Select */
1248#define nEPARITY 0x0
1249#define MSB 0x1e00 /* Master Synchronous Boundary */ 1205#define MSB 0x1e00 /* Master Synchronous Boundary */
1250#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ 1206#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1251#define nAPRXEN 0x0
1252#define WAKEUP 0x4000 /* Wake-Up */ 1207#define WAKEUP 0x4000 /* Wake-Up */
1253#define nWAKEUP 0x0
1254#define LMECH 0x8000 /* Lock Mechanism Select */ 1208#define LMECH 0x8000 /* Lock Mechanism Select */
1255#define nLMECH 0x0
1256 1209
1257/* Bit masks for MXVR_STATE_0 */ 1210/* Bit masks for MXVR_STATE_0 */
1258 1211
1259#define NACT 0x1 /* Network Activity */ 1212#define NACT 0x1 /* Network Activity */
1260#define nNACT 0x0
1261#define SBLOCK 0x2 /* Super Block Lock */ 1213#define SBLOCK 0x2 /* Super Block Lock */
1262#define nSBLOCK 0x0
1263#define FMPLLST 0xc /* Frequency Multiply PLL SM State */ 1214#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1264#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ 1215#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1265#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ 1216#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1266#define nAPBSY 0x0
1267#define APARB 0x200 /* Asynchronous Packet Arbitrating */ 1217#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1268#define nAPARB 0x0
1269#define APTX 0x400 /* Asynchronous Packet Transmitting */ 1218#define APTX 0x400 /* Asynchronous Packet Transmitting */
1270#define nAPTX 0x0
1271#define APRX 0x800 /* Receiving Asynchronous Packet */ 1219#define APRX 0x800 /* Receiving Asynchronous Packet */
1272#define nAPRX 0x0
1273#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ 1220#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1274#define nCMBSY 0x0
1275#define CMARB 0x2000 /* Control Message Arbitrating */ 1221#define CMARB 0x2000 /* Control Message Arbitrating */
1276#define nCMARB 0x0
1277#define CMTX 0x4000 /* Control Message Transmitting */ 1222#define CMTX 0x4000 /* Control Message Transmitting */
1278#define nCMTX 0x0
1279#define CMRX 0x8000 /* Receiving Control Message */ 1223#define CMRX 0x8000 /* Receiving Control Message */
1280#define nCMRX 0x0
1281#define MRXONB 0x10000 /* MRXONB Pin State */ 1224#define MRXONB 0x10000 /* MRXONB Pin State */
1282#define nMRXONB 0x0
1283#define RGSIP 0x20000 /* Remote Get Source In Progress */ 1225#define RGSIP 0x20000 /* Remote Get Source In Progress */
1284#define nRGSIP 0x0
1285#define DALIP 0x40000 /* Resource Deallocate In Progress */ 1226#define DALIP 0x40000 /* Resource Deallocate In Progress */
1286#define nDALIP 0x0
1287#define ALIP 0x80000 /* Resource Allocate In Progress */ 1227#define ALIP 0x80000 /* Resource Allocate In Progress */
1288#define nALIP 0x0
1289#define RRDIP 0x100000 /* Remote Read In Progress */ 1228#define RRDIP 0x100000 /* Remote Read In Progress */
1290#define nRRDIP 0x0
1291#define RWRIP 0x200000 /* Remote Write In Progress */ 1229#define RWRIP 0x200000 /* Remote Write In Progress */
1292#define nRWRIP 0x0
1293#define FLOCK 0x400000 /* Frame Lock */ 1230#define FLOCK 0x400000 /* Frame Lock */
1294#define nFLOCK 0x0
1295#define BLOCK 0x800000 /* Block Lock */ 1231#define BLOCK 0x800000 /* Block Lock */
1296#define nBLOCK 0x0
1297#define RSB 0xf000000 /* Received Synchronous Boundary */ 1232#define RSB 0xf000000 /* Received Synchronous Boundary */
1298#define DERRNUM 0xf0000000 /* DMA Error Channel Number */ 1233#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1299 1234
@@ -1302,535 +1237,343 @@
1302#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ 1237#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1303#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ 1238#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1304#define APCONT 0x100 /* Asynchronous Packet Continuation */ 1239#define APCONT 0x100 /* Asynchronous Packet Continuation */
1305#define nAPCONT 0x0
1306#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ 1240#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1307#define DMAACTIVE0 0x10000 /* DMA0 Active */ 1241#define DMAACTIVE0 0x10000 /* DMA0 Active */
1308#define nDMAACTIVE0 0x0
1309#define DMAACTIVE1 0x20000 /* DMA1 Active */ 1242#define DMAACTIVE1 0x20000 /* DMA1 Active */
1310#define nDMAACTIVE1 0x0
1311#define DMAACTIVE2 0x40000 /* DMA2 Active */ 1243#define DMAACTIVE2 0x40000 /* DMA2 Active */
1312#define nDMAACTIVE2 0x0
1313#define DMAACTIVE3 0x80000 /* DMA3 Active */ 1244#define DMAACTIVE3 0x80000 /* DMA3 Active */
1314#define nDMAACTIVE3 0x0
1315#define DMAACTIVE4 0x100000 /* DMA4 Active */ 1245#define DMAACTIVE4 0x100000 /* DMA4 Active */
1316#define nDMAACTIVE4 0x0
1317#define DMAACTIVE5 0x200000 /* DMA5 Active */ 1246#define DMAACTIVE5 0x200000 /* DMA5 Active */
1318#define nDMAACTIVE5 0x0
1319#define DMAACTIVE6 0x400000 /* DMA6 Active */ 1247#define DMAACTIVE6 0x400000 /* DMA6 Active */
1320#define nDMAACTIVE6 0x0
1321#define DMAACTIVE7 0x800000 /* DMA7 Active */ 1248#define DMAACTIVE7 0x800000 /* DMA7 Active */
1322#define nDMAACTIVE7 0x0
1323#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ 1249#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1324#define nDMAPMEN0 0x0
1325#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ 1250#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1326#define nDMAPMEN1 0x0
1327#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ 1251#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1328#define nDMAPMEN2 0x0
1329#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ 1252#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1330#define nDMAPMEN3 0x0
1331#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ 1253#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1332#define nDMAPMEN4 0x0
1333#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ 1254#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1334#define nDMAPMEN5 0x0
1335#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ 1255#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1336#define nDMAPMEN6 0x0
1337#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ 1256#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1338#define nDMAPMEN7 0x0
1339 1257
1340/* Bit masks for MXVR_INT_STAT_0 */ 1258/* Bit masks for MXVR_INT_STAT_0 */
1341 1259
1342#define NI2A 0x1 /* Network Inactive to Active */ 1260#define NI2A 0x1 /* Network Inactive to Active */
1343#define nNI2A 0x0
1344#define NA2I 0x2 /* Network Active to Inactive */ 1261#define NA2I 0x2 /* Network Active to Inactive */
1345#define nNA2I 0x0
1346#define SBU2L 0x4 /* Super Block Unlock to Lock */ 1262#define SBU2L 0x4 /* Super Block Unlock to Lock */
1347#define nSBU2L 0x0
1348#define SBL2U 0x8 /* Super Block Lock to Unlock */ 1263#define SBL2U 0x8 /* Super Block Lock to Unlock */
1349#define nSBL2U 0x0
1350#define PRU 0x10 /* Position Register Updated */ 1264#define PRU 0x10 /* Position Register Updated */
1351#define nPRU 0x0
1352#define MPRU 0x20 /* Maximum Position Register Updated */ 1265#define MPRU 0x20 /* Maximum Position Register Updated */
1353#define nMPRU 0x0
1354#define DRU 0x40 /* Delay Register Updated */ 1266#define DRU 0x40 /* Delay Register Updated */
1355#define nDRU 0x0
1356#define MDRU 0x80 /* Maximum Delay Register Updated */ 1267#define MDRU 0x80 /* Maximum Delay Register Updated */
1357#define nMDRU 0x0
1358#define SBU 0x100 /* Synchronous Boundary Updated */ 1268#define SBU 0x100 /* Synchronous Boundary Updated */
1359#define nSBU 0x0
1360#define ATU 0x200 /* Allocation Table Updated */ 1269#define ATU 0x200 /* Allocation Table Updated */
1361#define nATU 0x0
1362#define FCZ0 0x400 /* Frame Counter 0 Zero */ 1270#define FCZ0 0x400 /* Frame Counter 0 Zero */
1363#define nFCZ0 0x0
1364#define FCZ1 0x800 /* Frame Counter 1 Zero */ 1271#define FCZ1 0x800 /* Frame Counter 1 Zero */
1365#define nFCZ1 0x0
1366#define PERR 0x1000 /* Parity Error */ 1272#define PERR 0x1000 /* Parity Error */
1367#define nPERR 0x0
1368#define MH2L 0x2000 /* MRXONB High to Low */ 1273#define MH2L 0x2000 /* MRXONB High to Low */
1369#define nMH2L 0x0
1370#define ML2H 0x4000 /* MRXONB Low to High */ 1274#define ML2H 0x4000 /* MRXONB Low to High */
1371#define nML2H 0x0
1372#define WUP 0x8000 /* Wake-Up Preamble Received */ 1275#define WUP 0x8000 /* Wake-Up Preamble Received */
1373#define nWUP 0x0
1374#define FU2L 0x10000 /* Frame Unlock to Lock */ 1276#define FU2L 0x10000 /* Frame Unlock to Lock */
1375#define nFU2L 0x0
1376#define FL2U 0x20000 /* Frame Lock to Unlock */ 1277#define FL2U 0x20000 /* Frame Lock to Unlock */
1377#define nFL2U 0x0
1378#define BU2L 0x40000 /* Block Unlock to Lock */ 1278#define BU2L 0x40000 /* Block Unlock to Lock */
1379#define nBU2L 0x0
1380#define BL2U 0x80000 /* Block Lock to Unlock */ 1279#define BL2U 0x80000 /* Block Lock to Unlock */
1381#define nBL2U 0x0
1382#define OBERR 0x100000 /* DMA Out of Bounds Error */ 1280#define OBERR 0x100000 /* DMA Out of Bounds Error */
1383#define nOBERR 0x0
1384#define PFL 0x200000 /* PLL Frequency Locked */ 1281#define PFL 0x200000 /* PLL Frequency Locked */
1385#define nPFL 0x0
1386#define SCZ 0x400000 /* System Clock Counter Zero */ 1282#define SCZ 0x400000 /* System Clock Counter Zero */
1387#define nSCZ 0x0
1388#define FERR 0x800000 /* FIFO Error */ 1283#define FERR 0x800000 /* FIFO Error */
1389#define nFERR 0x0
1390#define CMR 0x1000000 /* Control Message Received */ 1284#define CMR 0x1000000 /* Control Message Received */
1391#define nCMR 0x0
1392#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ 1285#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1393#define nCMROF 0x0
1394#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ 1286#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1395#define nCMTS 0x0
1396#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ 1287#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1397#define nCMTC 0x0
1398#define RWRC 0x10000000 /* Remote Write Control Message Completed */ 1288#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1399#define nRWRC 0x0
1400#define BCZ 0x20000000 /* Block Counter Zero */ 1289#define BCZ 0x20000000 /* Block Counter Zero */
1401#define nBCZ 0x0
1402#define BMERR 0x40000000 /* Biphase Mark Coding Error */ 1290#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1403#define nBMERR 0x0
1404#define DERR 0x80000000 /* DMA Error */ 1291#define DERR 0x80000000 /* DMA Error */
1405#define nDERR 0x0
1406 1292
1407/* Bit masks for MXVR_INT_STAT_1 */ 1293/* Bit masks for MXVR_INT_STAT_1 */
1408 1294
1409#define HDONE0 0x1 /* DMA0 Half Done */ 1295#define HDONE0 0x1 /* DMA0 Half Done */
1410#define nHDONE0 0x0
1411#define DONE0 0x2 /* DMA0 Done */ 1296#define DONE0 0x2 /* DMA0 Done */
1412#define nDONE0 0x0
1413#define APR 0x4 /* Asynchronous Packet Received */ 1297#define APR 0x4 /* Asynchronous Packet Received */
1414#define nAPR 0x0
1415#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ 1298#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1416#define nAPROF 0x0
1417#define HDONE1 0x10 /* DMA1 Half Done */ 1299#define HDONE1 0x10 /* DMA1 Half Done */
1418#define nHDONE1 0x0
1419#define DONE1 0x20 /* DMA1 Done */ 1300#define DONE1 0x20 /* DMA1 Done */
1420#define nDONE1 0x0
1421#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ 1301#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1422#define nAPTS 0x0
1423#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ 1302#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1424#define nAPTC 0x0
1425#define HDONE2 0x100 /* DMA2 Half Done */ 1303#define HDONE2 0x100 /* DMA2 Half Done */
1426#define nHDONE2 0x0
1427#define DONE2 0x200 /* DMA2 Done */ 1304#define DONE2 0x200 /* DMA2 Done */
1428#define nDONE2 0x0
1429#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ 1305#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1430#define nAPRCE 0x0
1431#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ 1306#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1432#define nAPRPE 0x0
1433#define HDONE3 0x1000 /* DMA3 Half Done */ 1307#define HDONE3 0x1000 /* DMA3 Half Done */
1434#define nHDONE3 0x0
1435#define DONE3 0x2000 /* DMA3 Done */ 1308#define DONE3 0x2000 /* DMA3 Done */
1436#define nDONE3 0x0
1437#define HDONE4 0x10000 /* DMA4 Half Done */ 1309#define HDONE4 0x10000 /* DMA4 Half Done */
1438#define nHDONE4 0x0
1439#define DONE4 0x20000 /* DMA4 Done */ 1310#define DONE4 0x20000 /* DMA4 Done */
1440#define nDONE4 0x0
1441#define HDONE5 0x100000 /* DMA5 Half Done */ 1311#define HDONE5 0x100000 /* DMA5 Half Done */
1442#define nHDONE5 0x0
1443#define DONE5 0x200000 /* DMA5 Done */ 1312#define DONE5 0x200000 /* DMA5 Done */
1444#define nDONE5 0x0
1445#define HDONE6 0x1000000 /* DMA6 Half Done */ 1313#define HDONE6 0x1000000 /* DMA6 Half Done */
1446#define nHDONE6 0x0
1447#define DONE6 0x2000000 /* DMA6 Done */ 1314#define DONE6 0x2000000 /* DMA6 Done */
1448#define nDONE6 0x0
1449#define HDONE7 0x10000000 /* DMA7 Half Done */ 1315#define HDONE7 0x10000000 /* DMA7 Half Done */
1450#define nHDONE7 0x0
1451#define DONE7 0x20000000 /* DMA7 Done */ 1316#define DONE7 0x20000000 /* DMA7 Done */
1452#define nDONE7 0x0
1453 1317
1454/* Bit masks for MXVR_INT_EN_0 */ 1318/* Bit masks for MXVR_INT_EN_0 */
1455 1319
1456#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ 1320#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1457#define nNI2AEN 0x0
1458#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ 1321#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1459#define nNA2IEN 0x0
1460#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ 1322#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1461#define nSBU2LEN 0x0
1462#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ 1323#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1463#define nSBL2UEN 0x0
1464#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ 1324#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1465#define nPRUEN 0x0
1466#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ 1325#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1467#define nMPRUEN 0x0
1468#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ 1326#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1469#define nDRUEN 0x0
1470#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ 1327#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1471#define nMDRUEN 0x0
1472#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ 1328#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1473#define nSBUEN 0x0
1474#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ 1329#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1475#define nATUEN 0x0
1476#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ 1330#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1477#define nFCZ0EN 0x0
1478#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ 1331#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1479#define nFCZ1EN 0x0
1480#define PERREN 0x1000 /* Parity Error Interrupt Enable */ 1332#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1481#define nPERREN 0x0
1482#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ 1333#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1483#define nMH2LEN 0x0
1484#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ 1334#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1485#define nML2HEN 0x0
1486#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ 1335#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1487#define nWUPEN 0x0
1488#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ 1336#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1489#define nFU2LEN 0x0
1490#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ 1337#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1491#define nFL2UEN 0x0
1492#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ 1338#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1493#define nBU2LEN 0x0
1494#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ 1339#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1495#define nBL2UEN 0x0
1496#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ 1340#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1497#define nOBERREN 0x0
1498#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ 1341#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1499#define nPFLEN 0x0
1500#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ 1342#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1501#define nSCZEN 0x0
1502#define FERREN 0x800000 /* FIFO Error Interrupt Enable */ 1343#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1503#define nFERREN 0x0
1504#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ 1344#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1505#define nCMREN 0x0
1506#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ 1345#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1507#define nCMROFEN 0x0
1508#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ 1346#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1509#define nCMTSEN 0x0
1510#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ 1347#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1511#define nCMTCEN 0x0
1512#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ 1348#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1513#define nRWRCEN 0x0
1514#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ 1349#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1515#define nBCZEN 0x0
1516#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ 1350#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1517#define nBMERREN 0x0
1518#define DERREN 0x80000000 /* DMA Error Interrupt Enable */ 1351#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1519#define nDERREN 0x0
1520 1352
1521/* Bit masks for MXVR_INT_EN_1 */ 1353/* Bit masks for MXVR_INT_EN_1 */
1522 1354
1523#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ 1355#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1524#define nHDONEEN0 0x0
1525#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ 1356#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1526#define nDONEEN0 0x0
1527#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ 1357#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1528#define nAPREN 0x0
1529#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ 1358#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1530#define nAPROFEN 0x0
1531#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ 1359#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1532#define nHDONEEN1 0x0
1533#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ 1360#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1534#define nDONEEN1 0x0
1535#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ 1361#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1536#define nAPTSEN 0x0
1537#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ 1362#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1538#define nAPTCEN 0x0
1539#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ 1363#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1540#define nHDONEEN2 0x0
1541#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ 1364#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1542#define nDONEEN2 0x0
1543#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ 1365#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1544#define nAPRCEEN 0x0
1545#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ 1366#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1546#define nAPRPEEN 0x0
1547#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ 1367#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1548#define nHDONEEN3 0x0
1549#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ 1368#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1550#define nDONEEN3 0x0
1551#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ 1369#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1552#define nHDONEEN4 0x0
1553#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ 1370#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1554#define nDONEEN4 0x0
1555#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ 1371#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1556#define nHDONEEN5 0x0
1557#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ 1372#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1558#define nDONEEN5 0x0
1559#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ 1373#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1560#define nHDONEEN6 0x0
1561#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ 1374#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1562#define nDONEEN6 0x0
1563#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ 1375#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1564#define nHDONEEN7 0x0
1565#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ 1376#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1566#define nDONEEN7 0x0
1567 1377
1568/* Bit masks for MXVR_POSITION */ 1378/* Bit masks for MXVR_POSITION */
1569 1379
1570#define POSITION 0x3f /* Node Position */ 1380#define POSITION 0x3f /* Node Position */
1571#define PVALID 0x8000 /* Node Position Valid */ 1381#define PVALID 0x8000 /* Node Position Valid */
1572#define nPVALID 0x0
1573 1382
1574/* Bit masks for MXVR_MAX_POSITION */ 1383/* Bit masks for MXVR_MAX_POSITION */
1575 1384
1576#define MPOSITION 0x3f /* Maximum Node Position */ 1385#define MPOSITION 0x3f /* Maximum Node Position */
1577#define MPVALID 0x8000 /* Maximum Node Position Valid */ 1386#define MPVALID 0x8000 /* Maximum Node Position Valid */
1578#define nMPVALID 0x0
1579 1387
1580/* Bit masks for MXVR_DELAY */ 1388/* Bit masks for MXVR_DELAY */
1581 1389
1582#define DELAY 0x3f /* Node Frame Delay */ 1390#define DELAY 0x3f /* Node Frame Delay */
1583#define DVALID 0x8000 /* Node Frame Delay Valid */ 1391#define DVALID 0x8000 /* Node Frame Delay Valid */
1584#define nDVALID 0x0
1585 1392
1586/* Bit masks for MXVR_MAX_DELAY */ 1393/* Bit masks for MXVR_MAX_DELAY */
1587 1394
1588#define MDELAY 0x3f /* Maximum Node Frame Delay */ 1395#define MDELAY 0x3f /* Maximum Node Frame Delay */
1589#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ 1396#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1590#define nMDVALID 0x0
1591 1397
1592/* Bit masks for MXVR_LADDR */ 1398/* Bit masks for MXVR_LADDR */
1593 1399
1594#define LADDR 0xffff /* Logical Address */ 1400#define LADDR 0xffff /* Logical Address */
1595#define LVALID 0x80000000 /* Logical Address Valid */ 1401#define LVALID 0x80000000 /* Logical Address Valid */
1596#define nLVALID 0x0
1597 1402
1598/* Bit masks for MXVR_GADDR */ 1403/* Bit masks for MXVR_GADDR */
1599 1404
1600#define GADDRL 0xff /* Group Address Lower Byte */ 1405#define GADDRL 0xff /* Group Address Lower Byte */
1601#define GVALID 0x8000 /* Group Address Valid */ 1406#define GVALID 0x8000 /* Group Address Valid */
1602#define nGVALID 0x0
1603 1407
1604/* Bit masks for MXVR_AADDR */ 1408/* Bit masks for MXVR_AADDR */
1605 1409
1606#define AADDR 0xffff /* Alternate Address */ 1410#define AADDR 0xffff /* Alternate Address */
1607#define AVALID 0x80000000 /* Alternate Address Valid */ 1411#define AVALID 0x80000000 /* Alternate Address Valid */
1608#define nAVALID 0x0
1609 1412
1610/* Bit masks for MXVR_ALLOC_0 */ 1413/* Bit masks for MXVR_ALLOC_0 */
1611 1414
1612#define CL0 0x7f /* Channel 0 Connection Label */ 1415#define CL0 0x7f /* Channel 0 Connection Label */
1613#define CIU0 0x80 /* Channel 0 In Use */ 1416#define CIU0 0x80 /* Channel 0 In Use */
1614#define nCIU0 0x0
1615#define CL1 0x7f00 /* Channel 0 Connection Label */ 1417#define CL1 0x7f00 /* Channel 0 Connection Label */
1616#define CIU1 0x8000 /* Channel 0 In Use */ 1418#define CIU1 0x8000 /* Channel 0 In Use */
1617#define nCIU1 0x0
1618#define CL2 0x7f0000 /* Channel 0 Connection Label */ 1419#define CL2 0x7f0000 /* Channel 0 Connection Label */
1619#define CIU2 0x800000 /* Channel 0 In Use */ 1420#define CIU2 0x800000 /* Channel 0 In Use */
1620#define nCIU2 0x0
1621#define CL3 0x7f000000 /* Channel 0 Connection Label */ 1421#define CL3 0x7f000000 /* Channel 0 Connection Label */
1622#define CIU3 0x80000000 /* Channel 0 In Use */ 1422#define CIU3 0x80000000 /* Channel 0 In Use */
1623#define nCIU3 0x0
1624 1423
1625/* Bit masks for MXVR_ALLOC_1 */ 1424/* Bit masks for MXVR_ALLOC_1 */
1626 1425
1627#define CL4 0x7f /* Channel 4 Connection Label */ 1426#define CL4 0x7f /* Channel 4 Connection Label */
1628#define CIU4 0x80 /* Channel 4 In Use */ 1427#define CIU4 0x80 /* Channel 4 In Use */
1629#define nCIU4 0x0
1630#define CL5 0x7f00 /* Channel 5 Connection Label */ 1428#define CL5 0x7f00 /* Channel 5 Connection Label */
1631#define CIU5 0x8000 /* Channel 5 In Use */ 1429#define CIU5 0x8000 /* Channel 5 In Use */
1632#define nCIU5 0x0
1633#define CL6 0x7f0000 /* Channel 6 Connection Label */ 1430#define CL6 0x7f0000 /* Channel 6 Connection Label */
1634#define CIU6 0x800000 /* Channel 6 In Use */ 1431#define CIU6 0x800000 /* Channel 6 In Use */
1635#define nCIU6 0x0
1636#define CL7 0x7f000000 /* Channel 7 Connection Label */ 1432#define CL7 0x7f000000 /* Channel 7 Connection Label */
1637#define CIU7 0x80000000 /* Channel 7 In Use */ 1433#define CIU7 0x80000000 /* Channel 7 In Use */
1638#define nCIU7 0x0
1639 1434
1640/* Bit masks for MXVR_ALLOC_2 */ 1435/* Bit masks for MXVR_ALLOC_2 */
1641 1436
1642#define CL8 0x7f /* Channel 8 Connection Label */ 1437#define CL8 0x7f /* Channel 8 Connection Label */
1643#define CIU8 0x80 /* Channel 8 In Use */ 1438#define CIU8 0x80 /* Channel 8 In Use */
1644#define nCIU8 0x0
1645#define CL9 0x7f00 /* Channel 9 Connection Label */ 1439#define CL9 0x7f00 /* Channel 9 Connection Label */
1646#define CIU9 0x8000 /* Channel 9 In Use */ 1440#define CIU9 0x8000 /* Channel 9 In Use */
1647#define nCIU9 0x0
1648#define CL10 0x7f0000 /* Channel 10 Connection Label */ 1441#define CL10 0x7f0000 /* Channel 10 Connection Label */
1649#define CIU10 0x800000 /* Channel 10 In Use */ 1442#define CIU10 0x800000 /* Channel 10 In Use */
1650#define nCIU10 0x0
1651#define CL11 0x7f000000 /* Channel 11 Connection Label */ 1443#define CL11 0x7f000000 /* Channel 11 Connection Label */
1652#define CIU11 0x80000000 /* Channel 11 In Use */ 1444#define CIU11 0x80000000 /* Channel 11 In Use */
1653#define nCIU11 0x0
1654 1445
1655/* Bit masks for MXVR_ALLOC_3 */ 1446/* Bit masks for MXVR_ALLOC_3 */
1656 1447
1657#define CL12 0x7f /* Channel 12 Connection Label */ 1448#define CL12 0x7f /* Channel 12 Connection Label */
1658#define CIU12 0x80 /* Channel 12 In Use */ 1449#define CIU12 0x80 /* Channel 12 In Use */
1659#define nCIU12 0x0
1660#define CL13 0x7f00 /* Channel 13 Connection Label */ 1450#define CL13 0x7f00 /* Channel 13 Connection Label */
1661#define CIU13 0x8000 /* Channel 13 In Use */ 1451#define CIU13 0x8000 /* Channel 13 In Use */
1662#define nCIU13 0x0
1663#define CL14 0x7f0000 /* Channel 14 Connection Label */ 1452#define CL14 0x7f0000 /* Channel 14 Connection Label */
1664#define CIU14 0x800000 /* Channel 14 In Use */ 1453#define CIU14 0x800000 /* Channel 14 In Use */
1665#define nCIU14 0x0
1666#define CL15 0x7f000000 /* Channel 15 Connection Label */ 1454#define CL15 0x7f000000 /* Channel 15 Connection Label */
1667#define CIU15 0x80000000 /* Channel 15 In Use */ 1455#define CIU15 0x80000000 /* Channel 15 In Use */
1668#define nCIU15 0x0
1669 1456
1670/* Bit masks for MXVR_ALLOC_4 */ 1457/* Bit masks for MXVR_ALLOC_4 */
1671 1458
1672#define CL16 0x7f /* Channel 16 Connection Label */ 1459#define CL16 0x7f /* Channel 16 Connection Label */
1673#define CIU16 0x80 /* Channel 16 In Use */ 1460#define CIU16 0x80 /* Channel 16 In Use */
1674#define nCIU16 0x0
1675#define CL17 0x7f00 /* Channel 17 Connection Label */ 1461#define CL17 0x7f00 /* Channel 17 Connection Label */
1676#define CIU17 0x8000 /* Channel 17 In Use */ 1462#define CIU17 0x8000 /* Channel 17 In Use */
1677#define nCIU17 0x0
1678#define CL18 0x7f0000 /* Channel 18 Connection Label */ 1463#define CL18 0x7f0000 /* Channel 18 Connection Label */
1679#define CIU18 0x800000 /* Channel 18 In Use */ 1464#define CIU18 0x800000 /* Channel 18 In Use */
1680#define nCIU18 0x0
1681#define CL19 0x7f000000 /* Channel 19 Connection Label */ 1465#define CL19 0x7f000000 /* Channel 19 Connection Label */
1682#define CIU19 0x80000000 /* Channel 19 In Use */ 1466#define CIU19 0x80000000 /* Channel 19 In Use */
1683#define nCIU19 0x0
1684 1467
1685/* Bit masks for MXVR_ALLOC_5 */ 1468/* Bit masks for MXVR_ALLOC_5 */
1686 1469
1687#define CL20 0x7f /* Channel 20 Connection Label */ 1470#define CL20 0x7f /* Channel 20 Connection Label */
1688#define CIU20 0x80 /* Channel 20 In Use */ 1471#define CIU20 0x80 /* Channel 20 In Use */
1689#define nCIU20 0x0
1690#define CL21 0x7f00 /* Channel 21 Connection Label */ 1472#define CL21 0x7f00 /* Channel 21 Connection Label */
1691#define CIU21 0x8000 /* Channel 21 In Use */ 1473#define CIU21 0x8000 /* Channel 21 In Use */
1692#define nCIU21 0x0
1693#define CL22 0x7f0000 /* Channel 22 Connection Label */ 1474#define CL22 0x7f0000 /* Channel 22 Connection Label */
1694#define CIU22 0x800000 /* Channel 22 In Use */ 1475#define CIU22 0x800000 /* Channel 22 In Use */
1695#define nCIU22 0x0
1696#define CL23 0x7f000000 /* Channel 23 Connection Label */ 1476#define CL23 0x7f000000 /* Channel 23 Connection Label */
1697#define CIU23 0x80000000 /* Channel 23 In Use */ 1477#define CIU23 0x80000000 /* Channel 23 In Use */
1698#define nCIU23 0x0
1699 1478
1700/* Bit masks for MXVR_ALLOC_6 */ 1479/* Bit masks for MXVR_ALLOC_6 */
1701 1480
1702#define CL24 0x7f /* Channel 24 Connection Label */ 1481#define CL24 0x7f /* Channel 24 Connection Label */
1703#define CIU24 0x80 /* Channel 24 In Use */ 1482#define CIU24 0x80 /* Channel 24 In Use */
1704#define nCIU24 0x0
1705#define CL25 0x7f00 /* Channel 25 Connection Label */ 1483#define CL25 0x7f00 /* Channel 25 Connection Label */
1706#define CIU25 0x8000 /* Channel 25 In Use */ 1484#define CIU25 0x8000 /* Channel 25 In Use */
1707#define nCIU25 0x0
1708#define CL26 0x7f0000 /* Channel 26 Connection Label */ 1485#define CL26 0x7f0000 /* Channel 26 Connection Label */
1709#define CIU26 0x800000 /* Channel 26 In Use */ 1486#define CIU26 0x800000 /* Channel 26 In Use */
1710#define nCIU26 0x0
1711#define CL27 0x7f000000 /* Channel 27 Connection Label */ 1487#define CL27 0x7f000000 /* Channel 27 Connection Label */
1712#define CIU27 0x80000000 /* Channel 27 In Use */ 1488#define CIU27 0x80000000 /* Channel 27 In Use */
1713#define nCIU27 0x0
1714 1489
1715/* Bit masks for MXVR_ALLOC_7 */ 1490/* Bit masks for MXVR_ALLOC_7 */
1716 1491
1717#define CL28 0x7f /* Channel 28 Connection Label */ 1492#define CL28 0x7f /* Channel 28 Connection Label */
1718#define CIU28 0x80 /* Channel 28 In Use */ 1493#define CIU28 0x80 /* Channel 28 In Use */
1719#define nCIU28 0x0
1720#define CL29 0x7f00 /* Channel 29 Connection Label */ 1494#define CL29 0x7f00 /* Channel 29 Connection Label */
1721#define CIU29 0x8000 /* Channel 29 In Use */ 1495#define CIU29 0x8000 /* Channel 29 In Use */
1722#define nCIU29 0x0
1723#define CL30 0x7f0000 /* Channel 30 Connection Label */ 1496#define CL30 0x7f0000 /* Channel 30 Connection Label */
1724#define CIU30 0x800000 /* Channel 30 In Use */ 1497#define CIU30 0x800000 /* Channel 30 In Use */
1725#define nCIU30 0x0
1726#define CL31 0x7f000000 /* Channel 31 Connection Label */ 1498#define CL31 0x7f000000 /* Channel 31 Connection Label */
1727#define CIU31 0x80000000 /* Channel 31 In Use */ 1499#define CIU31 0x80000000 /* Channel 31 In Use */
1728#define nCIU31 0x0
1729 1500
1730/* Bit masks for MXVR_ALLOC_8 */ 1501/* Bit masks for MXVR_ALLOC_8 */
1731 1502
1732#define CL32 0x7f /* Channel 32 Connection Label */ 1503#define CL32 0x7f /* Channel 32 Connection Label */
1733#define CIU32 0x80 /* Channel 32 In Use */ 1504#define CIU32 0x80 /* Channel 32 In Use */
1734#define nCIU32 0x0
1735#define CL33 0x7f00 /* Channel 33 Connection Label */ 1505#define CL33 0x7f00 /* Channel 33 Connection Label */
1736#define CIU33 0x8000 /* Channel 33 In Use */ 1506#define CIU33 0x8000 /* Channel 33 In Use */
1737#define nCIU33 0x0
1738#define CL34 0x7f0000 /* Channel 34 Connection Label */ 1507#define CL34 0x7f0000 /* Channel 34 Connection Label */
1739#define CIU34 0x800000 /* Channel 34 In Use */ 1508#define CIU34 0x800000 /* Channel 34 In Use */
1740#define nCIU34 0x0
1741#define CL35 0x7f000000 /* Channel 35 Connection Label */ 1509#define CL35 0x7f000000 /* Channel 35 Connection Label */
1742#define CIU35 0x80000000 /* Channel 35 In Use */ 1510#define CIU35 0x80000000 /* Channel 35 In Use */
1743#define nCIU35 0x0
1744 1511
1745/* Bit masks for MXVR_ALLOC_9 */ 1512/* Bit masks for MXVR_ALLOC_9 */
1746 1513
1747#define CL36 0x7f /* Channel 36 Connection Label */ 1514#define CL36 0x7f /* Channel 36 Connection Label */
1748#define CIU36 0x80 /* Channel 36 In Use */ 1515#define CIU36 0x80 /* Channel 36 In Use */
1749#define nCIU36 0x0
1750#define CL37 0x7f00 /* Channel 37 Connection Label */ 1516#define CL37 0x7f00 /* Channel 37 Connection Label */
1751#define CIU37 0x8000 /* Channel 37 In Use */ 1517#define CIU37 0x8000 /* Channel 37 In Use */
1752#define nCIU37 0x0
1753#define CL38 0x7f0000 /* Channel 38 Connection Label */ 1518#define CL38 0x7f0000 /* Channel 38 Connection Label */
1754#define CIU38 0x800000 /* Channel 38 In Use */ 1519#define CIU38 0x800000 /* Channel 38 In Use */
1755#define nCIU38 0x0
1756#define CL39 0x7f000000 /* Channel 39 Connection Label */ 1520#define CL39 0x7f000000 /* Channel 39 Connection Label */
1757#define CIU39 0x80000000 /* Channel 39 In Use */ 1521#define CIU39 0x80000000 /* Channel 39 In Use */
1758#define nCIU39 0x0
1759 1522
1760/* Bit masks for MXVR_ALLOC_10 */ 1523/* Bit masks for MXVR_ALLOC_10 */
1761 1524
1762#define CL40 0x7f /* Channel 40 Connection Label */ 1525#define CL40 0x7f /* Channel 40 Connection Label */
1763#define CIU40 0x80 /* Channel 40 In Use */ 1526#define CIU40 0x80 /* Channel 40 In Use */
1764#define nCIU40 0x0
1765#define CL41 0x7f00 /* Channel 41 Connection Label */ 1527#define CL41 0x7f00 /* Channel 41 Connection Label */
1766#define CIU41 0x8000 /* Channel 41 In Use */ 1528#define CIU41 0x8000 /* Channel 41 In Use */
1767#define nCIU41 0x0
1768#define CL42 0x7f0000 /* Channel 42 Connection Label */ 1529#define CL42 0x7f0000 /* Channel 42 Connection Label */
1769#define CIU42 0x800000 /* Channel 42 In Use */ 1530#define CIU42 0x800000 /* Channel 42 In Use */
1770#define nCIU42 0x0
1771#define CL43 0x7f000000 /* Channel 43 Connection Label */ 1531#define CL43 0x7f000000 /* Channel 43 Connection Label */
1772#define CIU43 0x80000000 /* Channel 43 In Use */ 1532#define CIU43 0x80000000 /* Channel 43 In Use */
1773#define nCIU43 0x0
1774 1533
1775/* Bit masks for MXVR_ALLOC_11 */ 1534/* Bit masks for MXVR_ALLOC_11 */
1776 1535
1777#define CL44 0x7f /* Channel 44 Connection Label */ 1536#define CL44 0x7f /* Channel 44 Connection Label */
1778#define CIU44 0x80 /* Channel 44 In Use */ 1537#define CIU44 0x80 /* Channel 44 In Use */
1779#define nCIU44 0x0
1780#define CL45 0x7f00 /* Channel 45 Connection Label */ 1538#define CL45 0x7f00 /* Channel 45 Connection Label */
1781#define CIU45 0x8000 /* Channel 45 In Use */ 1539#define CIU45 0x8000 /* Channel 45 In Use */
1782#define nCIU45 0x0
1783#define CL46 0x7f0000 /* Channel 46 Connection Label */ 1540#define CL46 0x7f0000 /* Channel 46 Connection Label */
1784#define CIU46 0x800000 /* Channel 46 In Use */ 1541#define CIU46 0x800000 /* Channel 46 In Use */
1785#define nCIU46 0x0
1786#define CL47 0x7f000000 /* Channel 47 Connection Label */ 1542#define CL47 0x7f000000 /* Channel 47 Connection Label */
1787#define CIU47 0x80000000 /* Channel 47 In Use */ 1543#define CIU47 0x80000000 /* Channel 47 In Use */
1788#define nCIU47 0x0
1789 1544
1790/* Bit masks for MXVR_ALLOC_12 */ 1545/* Bit masks for MXVR_ALLOC_12 */
1791 1546
1792#define CL48 0x7f /* Channel 48 Connection Label */ 1547#define CL48 0x7f /* Channel 48 Connection Label */
1793#define CIU48 0x80 /* Channel 48 In Use */ 1548#define CIU48 0x80 /* Channel 48 In Use */
1794#define nCIU48 0x0
1795#define CL49 0x7f00 /* Channel 49 Connection Label */ 1549#define CL49 0x7f00 /* Channel 49 Connection Label */
1796#define CIU49 0x8000 /* Channel 49 In Use */ 1550#define CIU49 0x8000 /* Channel 49 In Use */
1797#define nCIU49 0x0
1798#define CL50 0x7f0000 /* Channel 50 Connection Label */ 1551#define CL50 0x7f0000 /* Channel 50 Connection Label */
1799#define CIU50 0x800000 /* Channel 50 In Use */ 1552#define CIU50 0x800000 /* Channel 50 In Use */
1800#define nCIU50 0x0
1801#define CL51 0x7f000000 /* Channel 51 Connection Label */ 1553#define CL51 0x7f000000 /* Channel 51 Connection Label */
1802#define CIU51 0x80000000 /* Channel 51 In Use */ 1554#define CIU51 0x80000000 /* Channel 51 In Use */
1803#define nCIU51 0x0
1804 1555
1805/* Bit masks for MXVR_ALLOC_13 */ 1556/* Bit masks for MXVR_ALLOC_13 */
1806 1557
1807#define CL52 0x7f /* Channel 52 Connection Label */ 1558#define CL52 0x7f /* Channel 52 Connection Label */
1808#define CIU52 0x80 /* Channel 52 In Use */ 1559#define CIU52 0x80 /* Channel 52 In Use */
1809#define nCIU52 0x0
1810#define CL53 0x7f00 /* Channel 53 Connection Label */ 1560#define CL53 0x7f00 /* Channel 53 Connection Label */
1811#define CIU53 0x8000 /* Channel 53 In Use */ 1561#define CIU53 0x8000 /* Channel 53 In Use */
1812#define nCIU53 0x0
1813#define CL54 0x7f0000 /* Channel 54 Connection Label */ 1562#define CL54 0x7f0000 /* Channel 54 Connection Label */
1814#define CIU54 0x800000 /* Channel 54 In Use */ 1563#define CIU54 0x800000 /* Channel 54 In Use */
1815#define nCIU54 0x0
1816#define CL55 0x7f000000 /* Channel 55 Connection Label */ 1564#define CL55 0x7f000000 /* Channel 55 Connection Label */
1817#define CIU55 0x80000000 /* Channel 55 In Use */ 1565#define CIU55 0x80000000 /* Channel 55 In Use */
1818#define nCIU55 0x0
1819 1566
1820/* Bit masks for MXVR_ALLOC_14 */ 1567/* Bit masks for MXVR_ALLOC_14 */
1821 1568
1822#define CL56 0x7f /* Channel 56 Connection Label */ 1569#define CL56 0x7f /* Channel 56 Connection Label */
1823#define CIU56 0x80 /* Channel 56 In Use */ 1570#define CIU56 0x80 /* Channel 56 In Use */
1824#define nCIU56 0x0
1825#define CL57 0x7f00 /* Channel 57 Connection Label */ 1571#define CL57 0x7f00 /* Channel 57 Connection Label */
1826#define CIU57 0x8000 /* Channel 57 In Use */ 1572#define CIU57 0x8000 /* Channel 57 In Use */
1827#define nCIU57 0x0
1828#define CL58 0x7f0000 /* Channel 58 Connection Label */ 1573#define CL58 0x7f0000 /* Channel 58 Connection Label */
1829#define CIU58 0x800000 /* Channel 58 In Use */ 1574#define CIU58 0x800000 /* Channel 58 In Use */
1830#define nCIU58 0x0
1831#define CL59 0x7f000000 /* Channel 59 Connection Label */ 1575#define CL59 0x7f000000 /* Channel 59 Connection Label */
1832#define CIU59 0x80000000 /* Channel 59 In Use */ 1576#define CIU59 0x80000000 /* Channel 59 In Use */
1833#define nCIU59 0x0
1834 1577
1835/* MXVR_SYNC_LCHAN_0 Masks */ 1578/* MXVR_SYNC_LCHAN_0 Masks */
1836 1579
@@ -1926,19 +1669,13 @@
1926/* Bit masks for MXVR_DMAx_CONFIG */ 1669/* Bit masks for MXVR_DMAx_CONFIG */
1927 1670
1928#define MDMAEN 0x1 /* DMA Channel Enable */ 1671#define MDMAEN 0x1 /* DMA Channel Enable */
1929#define nMDMAEN 0x0
1930#define DD 0x2 /* DMA Channel Direction */ 1672#define DD 0x2 /* DMA Channel Direction */
1931#define nDD 0x0
1932#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ 1673#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1933#define nBY4SWAPEN 0x0
1934#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ 1674#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1935#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ 1675#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1936#define nBITSWAPEN 0x0
1937#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ 1676#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1938#define nBY2SWAPEN 0x0
1939#define MFLOW 0x7000 /* DMA Channel Operation Flow */ 1677#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1940#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ 1678#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1941#define nFIXEDPM 0x0
1942#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ 1679#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1943#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ 1680#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1944#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ 1681#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
@@ -1946,94 +1683,71 @@
1946/* Bit masks for MXVR_AP_CTL */ 1683/* Bit masks for MXVR_AP_CTL */
1947 1684
1948#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ 1685#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1949#define nSTARTAP 0x0
1950#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ 1686#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1951#define nCANCELAP 0x0
1952#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ 1687#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1953#define nRESETAP 0x0
1954#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ 1688#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1955#define nAPRBE0 0x0
1956#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ 1689#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1957#define nAPRBE1 0x0
1958 1690
1959/* Bit masks for MXVR_APRB_START_ADDR */ 1691/* Bit masks for MXVR_APRB_START_ADDR */
1960 1692
1961#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ 1693#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1962 1694
1963/* Bit masks for MXVR_APRB_CURR_ADDR */ 1695/* Bit masks for MXVR_APRB_CURR_ADDR */
1964 1696
1965#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ 1697#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1966 1698
1967/* Bit masks for MXVR_APTB_START_ADDR */ 1699/* Bit masks for MXVR_APTB_START_ADDR */
1968 1700
1969#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ 1701#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1970 1702
1971/* Bit masks for MXVR_APTB_CURR_ADDR */ 1703/* Bit masks for MXVR_APTB_CURR_ADDR */
1972 1704
1973#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ 1705#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1974 1706
1975/* Bit masks for MXVR_CM_CTL */ 1707/* Bit masks for MXVR_CM_CTL */
1976 1708
1977#define STARTCM 0x1 /* Start Control Message Transmission */ 1709#define STARTCM 0x1 /* Start Control Message Transmission */
1978#define nSTARTCM 0x0
1979#define CANCELCM 0x2 /* Cancel Control Message Transmission */ 1710#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1980#define nCANCELCM 0x0
1981#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ 1711#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1982#define nCMRBE0 0x0
1983#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ 1712#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1984#define nCMRBE1 0x0
1985#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ 1713#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1986#define nCMRBE2 0x0
1987#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ 1714#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1988#define nCMRBE3 0x0
1989#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ 1715#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1990#define nCMRBE4 0x0
1991#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ 1716#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1992#define nCMRBE5 0x0
1993#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ 1717#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1994#define nCMRBE6 0x0
1995#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ 1718#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1996#define nCMRBE7 0x0
1997#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ 1719#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1998#define nCMRBE8 0x0
1999#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ 1720#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
2000#define nCMRBE9 0x0
2001#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ 1721#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
2002#define nCMRBE10 0x0
2003#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ 1722#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
2004#define nCMRBE11 0x0
2005#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ 1723#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
2006#define nCMRBE12 0x0
2007#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ 1724#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
2008#define nCMRBE13 0x0
2009#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ 1725#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
2010#define nCMRBE14 0x0
2011#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ 1726#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
2012#define nCMRBE15 0x0
2013 1727
2014/* Bit masks for MXVR_CMRB_START_ADDR */ 1728/* Bit masks for MXVR_CMRB_START_ADDR */
2015 1729
2016#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ 1730#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
2017 1731
2018/* Bit masks for MXVR_CMRB_CURR_ADDR */ 1732/* Bit masks for MXVR_CMRB_CURR_ADDR */
2019 1733
2020#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ 1734#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
2021 1735
2022/* Bit masks for MXVR_CMTB_START_ADDR */ 1736/* Bit masks for MXVR_CMTB_START_ADDR */
2023 1737
2024#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ 1738#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
2025 1739
2026/* Bit masks for MXVR_CMTB_CURR_ADDR */ 1740/* Bit masks for MXVR_CMTB_CURR_ADDR */
2027 1741
2028#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ 1742#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
2029 1743
2030/* Bit masks for MXVR_RRDB_START_ADDR */ 1744/* Bit masks for MXVR_RRDB_START_ADDR */
2031 1745
2032#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ 1746#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
2033 1747
2034/* Bit masks for MXVR_RRDB_CURR_ADDR */ 1748/* Bit masks for MXVR_RRDB_CURR_ADDR */
2035 1749
2036#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ 1750#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
2037 1751
2038/* Bit masks for MXVR_PAT_DATAx */ 1752/* Bit masks for MXVR_PAT_DATAx */
2039 1753
@@ -2045,136 +1759,72 @@
2045/* Bit masks for MXVR_PAT_EN_0 */ 1759/* Bit masks for MXVR_PAT_EN_0 */
2046 1760
2047#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ 1761#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2048#define nMATCH_EN_0_0 0x0
2049#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ 1762#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2050#define nMATCH_EN_0_1 0x0
2051#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ 1763#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2052#define nMATCH_EN_0_2 0x0
2053#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ 1764#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2054#define nMATCH_EN_0_3 0x0
2055#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ 1765#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2056#define nMATCH_EN_0_4 0x0
2057#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ 1766#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2058#define nMATCH_EN_0_5 0x0
2059#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ 1767#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2060#define nMATCH_EN_0_6 0x0
2061#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ 1768#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2062#define nMATCH_EN_0_7 0x0
2063#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ 1769#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2064#define nMATCH_EN_1_0 0x0
2065#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ 1770#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2066#define nMATCH_EN_1_1 0x0
2067#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ 1771#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2068#define nMATCH_EN_1_2 0x0
2069#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ 1772#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2070#define nMATCH_EN_1_3 0x0
2071#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ 1773#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2072#define nMATCH_EN_1_4 0x0
2073#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ 1774#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2074#define nMATCH_EN_1_5 0x0
2075#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ 1775#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2076#define nMATCH_EN_1_6 0x0
2077#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ 1776#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2078#define nMATCH_EN_1_7 0x0
2079#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ 1777#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2080#define nMATCH_EN_2_0 0x0
2081#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ 1778#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2082#define nMATCH_EN_2_1 0x0
2083#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ 1779#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2084#define nMATCH_EN_2_2 0x0
2085#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ 1780#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2086#define nMATCH_EN_2_3 0x0
2087#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ 1781#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2088#define nMATCH_EN_2_4 0x0
2089#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ 1782#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2090#define nMATCH_EN_2_5 0x0
2091#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ 1783#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2092#define nMATCH_EN_2_6 0x0
2093#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ 1784#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2094#define nMATCH_EN_2_7 0x0
2095#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ 1785#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2096#define nMATCH_EN_3_0 0x0
2097#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ 1786#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2098#define nMATCH_EN_3_1 0x0
2099#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ 1787#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2100#define nMATCH_EN_3_2 0x0
2101#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ 1788#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2102#define nMATCH_EN_3_3 0x0
2103#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ 1789#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2104#define nMATCH_EN_3_4 0x0
2105#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ 1790#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2106#define nMATCH_EN_3_5 0x0
2107#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ 1791#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2108#define nMATCH_EN_3_6 0x0
2109#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ 1792#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2110#define nMATCH_EN_3_7 0x0
2111 1793
2112/* Bit masks for MXVR_PAT_EN_1 */ 1794/* Bit masks for MXVR_PAT_EN_1 */
2113 1795
2114#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ 1796#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2115#define nMATCH_EN_0_0 0x0
2116#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ 1797#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2117#define nMATCH_EN_0_1 0x0
2118#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ 1798#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2119#define nMATCH_EN_0_2 0x0
2120#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ 1799#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2121#define nMATCH_EN_0_3 0x0
2122#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ 1800#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2123#define nMATCH_EN_0_4 0x0
2124#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ 1801#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2125#define nMATCH_EN_0_5 0x0
2126#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ 1802#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2127#define nMATCH_EN_0_6 0x0
2128#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ 1803#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2129#define nMATCH_EN_0_7 0x0
2130#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ 1804#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2131#define nMATCH_EN_1_0 0x0
2132#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ 1805#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2133#define nMATCH_EN_1_1 0x0
2134#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ 1806#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2135#define nMATCH_EN_1_2 0x0
2136#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ 1807#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2137#define nMATCH_EN_1_3 0x0
2138#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ 1808#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2139#define nMATCH_EN_1_4 0x0
2140#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ 1809#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2141#define nMATCH_EN_1_5 0x0
2142#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ 1810#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2143#define nMATCH_EN_1_6 0x0
2144#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ 1811#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2145#define nMATCH_EN_1_7 0x0
2146#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ 1812#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2147#define nMATCH_EN_2_0 0x0
2148#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ 1813#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2149#define nMATCH_EN_2_1 0x0
2150#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ 1814#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2151#define nMATCH_EN_2_2 0x0
2152#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ 1815#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2153#define nMATCH_EN_2_3 0x0
2154#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ 1816#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2155#define nMATCH_EN_2_4 0x0
2156#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ 1817#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2157#define nMATCH_EN_2_5 0x0
2158#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ 1818#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2159#define nMATCH_EN_2_6 0x0
2160#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ 1819#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2161#define nMATCH_EN_2_7 0x0
2162#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ 1820#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2163#define nMATCH_EN_3_0 0x0
2164#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ 1821#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2165#define nMATCH_EN_3_1 0x0
2166#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ 1822#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2167#define nMATCH_EN_3_2 0x0
2168#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ 1823#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2169#define nMATCH_EN_3_3 0x0
2170#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ 1824#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2171#define nMATCH_EN_3_4 0x0
2172#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ 1825#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2173#define nMATCH_EN_3_5 0x0
2174#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ 1826#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2175#define nMATCH_EN_3_6 0x0
2176#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ 1827#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2177#define nMATCH_EN_3_7 0x0
2178 1828
2179/* Bit masks for MXVR_FRAME_CNT_0 */ 1829/* Bit masks for MXVR_FRAME_CNT_0 */
2180 1830
@@ -2188,226 +1838,166 @@
2188 1838
2189#define TX_CH0 0x3f /* Transmit Channel 0 */ 1839#define TX_CH0 0x3f /* Transmit Channel 0 */
2190#define MUTE_CH0 0x80 /* Mute Channel 0 */ 1840#define MUTE_CH0 0x80 /* Mute Channel 0 */
2191#define nMUTE_CH0 0x0
2192#define TX_CH1 0x3f00 /* Transmit Channel 0 */ 1841#define TX_CH1 0x3f00 /* Transmit Channel 0 */
2193#define MUTE_CH1 0x8000 /* Mute Channel 0 */ 1842#define MUTE_CH1 0x8000 /* Mute Channel 0 */
2194#define nMUTE_CH1 0x0
2195#define TX_CH2 0x3f0000 /* Transmit Channel 0 */ 1843#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
2196#define MUTE_CH2 0x800000 /* Mute Channel 0 */ 1844#define MUTE_CH2 0x800000 /* Mute Channel 0 */
2197#define nMUTE_CH2 0x0
2198#define TX_CH3 0x3f000000 /* Transmit Channel 0 */ 1845#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
2199#define MUTE_CH3 0x80000000 /* Mute Channel 0 */ 1846#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
2200#define nMUTE_CH3 0x0
2201 1847
2202/* Bit masks for MXVR_ROUTING_1 */ 1848/* Bit masks for MXVR_ROUTING_1 */
2203 1849
2204#define TX_CH4 0x3f /* Transmit Channel 4 */ 1850#define TX_CH4 0x3f /* Transmit Channel 4 */
2205#define MUTE_CH4 0x80 /* Mute Channel 4 */ 1851#define MUTE_CH4 0x80 /* Mute Channel 4 */
2206#define nMUTE_CH4 0x0
2207#define TX_CH5 0x3f00 /* Transmit Channel 5 */ 1852#define TX_CH5 0x3f00 /* Transmit Channel 5 */
2208#define MUTE_CH5 0x8000 /* Mute Channel 5 */ 1853#define MUTE_CH5 0x8000 /* Mute Channel 5 */
2209#define nMUTE_CH5 0x0
2210#define TX_CH6 0x3f0000 /* Transmit Channel 6 */ 1854#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
2211#define MUTE_CH6 0x800000 /* Mute Channel 6 */ 1855#define MUTE_CH6 0x800000 /* Mute Channel 6 */
2212#define nMUTE_CH6 0x0
2213#define TX_CH7 0x3f000000 /* Transmit Channel 7 */ 1856#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
2214#define MUTE_CH7 0x80000000 /* Mute Channel 7 */ 1857#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
2215#define nMUTE_CH7 0x0
2216 1858
2217/* Bit masks for MXVR_ROUTING_2 */ 1859/* Bit masks for MXVR_ROUTING_2 */
2218 1860
2219#define TX_CH8 0x3f /* Transmit Channel 8 */ 1861#define TX_CH8 0x3f /* Transmit Channel 8 */
2220#define MUTE_CH8 0x80 /* Mute Channel 8 */ 1862#define MUTE_CH8 0x80 /* Mute Channel 8 */
2221#define nMUTE_CH8 0x0
2222#define TX_CH9 0x3f00 /* Transmit Channel 9 */ 1863#define TX_CH9 0x3f00 /* Transmit Channel 9 */
2223#define MUTE_CH9 0x8000 /* Mute Channel 9 */ 1864#define MUTE_CH9 0x8000 /* Mute Channel 9 */
2224#define nMUTE_CH9 0x0
2225#define TX_CH10 0x3f0000 /* Transmit Channel 10 */ 1865#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
2226#define MUTE_CH10 0x800000 /* Mute Channel 10 */ 1866#define MUTE_CH10 0x800000 /* Mute Channel 10 */
2227#define nMUTE_CH10 0x0
2228#define TX_CH11 0x3f000000 /* Transmit Channel 11 */ 1867#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
2229#define MUTE_CH11 0x80000000 /* Mute Channel 11 */ 1868#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
2230#define nMUTE_CH11 0x0
2231 1869
2232/* Bit masks for MXVR_ROUTING_3 */ 1870/* Bit masks for MXVR_ROUTING_3 */
2233 1871
2234#define TX_CH12 0x3f /* Transmit Channel 12 */ 1872#define TX_CH12 0x3f /* Transmit Channel 12 */
2235#define MUTE_CH12 0x80 /* Mute Channel 12 */ 1873#define MUTE_CH12 0x80 /* Mute Channel 12 */
2236#define nMUTE_CH12 0x0
2237#define TX_CH13 0x3f00 /* Transmit Channel 13 */ 1874#define TX_CH13 0x3f00 /* Transmit Channel 13 */
2238#define MUTE_CH13 0x8000 /* Mute Channel 13 */ 1875#define MUTE_CH13 0x8000 /* Mute Channel 13 */
2239#define nMUTE_CH13 0x0
2240#define TX_CH14 0x3f0000 /* Transmit Channel 14 */ 1876#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
2241#define MUTE_CH14 0x800000 /* Mute Channel 14 */ 1877#define MUTE_CH14 0x800000 /* Mute Channel 14 */
2242#define nMUTE_CH14 0x0
2243#define TX_CH15 0x3f000000 /* Transmit Channel 15 */ 1878#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
2244#define MUTE_CH15 0x80000000 /* Mute Channel 15 */ 1879#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
2245#define nMUTE_CH15 0x0
2246 1880
2247/* Bit masks for MXVR_ROUTING_4 */ 1881/* Bit masks for MXVR_ROUTING_4 */
2248 1882
2249#define TX_CH16 0x3f /* Transmit Channel 16 */ 1883#define TX_CH16 0x3f /* Transmit Channel 16 */
2250#define MUTE_CH16 0x80 /* Mute Channel 16 */ 1884#define MUTE_CH16 0x80 /* Mute Channel 16 */
2251#define nMUTE_CH16 0x0
2252#define TX_CH17 0x3f00 /* Transmit Channel 17 */ 1885#define TX_CH17 0x3f00 /* Transmit Channel 17 */
2253#define MUTE_CH17 0x8000 /* Mute Channel 17 */ 1886#define MUTE_CH17 0x8000 /* Mute Channel 17 */
2254#define nMUTE_CH17 0x0
2255#define TX_CH18 0x3f0000 /* Transmit Channel 18 */ 1887#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
2256#define MUTE_CH18 0x800000 /* Mute Channel 18 */ 1888#define MUTE_CH18 0x800000 /* Mute Channel 18 */
2257#define nMUTE_CH18 0x0
2258#define TX_CH19 0x3f000000 /* Transmit Channel 19 */ 1889#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
2259#define MUTE_CH19 0x80000000 /* Mute Channel 19 */ 1890#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
2260#define nMUTE_CH19 0x0
2261 1891
2262/* Bit masks for MXVR_ROUTING_5 */ 1892/* Bit masks for MXVR_ROUTING_5 */
2263 1893
2264#define TX_CH20 0x3f /* Transmit Channel 20 */ 1894#define TX_CH20 0x3f /* Transmit Channel 20 */
2265#define MUTE_CH20 0x80 /* Mute Channel 20 */ 1895#define MUTE_CH20 0x80 /* Mute Channel 20 */
2266#define nMUTE_CH20 0x0
2267#define TX_CH21 0x3f00 /* Transmit Channel 21 */ 1896#define TX_CH21 0x3f00 /* Transmit Channel 21 */
2268#define MUTE_CH21 0x8000 /* Mute Channel 21 */ 1897#define MUTE_CH21 0x8000 /* Mute Channel 21 */
2269#define nMUTE_CH21 0x0
2270#define TX_CH22 0x3f0000 /* Transmit Channel 22 */ 1898#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
2271#define MUTE_CH22 0x800000 /* Mute Channel 22 */ 1899#define MUTE_CH22 0x800000 /* Mute Channel 22 */
2272#define nMUTE_CH22 0x0
2273#define TX_CH23 0x3f000000 /* Transmit Channel 23 */ 1900#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
2274#define MUTE_CH23 0x80000000 /* Mute Channel 23 */ 1901#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
2275#define nMUTE_CH23 0x0
2276 1902
2277/* Bit masks for MXVR_ROUTING_6 */ 1903/* Bit masks for MXVR_ROUTING_6 */
2278 1904
2279#define TX_CH24 0x3f /* Transmit Channel 24 */ 1905#define TX_CH24 0x3f /* Transmit Channel 24 */
2280#define MUTE_CH24 0x80 /* Mute Channel 24 */ 1906#define MUTE_CH24 0x80 /* Mute Channel 24 */
2281#define nMUTE_CH24 0x0
2282#define TX_CH25 0x3f00 /* Transmit Channel 25 */ 1907#define TX_CH25 0x3f00 /* Transmit Channel 25 */
2283#define MUTE_CH25 0x8000 /* Mute Channel 25 */ 1908#define MUTE_CH25 0x8000 /* Mute Channel 25 */
2284#define nMUTE_CH25 0x0
2285#define TX_CH26 0x3f0000 /* Transmit Channel 26 */ 1909#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
2286#define MUTE_CH26 0x800000 /* Mute Channel 26 */ 1910#define MUTE_CH26 0x800000 /* Mute Channel 26 */
2287#define nMUTE_CH26 0x0
2288#define TX_CH27 0x3f000000 /* Transmit Channel 27 */ 1911#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
2289#define MUTE_CH27 0x80000000 /* Mute Channel 27 */ 1912#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
2290#define nMUTE_CH27 0x0
2291 1913
2292/* Bit masks for MXVR_ROUTING_7 */ 1914/* Bit masks for MXVR_ROUTING_7 */
2293 1915
2294#define TX_CH28 0x3f /* Transmit Channel 28 */ 1916#define TX_CH28 0x3f /* Transmit Channel 28 */
2295#define MUTE_CH28 0x80 /* Mute Channel 28 */ 1917#define MUTE_CH28 0x80 /* Mute Channel 28 */
2296#define nMUTE_CH28 0x0
2297#define TX_CH29 0x3f00 /* Transmit Channel 29 */ 1918#define TX_CH29 0x3f00 /* Transmit Channel 29 */
2298#define MUTE_CH29 0x8000 /* Mute Channel 29 */ 1919#define MUTE_CH29 0x8000 /* Mute Channel 29 */
2299#define nMUTE_CH29 0x0
2300#define TX_CH30 0x3f0000 /* Transmit Channel 30 */ 1920#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
2301#define MUTE_CH30 0x800000 /* Mute Channel 30 */ 1921#define MUTE_CH30 0x800000 /* Mute Channel 30 */
2302#define nMUTE_CH30 0x0
2303#define TX_CH31 0x3f000000 /* Transmit Channel 31 */ 1922#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
2304#define MUTE_CH31 0x80000000 /* Mute Channel 31 */ 1923#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
2305#define nMUTE_CH31 0x0
2306 1924
2307/* Bit masks for MXVR_ROUTING_8 */ 1925/* Bit masks for MXVR_ROUTING_8 */
2308 1926
2309#define TX_CH32 0x3f /* Transmit Channel 32 */ 1927#define TX_CH32 0x3f /* Transmit Channel 32 */
2310#define MUTE_CH32 0x80 /* Mute Channel 32 */ 1928#define MUTE_CH32 0x80 /* Mute Channel 32 */
2311#define nMUTE_CH32 0x0
2312#define TX_CH33 0x3f00 /* Transmit Channel 33 */ 1929#define TX_CH33 0x3f00 /* Transmit Channel 33 */
2313#define MUTE_CH33 0x8000 /* Mute Channel 33 */ 1930#define MUTE_CH33 0x8000 /* Mute Channel 33 */
2314#define nMUTE_CH33 0x0
2315#define TX_CH34 0x3f0000 /* Transmit Channel 34 */ 1931#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
2316#define MUTE_CH34 0x800000 /* Mute Channel 34 */ 1932#define MUTE_CH34 0x800000 /* Mute Channel 34 */
2317#define nMUTE_CH34 0x0
2318#define TX_CH35 0x3f000000 /* Transmit Channel 35 */ 1933#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
2319#define MUTE_CH35 0x80000000 /* Mute Channel 35 */ 1934#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
2320#define nMUTE_CH35 0x0
2321 1935
2322/* Bit masks for MXVR_ROUTING_9 */ 1936/* Bit masks for MXVR_ROUTING_9 */
2323 1937
2324#define TX_CH36 0x3f /* Transmit Channel 36 */ 1938#define TX_CH36 0x3f /* Transmit Channel 36 */
2325#define MUTE_CH36 0x80 /* Mute Channel 36 */ 1939#define MUTE_CH36 0x80 /* Mute Channel 36 */
2326#define nMUTE_CH36 0x0
2327#define TX_CH37 0x3f00 /* Transmit Channel 37 */ 1940#define TX_CH37 0x3f00 /* Transmit Channel 37 */
2328#define MUTE_CH37 0x8000 /* Mute Channel 37 */ 1941#define MUTE_CH37 0x8000 /* Mute Channel 37 */
2329#define nMUTE_CH37 0x0
2330#define TX_CH38 0x3f0000 /* Transmit Channel 38 */ 1942#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
2331#define MUTE_CH38 0x800000 /* Mute Channel 38 */ 1943#define MUTE_CH38 0x800000 /* Mute Channel 38 */
2332#define nMUTE_CH38 0x0
2333#define TX_CH39 0x3f000000 /* Transmit Channel 39 */ 1944#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
2334#define MUTE_CH39 0x80000000 /* Mute Channel 39 */ 1945#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
2335#define nMUTE_CH39 0x0
2336 1946
2337/* Bit masks for MXVR_ROUTING_10 */ 1947/* Bit masks for MXVR_ROUTING_10 */
2338 1948
2339#define TX_CH40 0x3f /* Transmit Channel 40 */ 1949#define TX_CH40 0x3f /* Transmit Channel 40 */
2340#define MUTE_CH40 0x80 /* Mute Channel 40 */ 1950#define MUTE_CH40 0x80 /* Mute Channel 40 */
2341#define nMUTE_CH40 0x0
2342#define TX_CH41 0x3f00 /* Transmit Channel 41 */ 1951#define TX_CH41 0x3f00 /* Transmit Channel 41 */
2343#define MUTE_CH41 0x8000 /* Mute Channel 41 */ 1952#define MUTE_CH41 0x8000 /* Mute Channel 41 */
2344#define nMUTE_CH41 0x0
2345#define TX_CH42 0x3f0000 /* Transmit Channel 42 */ 1953#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
2346#define MUTE_CH42 0x800000 /* Mute Channel 42 */ 1954#define MUTE_CH42 0x800000 /* Mute Channel 42 */
2347#define nMUTE_CH42 0x0
2348#define TX_CH43 0x3f000000 /* Transmit Channel 43 */ 1955#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
2349#define MUTE_CH43 0x80000000 /* Mute Channel 43 */ 1956#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
2350#define nMUTE_CH43 0x0
2351 1957
2352/* Bit masks for MXVR_ROUTING_11 */ 1958/* Bit masks for MXVR_ROUTING_11 */
2353 1959
2354#define TX_CH44 0x3f /* Transmit Channel 44 */ 1960#define TX_CH44 0x3f /* Transmit Channel 44 */
2355#define MUTE_CH44 0x80 /* Mute Channel 44 */ 1961#define MUTE_CH44 0x80 /* Mute Channel 44 */
2356#define nMUTE_CH44 0x0
2357#define TX_CH45 0x3f00 /* Transmit Channel 45 */ 1962#define TX_CH45 0x3f00 /* Transmit Channel 45 */
2358#define MUTE_CH45 0x8000 /* Mute Channel 45 */ 1963#define MUTE_CH45 0x8000 /* Mute Channel 45 */
2359#define nMUTE_CH45 0x0
2360#define TX_CH46 0x3f0000 /* Transmit Channel 46 */ 1964#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
2361#define MUTE_CH46 0x800000 /* Mute Channel 46 */ 1965#define MUTE_CH46 0x800000 /* Mute Channel 46 */
2362#define nMUTE_CH46 0x0
2363#define TX_CH47 0x3f000000 /* Transmit Channel 47 */ 1966#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
2364#define MUTE_CH47 0x80000000 /* Mute Channel 47 */ 1967#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
2365#define nMUTE_CH47 0x0
2366 1968
2367/* Bit masks for MXVR_ROUTING_12 */ 1969/* Bit masks for MXVR_ROUTING_12 */
2368 1970
2369#define TX_CH48 0x3f /* Transmit Channel 48 */ 1971#define TX_CH48 0x3f /* Transmit Channel 48 */
2370#define MUTE_CH48 0x80 /* Mute Channel 48 */ 1972#define MUTE_CH48 0x80 /* Mute Channel 48 */
2371#define nMUTE_CH48 0x0
2372#define TX_CH49 0x3f00 /* Transmit Channel 49 */ 1973#define TX_CH49 0x3f00 /* Transmit Channel 49 */
2373#define MUTE_CH49 0x8000 /* Mute Channel 49 */ 1974#define MUTE_CH49 0x8000 /* Mute Channel 49 */
2374#define nMUTE_CH49 0x0
2375#define TX_CH50 0x3f0000 /* Transmit Channel 50 */ 1975#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
2376#define MUTE_CH50 0x800000 /* Mute Channel 50 */ 1976#define MUTE_CH50 0x800000 /* Mute Channel 50 */
2377#define nMUTE_CH50 0x0
2378#define TX_CH51 0x3f000000 /* Transmit Channel 51 */ 1977#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
2379#define MUTE_CH51 0x80000000 /* Mute Channel 51 */ 1978#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
2380#define nMUTE_CH51 0x0
2381 1979
2382/* Bit masks for MXVR_ROUTING_13 */ 1980/* Bit masks for MXVR_ROUTING_13 */
2383 1981
2384#define TX_CH52 0x3f /* Transmit Channel 52 */ 1982#define TX_CH52 0x3f /* Transmit Channel 52 */
2385#define MUTE_CH52 0x80 /* Mute Channel 52 */ 1983#define MUTE_CH52 0x80 /* Mute Channel 52 */
2386#define nMUTE_CH52 0x0
2387#define TX_CH53 0x3f00 /* Transmit Channel 53 */ 1984#define TX_CH53 0x3f00 /* Transmit Channel 53 */
2388#define MUTE_CH53 0x8000 /* Mute Channel 53 */ 1985#define MUTE_CH53 0x8000 /* Mute Channel 53 */
2389#define nMUTE_CH53 0x0
2390#define TX_CH54 0x3f0000 /* Transmit Channel 54 */ 1986#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
2391#define MUTE_CH54 0x800000 /* Mute Channel 54 */ 1987#define MUTE_CH54 0x800000 /* Mute Channel 54 */
2392#define nMUTE_CH54 0x0
2393#define TX_CH55 0x3f000000 /* Transmit Channel 55 */ 1988#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
2394#define MUTE_CH55 0x80000000 /* Mute Channel 55 */ 1989#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
2395#define nMUTE_CH55 0x0
2396 1990
2397/* Bit masks for MXVR_ROUTING_14 */ 1991/* Bit masks for MXVR_ROUTING_14 */
2398 1992
2399#define TX_CH56 0x3f /* Transmit Channel 56 */ 1993#define TX_CH56 0x3f /* Transmit Channel 56 */
2400#define MUTE_CH56 0x80 /* Mute Channel 56 */ 1994#define MUTE_CH56 0x80 /* Mute Channel 56 */
2401#define nMUTE_CH56 0x0
2402#define TX_CH57 0x3f00 /* Transmit Channel 57 */ 1995#define TX_CH57 0x3f00 /* Transmit Channel 57 */
2403#define MUTE_CH57 0x8000 /* Mute Channel 57 */ 1996#define MUTE_CH57 0x8000 /* Mute Channel 57 */
2404#define nMUTE_CH57 0x0
2405#define TX_CH58 0x3f0000 /* Transmit Channel 58 */ 1997#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
2406#define MUTE_CH58 0x800000 /* Mute Channel 58 */ 1998#define MUTE_CH58 0x800000 /* Mute Channel 58 */
2407#define nMUTE_CH58 0x0
2408#define TX_CH59 0x3f000000 /* Transmit Channel 59 */ 1999#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
2409#define MUTE_CH59 0x80000000 /* Mute Channel 59 */ 2000#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
2410#define nMUTE_CH59 0x0
2411 2001
2412/* Bit masks for MXVR_BLOCK_CNT */ 2002/* Bit masks for MXVR_BLOCK_CNT */
2413 2003
@@ -2416,53 +2006,37 @@
2416/* Bit masks for MXVR_CLK_CTL */ 2006/* Bit masks for MXVR_CLK_CTL */
2417 2007
2418#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ 2008#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
2419#define nMXTALCEN 0x0
2420#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ 2009#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
2421#define nMXTALFEN 0x0
2422#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ 2010#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
2423#define CLKX3SEL 0x80 /* Clock Generation Source Select */ 2011#define CLKX3SEL 0x80 /* Clock Generation Source Select */
2424#define nCLKX3SEL 0x0
2425#define MMCLKEN 0x100 /* Master Clock Enable */ 2012#define MMCLKEN 0x100 /* Master Clock Enable */
2426#define nMMCLKEN 0x0
2427#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ 2013#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
2428#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ 2014#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
2429#define MBCLKEN 0x10000 /* Bit Clock Enable */ 2015#define MBCLKEN 0x10000 /* Bit Clock Enable */
2430#define nMBCLKEN 0x0
2431#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ 2016#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
2432#define INVRX 0x800000 /* Invert Receive Data */ 2017#define INVRX 0x800000 /* Invert Receive Data */
2433#define nINVRX 0x0
2434#define MFSEN 0x1000000 /* Frame Sync Enable */ 2018#define MFSEN 0x1000000 /* Frame Sync Enable */
2435#define nMFSEN 0x0
2436#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ 2019#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
2437#define MFSSEL 0x60000000 /* Frame Sync Select */ 2020#define MFSSEL 0x60000000 /* Frame Sync Select */
2438#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ 2021#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2439#define nMFSSYNC 0x0
2440 2022
2441/* Bit masks for MXVR_CDRPLL_CTL */ 2023/* Bit masks for MXVR_CDRPLL_CTL */
2442 2024
2443#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ 2025#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2444#define nCDRSMEN 0x0
2445#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ 2026#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2446#define nCDRRSTB 0x0
2447#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ 2027#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2448#define nCDRSVCO 0x0
2449#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ 2028#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2450#define nCDRMODE 0x0
2451#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ 2029#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2452#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ 2030#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2453#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ 2031#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2454#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ 2032#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2455#define nCDRSHPEN 0x0
2456#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ 2033#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2457 2034
2458/* Bit masks for MXVR_FMPLL_CTL */ 2035/* Bit masks for MXVR_FMPLL_CTL */
2459 2036
2460#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ 2037#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2461#define nFMSMEN 0x0
2462#define FMRSTB 0x2 /* MXVR FMPLL Reset */ 2038#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2463#define nFMRSTB 0x0
2464#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ 2039#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2465#define nFMSVCO 0x0
2466#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ 2040#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2467#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ 2041#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2468#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ 2042#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
@@ -2470,15 +2044,10 @@
2470/* Bit masks for MXVR_PIN_CTL */ 2044/* Bit masks for MXVR_PIN_CTL */
2471 2045
2472#define MTXONBOD 0x1 /* MTXONB Open Drain Select */ 2046#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2473#define nMTXONBOD 0x0
2474#define MTXONBG 0x2 /* MTXONB Gates MTX Select */ 2047#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2475#define nMTXONBG 0x0
2476#define MFSOE 0x10 /* MFS Output Enable */ 2048#define MFSOE 0x10 /* MFS Output Enable */
2477#define nMFSOE 0x0
2478#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ 2049#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2479#define nMFSGPSEL 0x0
2480#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ 2050#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2481#define nMFSGPDAT 0x0
2482 2051
2483/* Bit masks for MXVR_SCLK_CNT */ 2052/* Bit masks for MXVR_SCLK_CNT */
2484 2053
@@ -2487,7 +2056,6 @@
2487/* Bit masks for KPAD_CTL */ 2056/* Bit masks for KPAD_CTL */
2488 2057
2489#define KPAD_EN 0x1 /* Keypad Enable */ 2058#define KPAD_EN 0x1 /* Keypad Enable */
2490#define nKPAD_EN 0x0
2491#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 2059#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2492#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 2060#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2493#define KPAD_COLEN 0xe000 /* Column Enable Width */ 2061#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -2509,29 +2077,21 @@
2509/* Bit masks for KPAD_STAT */ 2077/* Bit masks for KPAD_STAT */
2510 2078
2511#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 2079#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2512#define nKPAD_IRQ 0x0
2513#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 2080#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2514#define KPAD_PRESSED 0x8 /* Key press current status */ 2081#define KPAD_PRESSED 0x8 /* Key press current status */
2515#define nKPAD_PRESSED 0x0
2516 2082
2517/* Bit masks for KPAD_SOFTEVAL */ 2083/* Bit masks for KPAD_SOFTEVAL */
2518 2084
2519#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 2085#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2520#define nKPAD_SOFTEVAL_E 0x0
2521 2086
2522/* Bit masks for SDH_COMMAND */ 2087/* Bit masks for SDH_COMMAND */
2523 2088
2524#define CMD_IDX 0x3f /* Command Index */ 2089#define CMD_IDX 0x3f /* Command Index */
2525#define CMD_RSP 0x40 /* Response */ 2090#define CMD_RSP 0x40 /* Response */
2526#define nCMD_RSP 0x0
2527#define CMD_L_RSP 0x80 /* Long Response */ 2091#define CMD_L_RSP 0x80 /* Long Response */
2528#define nCMD_L_RSP 0x0
2529#define CMD_INT_E 0x100 /* Command Interrupt */ 2092#define CMD_INT_E 0x100 /* Command Interrupt */
2530#define nCMD_INT_E 0x0
2531#define CMD_PEND_E 0x200 /* Command Pending */ 2093#define CMD_PEND_E 0x200 /* Command Pending */
2532#define nCMD_PEND_E 0x0
2533#define CMD_E 0x400 /* Command Enable */ 2094#define CMD_E 0x400 /* Command Enable */
2534#define nCMD_E 0x0
2535 2095
2536/* Bit masks for SDH_PWR_CTL */ 2096/* Bit masks for SDH_PWR_CTL */
2537 2097
@@ -2540,21 +2100,15 @@
2540#define TBD 0x3c /* TBD */ 2100#define TBD 0x3c /* TBD */
2541#endif 2101#endif
2542#define SD_CMD_OD 0x40 /* Open Drain Output */ 2102#define SD_CMD_OD 0x40 /* Open Drain Output */
2543#define nSD_CMD_OD 0x0
2544#define ROD_CTL 0x80 /* Rod Control */ 2103#define ROD_CTL 0x80 /* Rod Control */
2545#define nROD_CTL 0x0
2546 2104
2547/* Bit masks for SDH_CLK_CTL */ 2105/* Bit masks for SDH_CLK_CTL */
2548 2106
2549#define CLKDIV 0xff /* MC_CLK Divisor */ 2107#define CLKDIV 0xff /* MC_CLK Divisor */
2550#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 2108#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2551#define nCLK_E 0x0
2552#define PWR_SV_E 0x200 /* Power Save Enable */ 2109#define PWR_SV_E 0x200 /* Power Save Enable */
2553#define nPWR_SV_E 0x0
2554#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 2110#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2555#define nCLKDIV_BYPASS 0x0
2556#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 2111#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2557#define nWIDE_BUS 0x0
2558 2112
2559/* Bit masks for SDH_RESP_CMD */ 2113/* Bit masks for SDH_RESP_CMD */
2560 2114
@@ -2563,133 +2117,74 @@
2563/* Bit masks for SDH_DATA_CTL */ 2117/* Bit masks for SDH_DATA_CTL */
2564 2118
2565#define DTX_E 0x1 /* Data Transfer Enable */ 2119#define DTX_E 0x1 /* Data Transfer Enable */
2566#define nDTX_E 0x0
2567#define DTX_DIR 0x2 /* Data Transfer Direction */ 2120#define DTX_DIR 0x2 /* Data Transfer Direction */
2568#define nDTX_DIR 0x0
2569#define DTX_MODE 0x4 /* Data Transfer Mode */ 2121#define DTX_MODE 0x4 /* Data Transfer Mode */
2570#define nDTX_MODE 0x0
2571#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 2122#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2572#define nDTX_DMA_E 0x0
2573#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 2123#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2574 2124
2575/* Bit masks for SDH_STATUS */ 2125/* Bit masks for SDH_STATUS */
2576 2126
2577#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 2127#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2578#define nCMD_CRC_FAIL 0x0
2579#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 2128#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2580#define nDAT_CRC_FAIL 0x0 2129#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2581#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 2130#define DAT_TIME_OUT 0x8 /* Data Time Out */
2582#define nCMD_TIMEOUT 0x0
2583#define DAT_TIMEOUT 0x8 /* Data Time Out */
2584#define nDAT_TIMEOUT 0x0
2585#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 2131#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2586#define nTX_UNDERRUN 0x0
2587#define RX_OVERRUN 0x20 /* Receive Overrun */ 2132#define RX_OVERRUN 0x20 /* Receive Overrun */
2588#define nRX_OVERRUN 0x0
2589#define CMD_RESP_END 0x40 /* CMD Response End */ 2133#define CMD_RESP_END 0x40 /* CMD Response End */
2590#define nCMD_RESP_END 0x0
2591#define CMD_SENT 0x80 /* CMD Sent */ 2134#define CMD_SENT 0x80 /* CMD Sent */
2592#define nCMD_SENT 0x0
2593#define DAT_END 0x100 /* Data End */ 2135#define DAT_END 0x100 /* Data End */
2594#define nDAT_END 0x0
2595#define START_BIT_ERR 0x200 /* Start Bit Error */ 2136#define START_BIT_ERR 0x200 /* Start Bit Error */
2596#define nSTART_BIT_ERR 0x0
2597#define DAT_BLK_END 0x400 /* Data Block End */ 2137#define DAT_BLK_END 0x400 /* Data Block End */
2598#define nDAT_BLK_END 0x0
2599#define CMD_ACT 0x800 /* CMD Active */ 2138#define CMD_ACT 0x800 /* CMD Active */
2600#define nCMD_ACT 0x0
2601#define TX_ACT 0x1000 /* Transmit Active */ 2139#define TX_ACT 0x1000 /* Transmit Active */
2602#define nTX_ACT 0x0
2603#define RX_ACT 0x2000 /* Receive Active */ 2140#define RX_ACT 0x2000 /* Receive Active */
2604#define nRX_ACT 0x0
2605#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 2141#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2606#define nTX_FIFO_STAT 0x0
2607#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 2142#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2608#define nRX_FIFO_STAT 0x0
2609#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 2143#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2610#define nTX_FIFO_FULL 0x0
2611#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 2144#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2612#define nRX_FIFO_FULL 0x0
2613#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 2145#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2614#define nTX_FIFO_ZERO 0x0
2615#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 2146#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2616#define nRX_DAT_ZERO 0x0
2617#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 2147#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2618#define nTX_DAT_RDY 0x0
2619#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 2148#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2620#define nRX_FIFO_RDY 0x0
2621 2149
2622/* Bit masks for SDH_STATUS_CLR */ 2150/* Bit masks for SDH_STATUS_CLR */
2623 2151
2624#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 2152#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2625#define nCMD_CRC_FAIL_STAT 0x0
2626#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 2153#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2627#define nDAT_CRC_FAIL_STAT 0x0
2628#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 2154#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2629#define nCMD_TIMEOUT_STAT 0x0
2630#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 2155#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2631#define nDAT_TIMEOUT_STAT 0x0
2632#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 2156#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2633#define nTX_UNDERRUN_STAT 0x0
2634#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 2157#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2635#define nRX_OVERRUN_STAT 0x0
2636#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 2158#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2637#define nCMD_RESP_END_STAT 0x0
2638#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 2159#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2639#define nCMD_SENT_STAT 0x0
2640#define DAT_END_STAT 0x100 /* Data End Status */ 2160#define DAT_END_STAT 0x100 /* Data End Status */
2641#define nDAT_END_STAT 0x0
2642#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 2161#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2643#define nSTART_BIT_ERR_STAT 0x0
2644#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 2162#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2645#define nDAT_BLK_END_STAT 0x0
2646 2163
2647/* Bit masks for SDH_MASK0 */ 2164/* Bit masks for SDH_MASK0 */
2648 2165
2649#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 2166#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2650#define nCMD_CRC_FAIL_MASK 0x0
2651#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 2167#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2652#define nDAT_CRC_FAIL_MASK 0x0
2653#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 2168#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2654#define nCMD_TIMEOUT_MASK 0x0
2655#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 2169#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2656#define nDAT_TIMEOUT_MASK 0x0
2657#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 2170#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2658#define nTX_UNDERRUN_MASK 0x0
2659#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 2171#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2660#define nRX_OVERRUN_MASK 0x0
2661#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 2172#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2662#define nCMD_RESP_END_MASK 0x0
2663#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 2173#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2664#define nCMD_SENT_MASK 0x0
2665#define DAT_END_MASK 0x100 /* Data End Mask */ 2174#define DAT_END_MASK 0x100 /* Data End Mask */
2666#define nDAT_END_MASK 0x0
2667#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 2175#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2668#define nSTART_BIT_ERR_MASK 0x0
2669#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 2176#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2670#define nDAT_BLK_END_MASK 0x0
2671#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 2177#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2672#define nCMD_ACT_MASK 0x0
2673#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 2178#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2674#define nTX_ACT_MASK 0x0
2675#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 2179#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2676#define nRX_ACT_MASK 0x0
2677#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 2180#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2678#define nTX_FIFO_STAT_MASK 0x0
2679#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 2181#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2680#define nRX_FIFO_STAT_MASK 0x0
2681#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 2182#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2682#define nTX_FIFO_FULL_MASK 0x0
2683#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 2183#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2684#define nRX_FIFO_FULL_MASK 0x0
2685#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 2184#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2686#define nTX_FIFO_ZERO_MASK 0x0
2687#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 2185#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2688#define nRX_DAT_ZERO_MASK 0x0
2689#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 2186#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2690#define nTX_DAT_RDY_MASK 0x0
2691#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 2187#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2692#define nRX_FIFO_RDY_MASK 0x0
2693 2188
2694/* Bit masks for SDH_FIFO_CNT */ 2189/* Bit masks for SDH_FIFO_CNT */
2695 2190
@@ -2698,73 +2193,47 @@
2698/* Bit masks for SDH_E_STATUS */ 2193/* Bit masks for SDH_E_STATUS */
2699 2194
2700#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 2195#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2701#define nSDIO_INT_DET 0x0
2702#define SD_CARD_DET 0x10 /* SD Card Detect */ 2196#define SD_CARD_DET 0x10 /* SD Card Detect */
2703#define nSD_CARD_DET 0x0
2704 2197
2705/* Bit masks for SDH_E_MASK */ 2198/* Bit masks for SDH_E_MASK */
2706 2199
2707#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 2200#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2708#define nSDIO_MSK 0x0
2709#define SCD_MSK 0x40 /* Mask Card Detect */ 2201#define SCD_MSK 0x40 /* Mask Card Detect */
2710#define nSCD_MSK 0x0
2711 2202
2712/* Bit masks for SDH_CFG */ 2203/* Bit masks for SDH_CFG */
2713 2204
2714#define CLKS_EN 0x1 /* Clocks Enable */ 2205#define CLKS_EN 0x1 /* Clocks Enable */
2715#define nCLKS_EN 0x0
2716#define SD4E 0x4 /* SDIO 4-Bit Enable */ 2206#define SD4E 0x4 /* SDIO 4-Bit Enable */
2717#define nSD4E 0x0
2718#define MWE 0x8 /* Moving Window Enable */ 2207#define MWE 0x8 /* Moving Window Enable */
2719#define nMWE 0x0
2720#define SD_RST 0x10 /* SDMMC Reset */ 2208#define SD_RST 0x10 /* SDMMC Reset */
2721#define nSD_RST 0x0
2722#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 2209#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2723#define nPUP_SDDAT 0x0
2724#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 2210#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2725#define nPUP_SDDAT3 0x0
2726#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 2211#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2727#define nPD_SDDAT3 0x0
2728 2212
2729/* Bit masks for SDH_RD_WAIT_EN */ 2213/* Bit masks for SDH_RD_WAIT_EN */
2730 2214
2731#define RWR 0x1 /* Read Wait Request */ 2215#define RWR 0x1 /* Read Wait Request */
2732#define nRWR 0x0
2733 2216
2734/* Bit masks for ATAPI_CONTROL */ 2217/* Bit masks for ATAPI_CONTROL */
2735 2218
2736#define PIO_START 0x1 /* Start PIO/Reg Op */ 2219#define PIO_START 0x1 /* Start PIO/Reg Op */
2737#define nPIO_START 0x0
2738#define MULTI_START 0x2 /* Start Multi-DMA Op */ 2220#define MULTI_START 0x2 /* Start Multi-DMA Op */
2739#define nMULTI_START 0x0
2740#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 2221#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2741#define nULTRA_START 0x0
2742#define XFER_DIR 0x8 /* Transfer Direction */ 2222#define XFER_DIR 0x8 /* Transfer Direction */
2743#define nXFER_DIR 0x0
2744#define IORDY_EN 0x10 /* IORDY Enable */ 2223#define IORDY_EN 0x10 /* IORDY Enable */
2745#define nIORDY_EN 0x0
2746#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 2224#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2747#define nFIFO_FLUSH 0x0
2748#define SOFT_RST 0x40 /* Soft Reset */ 2225#define SOFT_RST 0x40 /* Soft Reset */
2749#define nSOFT_RST 0x0
2750#define DEV_RST 0x80 /* Device Reset */ 2226#define DEV_RST 0x80 /* Device Reset */
2751#define nDEV_RST 0x0
2752#define TFRCNT_RST 0x100 /* Trans Count Reset */ 2227#define TFRCNT_RST 0x100 /* Trans Count Reset */
2753#define nTFRCNT_RST 0x0
2754#define END_ON_TERM 0x200 /* End/Terminate Select */ 2228#define END_ON_TERM 0x200 /* End/Terminate Select */
2755#define nEND_ON_TERM 0x0
2756#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 2229#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2757#define nPIO_USE_DMA 0x0
2758#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 2230#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2759 2231
2760/* Bit masks for ATAPI_STATUS */ 2232/* Bit masks for ATAPI_STATUS */
2761 2233
2762#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 2234#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2763#define nPIO_XFER_ON 0x0
2764#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 2235#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2765#define nMULTI_XFER_ON 0x0
2766#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 2236#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2767#define nULTRA_XFER_ON 0x0
2768#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 2237#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2769 2238
2770/* Bit masks for ATAPI_DEV_ADDR */ 2239/* Bit masks for ATAPI_DEV_ADDR */
@@ -2774,66 +2243,39 @@
2774/* Bit masks for ATAPI_INT_MASK */ 2243/* Bit masks for ATAPI_INT_MASK */
2775 2244
2776#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 2245#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2777#define nATAPI_DEV_INT_MASK 0x0
2778#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 2246#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2779#define nPIO_DONE_MASK 0x0
2780#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 2247#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2781#define nMULTI_DONE_MASK 0x0
2782#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 2248#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2783#define nUDMAIN_DONE_MASK 0x0
2784#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 2249#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2785#define nUDMAOUT_DONE_MASK 0x0
2786#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 2250#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2787#define nHOST_TERM_XFER_MASK 0x0
2788#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 2251#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2789#define nMULTI_TERM_MASK 0x0
2790#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 2252#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2791#define nUDMAIN_TERM_MASK 0x0
2792#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 2253#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2793#define nUDMAOUT_TERM_MASK 0x0
2794 2254
2795/* Bit masks for ATAPI_INT_STATUS */ 2255/* Bit masks for ATAPI_INT_STATUS */
2796 2256
2797#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 2257#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2798#define nATAPI_DEV_INT 0x0
2799#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 2258#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2800#define nPIO_DONE_INT 0x0
2801#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 2259#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2802#define nMULTI_DONE_INT 0x0
2803#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 2260#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2804#define nUDMAIN_DONE_INT 0x0
2805#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 2261#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2806#define nUDMAOUT_DONE_INT 0x0
2807#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 2262#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2808#define nHOST_TERM_XFER_INT 0x0
2809#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 2263#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2810#define nMULTI_TERM_INT 0x0
2811#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 2264#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2812#define nUDMAIN_TERM_INT 0x0
2813#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 2265#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2814#define nUDMAOUT_TERM_INT 0x0
2815 2266
2816/* Bit masks for ATAPI_LINE_STATUS */ 2267/* Bit masks for ATAPI_LINE_STATUS */
2817 2268
2818#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 2269#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2819#define nATAPI_INTR 0x0
2820#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 2270#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2821#define nATAPI_DASP 0x0
2822#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 2271#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2823#define nATAPI_CS0N 0x0
2824#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 2272#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2825#define nATAPI_CS1N 0x0
2826#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 2273#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2827#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 2274#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2828#define nATAPI_DMAREQ 0x0
2829#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 2275#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2830#define nATAPI_DMAACKN 0x0
2831#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 2276#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2832#define nATAPI_DIOWN 0x0
2833#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 2277#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2834#define nATAPI_DIORN 0x0
2835#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 2278#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2836#define nATAPI_IORDY 0x0
2837 2279
2838/* Bit masks for ATAPI_SM_STATE */ 2280/* Bit masks for ATAPI_SM_STATE */
2839 2281
@@ -2845,7 +2287,6 @@
2845/* Bit masks for ATAPI_TERMINATE */ 2287/* Bit masks for ATAPI_TERMINATE */
2846 2288
2847#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 2289#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2848#define nATAPI_HOST_TERM 0x0
2849 2290
2850/* Bit masks for ATAPI_REG_TIM_0 */ 2291/* Bit masks for ATAPI_REG_TIM_0 */
2851 2292
@@ -2900,41 +2341,26 @@
2900/* Bit masks for TIMER_ENABLE1 */ 2341/* Bit masks for TIMER_ENABLE1 */
2901 2342
2902#define TIMEN8 0x1 /* Timer 8 Enable */ 2343#define TIMEN8 0x1 /* Timer 8 Enable */
2903#define nTIMEN8 0x0
2904#define TIMEN9 0x2 /* Timer 9 Enable */ 2344#define TIMEN9 0x2 /* Timer 9 Enable */
2905#define nTIMEN9 0x0
2906#define TIMEN10 0x4 /* Timer 10 Enable */ 2345#define TIMEN10 0x4 /* Timer 10 Enable */
2907#define nTIMEN10 0x0
2908 2346
2909/* Bit masks for TIMER_DISABLE1 */ 2347/* Bit masks for TIMER_DISABLE1 */
2910 2348
2911#define TIMDIS8 0x1 /* Timer 8 Disable */ 2349#define TIMDIS8 0x1 /* Timer 8 Disable */
2912#define nTIMDIS8 0x0
2913#define TIMDIS9 0x2 /* Timer 9 Disable */ 2350#define TIMDIS9 0x2 /* Timer 9 Disable */
2914#define nTIMDIS9 0x0
2915#define TIMDIS10 0x4 /* Timer 10 Disable */ 2351#define TIMDIS10 0x4 /* Timer 10 Disable */
2916#define nTIMDIS10 0x0
2917 2352
2918/* Bit masks for TIMER_STATUS1 */ 2353/* Bit masks for TIMER_STATUS1 */
2919 2354
2920#define TIMIL8 0x1 /* Timer 8 Interrupt */ 2355#define TIMIL8 0x1 /* Timer 8 Interrupt */
2921#define nTIMIL8 0x0
2922#define TIMIL9 0x2 /* Timer 9 Interrupt */ 2356#define TIMIL9 0x2 /* Timer 9 Interrupt */
2923#define nTIMIL9 0x0
2924#define TIMIL10 0x4 /* Timer 10 Interrupt */ 2357#define TIMIL10 0x4 /* Timer 10 Interrupt */
2925#define nTIMIL10 0x0
2926#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 2358#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2927#define nTOVF_ERR8 0x0
2928#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 2359#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2929#define nTOVF_ERR9 0x0
2930#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 2360#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2931#define nTOVF_ERR10 0x0
2932#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 2361#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2933#define nTRUN8 0x0
2934#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 2362#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2935#define nTRUN9 0x0
2936#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 2363#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2937#define nTRUN10 0x0
2938 2364
2939/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 2365/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2940 2366
@@ -2945,131 +2371,77 @@
2945/* Bit masks for USB_POWER */ 2371/* Bit masks for USB_POWER */
2946 2372
2947#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 2373#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2948#define nENABLE_SUSPENDM 0x0
2949#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 2374#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2950#define nSUSPEND_MODE 0x0
2951#define RESUME_MODE 0x4 /* DMA Mode */ 2375#define RESUME_MODE 0x4 /* DMA Mode */
2952#define nRESUME_MODE 0x0
2953#define RESET 0x8 /* Reset indicator */ 2376#define RESET 0x8 /* Reset indicator */
2954#define nRESET 0x0
2955#define HS_MODE 0x10 /* High Speed mode indicator */ 2377#define HS_MODE 0x10 /* High Speed mode indicator */
2956#define nHS_MODE 0x0
2957#define HS_ENABLE 0x20 /* high Speed Enable */ 2378#define HS_ENABLE 0x20 /* high Speed Enable */
2958#define nHS_ENABLE 0x0
2959#define SOFT_CONN 0x40 /* Soft connect */ 2379#define SOFT_CONN 0x40 /* Soft connect */
2960#define nSOFT_CONN 0x0
2961#define ISO_UPDATE 0x80 /* Isochronous update */ 2380#define ISO_UPDATE 0x80 /* Isochronous update */
2962#define nISO_UPDATE 0x0
2963 2381
2964/* Bit masks for USB_INTRTX */ 2382/* Bit masks for USB_INTRTX */
2965 2383
2966#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 2384#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2967#define nEP0_TX 0x0
2968#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 2385#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2969#define nEP1_TX 0x0
2970#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 2386#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2971#define nEP2_TX 0x0
2972#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 2387#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2973#define nEP3_TX 0x0
2974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 2388#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2975#define nEP4_TX 0x0
2976#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 2389#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2977#define nEP5_TX 0x0
2978#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 2390#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2979#define nEP6_TX 0x0
2980#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 2391#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2981#define nEP7_TX 0x0
2982 2392
2983/* Bit masks for USB_INTRRX */ 2393/* Bit masks for USB_INTRRX */
2984 2394
2985#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 2395#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2986#define nEP1_RX 0x0
2987#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 2396#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2988#define nEP2_RX 0x0
2989#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 2397#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2990#define nEP3_RX 0x0
2991#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 2398#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2992#define nEP4_RX 0x0
2993#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 2399#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2994#define nEP5_RX 0x0
2995#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 2400#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2996#define nEP6_RX 0x0
2997#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 2401#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2998#define nEP7_RX 0x0
2999 2402
3000/* Bit masks for USB_INTRTXE */ 2403/* Bit masks for USB_INTRTXE */
3001 2404
3002#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 2405#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
3003#define nEP0_TX_E 0x0
3004#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 2406#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
3005#define nEP1_TX_E 0x0
3006#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 2407#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
3007#define nEP2_TX_E 0x0
3008#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 2408#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
3009#define nEP3_TX_E 0x0
3010#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 2409#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
3011#define nEP4_TX_E 0x0
3012#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 2410#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
3013#define nEP5_TX_E 0x0
3014#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 2411#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
3015#define nEP6_TX_E 0x0
3016#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 2412#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
3017#define nEP7_TX_E 0x0
3018 2413
3019/* Bit masks for USB_INTRRXE */ 2414/* Bit masks for USB_INTRRXE */
3020 2415
3021#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 2416#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
3022#define nEP1_RX_E 0x0
3023#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 2417#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
3024#define nEP2_RX_E 0x0
3025#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 2418#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
3026#define nEP3_RX_E 0x0
3027#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 2419#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
3028#define nEP4_RX_E 0x0
3029#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 2420#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
3030#define nEP5_RX_E 0x0
3031#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 2421#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
3032#define nEP6_RX_E 0x0
3033#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 2422#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
3034#define nEP7_RX_E 0x0
3035 2423
3036/* Bit masks for USB_INTRUSB */ 2424/* Bit masks for USB_INTRUSB */
3037 2425
3038#define SUSPEND_B 0x1 /* Suspend indicator */ 2426#define SUSPEND_B 0x1 /* Suspend indicator */
3039#define nSUSPEND_B 0x0
3040#define RESUME_B 0x2 /* Resume indicator */ 2427#define RESUME_B 0x2 /* Resume indicator */
3041#define nRESUME_B 0x0
3042#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 2428#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
3043#define nRESET_OR_BABLE_B 0x0
3044#define SOF_B 0x8 /* Start of frame */ 2429#define SOF_B 0x8 /* Start of frame */
3045#define nSOF_B 0x0
3046#define CONN_B 0x10 /* Connection indicator */ 2430#define CONN_B 0x10 /* Connection indicator */
3047#define nCONN_B 0x0
3048#define DISCON_B 0x20 /* Disconnect indicator */ 2431#define DISCON_B 0x20 /* Disconnect indicator */
3049#define nDISCON_B 0x0
3050#define SESSION_REQ_B 0x40 /* Session Request */ 2432#define SESSION_REQ_B 0x40 /* Session Request */
3051#define nSESSION_REQ_B 0x0
3052#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 2433#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
3053#define nVBUS_ERROR_B 0x0
3054 2434
3055/* Bit masks for USB_INTRUSBE */ 2435/* Bit masks for USB_INTRUSBE */
3056 2436
3057#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 2437#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
3058#define nSUSPEND_BE 0x0
3059#define RESUME_BE 0x2 /* Resume indicator int enable */ 2438#define RESUME_BE 0x2 /* Resume indicator int enable */
3060#define nRESUME_BE 0x0
3061#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 2439#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
3062#define nRESET_OR_BABLE_BE 0x0
3063#define SOF_BE 0x8 /* Start of frame int enable */ 2440#define SOF_BE 0x8 /* Start of frame int enable */
3064#define nSOF_BE 0x0
3065#define CONN_BE 0x10 /* Connection indicator int enable */ 2441#define CONN_BE 0x10 /* Connection indicator int enable */
3066#define nCONN_BE 0x0
3067#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 2442#define DISCON_BE 0x20 /* Disconnect indicator int enable */
3068#define nDISCON_BE 0x0
3069#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 2443#define SESSION_REQ_BE 0x40 /* Session Request int enable */
3070#define nSESSION_REQ_BE 0x0
3071#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 2444#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
3072#define nVBUS_ERROR_BE 0x0
3073 2445
3074/* Bit masks for USB_FRAME */ 2446/* Bit masks for USB_FRAME */
3075 2447
@@ -3082,117 +2454,67 @@
3082/* Bit masks for USB_GLOBAL_CTL */ 2454/* Bit masks for USB_GLOBAL_CTL */
3083 2455
3084#define GLOBAL_ENA 0x1 /* enables USB module */ 2456#define GLOBAL_ENA 0x1 /* enables USB module */
3085#define nGLOBAL_ENA 0x0
3086#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 2457#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
3087#define nEP1_TX_ENA 0x0
3088#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 2458#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
3089#define nEP2_TX_ENA 0x0
3090#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 2459#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
3091#define nEP3_TX_ENA 0x0
3092#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 2460#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
3093#define nEP4_TX_ENA 0x0
3094#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 2461#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
3095#define nEP5_TX_ENA 0x0
3096#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 2462#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
3097#define nEP6_TX_ENA 0x0
3098#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 2463#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
3099#define nEP7_TX_ENA 0x0
3100#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 2464#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
3101#define nEP1_RX_ENA 0x0
3102#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 2465#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
3103#define nEP2_RX_ENA 0x0
3104#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 2466#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
3105#define nEP3_RX_ENA 0x0
3106#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 2467#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
3107#define nEP4_RX_ENA 0x0
3108#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 2468#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
3109#define nEP5_RX_ENA 0x0
3110#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 2469#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
3111#define nEP6_RX_ENA 0x0
3112#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 2470#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
3113#define nEP7_RX_ENA 0x0
3114 2471
3115/* Bit masks for USB_OTG_DEV_CTL */ 2472/* Bit masks for USB_OTG_DEV_CTL */
3116 2473
3117#define SESSION 0x1 /* session indicator */ 2474#define SESSION 0x1 /* session indicator */
3118#define nSESSION 0x0
3119#define HOST_REQ 0x2 /* Host negotiation request */ 2475#define HOST_REQ 0x2 /* Host negotiation request */
3120#define nHOST_REQ 0x0
3121#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 2476#define HOST_MODE 0x4 /* indicates USBDRC is a host */
3122#define nHOST_MODE 0x0
3123#define VBUS0 0x8 /* Vbus level indicator[0] */ 2477#define VBUS0 0x8 /* Vbus level indicator[0] */
3124#define nVBUS0 0x0
3125#define VBUS1 0x10 /* Vbus level indicator[1] */ 2478#define VBUS1 0x10 /* Vbus level indicator[1] */
3126#define nVBUS1 0x0
3127#define LSDEV 0x20 /* Low-speed indicator */ 2479#define LSDEV 0x20 /* Low-speed indicator */
3128#define nLSDEV 0x0
3129#define FSDEV 0x40 /* Full or High-speed indicator */ 2480#define FSDEV 0x40 /* Full or High-speed indicator */
3130#define nFSDEV 0x0
3131#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 2481#define B_DEVICE 0x80 /* A' or 'B' device indicator */
3132#define nB_DEVICE 0x0
3133 2482
3134/* Bit masks for USB_OTG_VBUS_IRQ */ 2483/* Bit masks for USB_OTG_VBUS_IRQ */
3135 2484
3136#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 2485#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
3137#define nDRIVE_VBUS_ON 0x0
3138#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 2486#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
3139#define nDRIVE_VBUS_OFF 0x0
3140#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 2487#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
3141#define nCHRG_VBUS_START 0x0
3142#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 2488#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
3143#define nCHRG_VBUS_END 0x0
3144#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 2489#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
3145#define nDISCHRG_VBUS_START 0x0
3146#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 2490#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
3147#define nDISCHRG_VBUS_END 0x0
3148 2491
3149/* Bit masks for USB_OTG_VBUS_MASK */ 2492/* Bit masks for USB_OTG_VBUS_MASK */
3150 2493
3151#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 2494#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
3152#define nDRIVE_VBUS_ON_ENA 0x0
3153#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 2495#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
3154#define nDRIVE_VBUS_OFF_ENA 0x0
3155#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 2496#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
3156#define nCHRG_VBUS_START_ENA 0x0
3157#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 2497#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
3158#define nCHRG_VBUS_END_ENA 0x0
3159#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 2498#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
3160#define nDISCHRG_VBUS_START_ENA 0x0
3161#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 2499#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
3162#define nDISCHRG_VBUS_END_ENA 0x0
3163 2500
3164/* Bit masks for USB_CSR0 */ 2501/* Bit masks for USB_CSR0 */
3165 2502
3166#define RXPKTRDY 0x1 /* data packet receive indicator */ 2503#define RXPKTRDY 0x1 /* data packet receive indicator */
3167#define nRXPKTRDY 0x0
3168#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 2504#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
3169#define nTXPKTRDY 0x0
3170#define STALL_SENT 0x4 /* STALL handshake sent */ 2505#define STALL_SENT 0x4 /* STALL handshake sent */
3171#define nSTALL_SENT 0x0
3172#define DATAEND 0x8 /* Data end indicator */ 2506#define DATAEND 0x8 /* Data end indicator */
3173#define nDATAEND 0x0
3174#define SETUPEND 0x10 /* Setup end */ 2507#define SETUPEND 0x10 /* Setup end */
3175#define nSETUPEND 0x0
3176#define SENDSTALL 0x20 /* Send STALL handshake */ 2508#define SENDSTALL 0x20 /* Send STALL handshake */
3177#define nSENDSTALL 0x0
3178#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 2509#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
3179#define nSERVICED_RXPKTRDY 0x0
3180#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 2510#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
3181#define nSERVICED_SETUPEND 0x0
3182#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 2511#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
3183#define nFLUSHFIFO 0x0
3184#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 2512#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
3185#define nSTALL_RECEIVED_H 0x0
3186#define SETUPPKT_H 0x8 /* send Setup token host mode */ 2513#define SETUPPKT_H 0x8 /* send Setup token host mode */
3187#define nSETUPPKT_H 0x0
3188#define ERROR_H 0x10 /* timeout error indicator host mode */ 2514#define ERROR_H 0x10 /* timeout error indicator host mode */
3189#define nERROR_H 0x0
3190#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 2515#define REQPKT_H 0x20 /* Request an IN transaction host mode */
3191#define nREQPKT_H 0x0
3192#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 2516#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
3193#define nSTATUSPKT_H 0x0
3194#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 2517#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
3195#define nNAK_TIMEOUT_H 0x0
3196 2518
3197/* Bit masks for USB_COUNT0 */ 2519/* Bit masks for USB_COUNT0 */
3198 2520
@@ -3213,37 +2535,21 @@
3213/* Bit masks for USB_TXCSR */ 2535/* Bit masks for USB_TXCSR */
3214 2536
3215#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 2537#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
3216#define nTXPKTRDY_T 0x0
3217#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 2538#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
3218#define nFIFO_NOT_EMPTY_T 0x0
3219#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 2539#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
3220#define nUNDERRUN_T 0x0
3221#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 2540#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
3222#define nFLUSHFIFO_T 0x0
3223#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 2541#define STALL_SEND_T 0x10 /* issue a Stall handshake */
3224#define nSTALL_SEND_T 0x0
3225#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 2542#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
3226#define nSTALL_SENT_T 0x0
3227#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 2543#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
3228#define nCLEAR_DATATOGGLE_T 0x0
3229#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 2544#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
3230#define nINCOMPTX_T 0x0
3231#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 2545#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
3232#define nDMAREQMODE_T 0x0
3233#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 2546#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
3234#define nFORCE_DATATOGGLE_T 0x0
3235#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 2547#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
3236#define nDMAREQ_ENA_T 0x0
3237#define ISO_T 0x4000 /* enable Isochronous transfers */ 2548#define ISO_T 0x4000 /* enable Isochronous transfers */
3238#define nISO_T 0x0
3239#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 2549#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
3240#define nAUTOSET_T 0x0
3241#define ERROR_TH 0x4 /* error condition host mode */ 2550#define ERROR_TH 0x4 /* error condition host mode */
3242#define nERROR_TH 0x0
3243#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 2551#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
3244#define nSTALL_RECEIVED_TH 0x0
3245#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 2552#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
3246#define nNAK_TIMEOUT_TH 0x0
3247 2553
3248/* Bit masks for USB_TXCOUNT */ 2554/* Bit masks for USB_TXCOUNT */
3249 2555
@@ -3252,45 +2558,25 @@
3252/* Bit masks for USB_RXCSR */ 2558/* Bit masks for USB_RXCSR */
3253 2559
3254#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 2560#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
3255#define nRXPKTRDY_R 0x0
3256#define FIFO_FULL_R 0x2 /* FIFO not empty */ 2561#define FIFO_FULL_R 0x2 /* FIFO not empty */
3257#define nFIFO_FULL_R 0x0
3258#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 2562#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
3259#define nOVERRUN_R 0x0
3260#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 2563#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
3261#define nDATAERROR_R 0x0
3262#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 2564#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
3263#define nFLUSHFIFO_R 0x0
3264#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 2565#define STALL_SEND_R 0x20 /* issue a Stall handshake */
3265#define nSTALL_SEND_R 0x0
3266#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 2566#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
3267#define nSTALL_SENT_R 0x0
3268#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 2567#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
3269#define nCLEAR_DATATOGGLE_R 0x0
3270#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 2568#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
3271#define nINCOMPRX_R 0x0
3272#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 2569#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
3273#define nDMAREQMODE_R 0x0
3274#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 2570#define DISNYET_R 0x1000 /* disable Nyet handshakes */
3275#define nDISNYET_R 0x0
3276#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 2571#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
3277#define nDMAREQ_ENA_R 0x0
3278#define ISO_R 0x4000 /* enable Isochronous transfers */ 2572#define ISO_R 0x4000 /* enable Isochronous transfers */
3279#define nISO_R 0x0
3280#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 2573#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
3281#define nAUTOCLEAR_R 0x0
3282#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 2574#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
3283#define nERROR_RH 0x0
3284#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 2575#define REQPKT_RH 0x20 /* request an IN transaction host mode */
3285#define nREQPKT_RH 0x0
3286#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 2576#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
3287#define nSTALL_RECEIVED_RH 0x0
3288#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 2577#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
3289#define nINCOMPRX_RH 0x0
3290#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 2578#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
3291#define nDMAREQMODE_RH 0x0
3292#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 2579#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
3293#define nAUTOREQ_RH 0x0
3294 2580
3295/* Bit masks for USB_RXCOUNT */ 2581/* Bit masks for USB_RXCOUNT */
3296 2582
@@ -3317,35 +2603,22 @@
3317/* Bit masks for USB_DMA_INTERRUPT */ 2603/* Bit masks for USB_DMA_INTERRUPT */
3318 2604
3319#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 2605#define DMA0_INT 0x1 /* DMA0 pending interrupt */
3320#define nDMA0_INT 0x0
3321#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 2606#define DMA1_INT 0x2 /* DMA1 pending interrupt */
3322#define nDMA1_INT 0x0
3323#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 2607#define DMA2_INT 0x4 /* DMA2 pending interrupt */
3324#define nDMA2_INT 0x0
3325#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 2608#define DMA3_INT 0x8 /* DMA3 pending interrupt */
3326#define nDMA3_INT 0x0
3327#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 2609#define DMA4_INT 0x10 /* DMA4 pending interrupt */
3328#define nDMA4_INT 0x0
3329#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 2610#define DMA5_INT 0x20 /* DMA5 pending interrupt */
3330#define nDMA5_INT 0x0
3331#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 2611#define DMA6_INT 0x40 /* DMA6 pending interrupt */
3332#define nDMA6_INT 0x0
3333#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 2612#define DMA7_INT 0x80 /* DMA7 pending interrupt */
3334#define nDMA7_INT 0x0
3335 2613
3336/* Bit masks for USB_DMAxCONTROL */ 2614/* Bit masks for USB_DMAxCONTROL */
3337 2615
3338#define DMA_ENA 0x1 /* DMA enable */ 2616#define DMA_ENA 0x1 /* DMA enable */
3339#define nDMA_ENA 0x0
3340#define DIRECTION 0x2 /* direction of DMA transfer */ 2617#define DIRECTION 0x2 /* direction of DMA transfer */
3341#define nDIRECTION 0x0
3342#define MODE 0x4 /* DMA Bus error */ 2618#define MODE 0x4 /* DMA Bus error */
3343#define nMODE 0x0
3344#define INT_ENA 0x8 /* Interrupt enable */ 2619#define INT_ENA 0x8 /* Interrupt enable */
3345#define nINT_ENA 0x0
3346#define EPNUM 0xf0 /* EP number */ 2620#define EPNUM 0xf0 /* EP number */
3347#define BUSERROR 0x100 /* DMA Bus error */ 2621#define BUSERROR 0x100 /* DMA Bus error */
3348#define nBUSERROR 0x0
3349 2622
3350/* Bit masks for USB_DMAxADDRHIGH */ 2623/* Bit masks for USB_DMAxADDRHIGH */
3351 2624
@@ -3366,26 +2639,16 @@
3366/* Bit masks for HMDMAx_CONTROL */ 2639/* Bit masks for HMDMAx_CONTROL */
3367 2640
3368#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 2641#define HMDMAEN 0x1 /* Handshake MDMA Enable */
3369#define nHMDMAEN 0x0
3370#define REP 0x2 /* Handshake MDMA Request Polarity */ 2642#define REP 0x2 /* Handshake MDMA Request Polarity */
3371#define nREP 0x0
3372#define UTE 0x8 /* Urgency Threshold Enable */ 2643#define UTE 0x8 /* Urgency Threshold Enable */
3373#define nUTE 0x0
3374#define OIE 0x10 /* Overflow Interrupt Enable */ 2644#define OIE 0x10 /* Overflow Interrupt Enable */
3375#define nOIE 0x0
3376#define BDIE 0x20 /* Block Done Interrupt Enable */ 2645#define BDIE 0x20 /* Block Done Interrupt Enable */
3377#define nBDIE 0x0
3378#define MBDI 0x40 /* Mask Block Done Interrupt */ 2646#define MBDI 0x40 /* Mask Block Done Interrupt */
3379#define nMBDI 0x0
3380#define DRQ 0x300 /* Handshake MDMA Request Type */ 2647#define DRQ 0x300 /* Handshake MDMA Request Type */
3381#define RBC 0x1000 /* Force Reload of BCOUNT */ 2648#define RBC 0x1000 /* Force Reload of BCOUNT */
3382#define nRBC 0x0
3383#define PS 0x2000 /* Pin Status */ 2649#define PS 0x2000 /* Pin Status */
3384#define nPS 0x0
3385#define OI 0x4000 /* Overflow Interrupt Generated */ 2650#define OI 0x4000 /* Overflow Interrupt Generated */
3386#define nOI 0x0
3387#define BDI 0x8000 /* Block Done Interrupt Generated */ 2651#define BDI 0x8000 /* Block Done Interrupt Generated */
3388#define nBDI 0x0
3389 2652
3390/* ******************************************* */ 2653/* ******************************************* */
3391/* MULTI BIT MACRO ENUMERATIONS */ 2654/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index a1b200fe6a1f..2381ac50a2cf 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -46,7 +46,7 @@
46 46
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ 47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48 48
49#define CHIPID 0xffc00014 49#define CHIPID 0xffc00014
50 50
51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ 51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
52 52
@@ -1512,231 +1512,144 @@
1512/* and MULTI BIT READ MACROS */ 1512/* and MULTI BIT READ MACROS */
1513/* ********************************************************** */ 1513/* ********************************************************** */
1514 1514
1515/* SIC_IMASK Masks */
1516#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1517#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1518#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1519#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1520
1521/* SIC_IWR Masks */
1522#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1523#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1524#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
1525#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
1526
1515/* Bit masks for SIC_IAR0 */ 1527/* Bit masks for SIC_IAR0 */
1516 1528
1517#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ 1529#define PLL_WAKEUP 0x1 /* PLL Wakeup */
1518#define nIRQ_PLL_WAKEUP 0x0
1519 1530
1520/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ 1531/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1521 1532
1522#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ 1533#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
1523#define nIRQ_DMA0_ERR 0x0 1534#define EPPI0_ERR 0x4 /* EPPI0 Error */
1524#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ 1535#define SPORT0_ERR 0x8 /* SPORT0 Error */
1525#define nIRQ_EPPI0_ERR 0x0 1536#define SPORT1_ERR 0x10 /* SPORT1 Error */
1526#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ 1537#define SPI0_ERR 0x20 /* SPI0 Error */
1527#define nIRQ_SPORT0_ERR 0x0 1538#define UART0_ERR 0x40 /* UART0 Error */
1528#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ 1539#define RTC 0x80 /* Real-Time Clock */
1529#define nIRQ_SPORT1_ERR 0x0 1540#define DMA12 0x100 /* DMA Channel 12 */
1530#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ 1541#define DMA0 0x200 /* DMA Channel 0 */
1531#define nIRQ_SPI0_ERR 0x0 1542#define DMA1 0x400 /* DMA Channel 1 */
1532#define IRQ_UART0_ERR 0x40 /* UART0 Error */ 1543#define DMA2 0x800 /* DMA Channel 2 */
1533#define nIRQ_UART0_ERR 0x0 1544#define DMA3 0x1000 /* DMA Channel 3 */
1534#define IRQ_RTC 0x80 /* Real-Time Clock */ 1545#define DMA4 0x2000 /* DMA Channel 4 */
1535#define nIRQ_RTC 0x0 1546#define DMA6 0x4000 /* DMA Channel 6 */
1536#define IRQ_DMA12 0x100 /* DMA Channel 12 */ 1547#define DMA7 0x8000 /* DMA Channel 7 */
1537#define nIRQ_DMA12 0x0 1548#define PINT0 0x80000 /* Pin Interrupt 0 */
1538#define IRQ_DMA0 0x200 /* DMA Channel 0 */ 1549#define PINT1 0x100000 /* Pin Interrupt 1 */
1539#define nIRQ_DMA0 0x0 1550#define MDMA0 0x200000 /* Memory DMA Stream 0 */
1540#define IRQ_DMA1 0x400 /* DMA Channel 1 */ 1551#define MDMA1 0x400000 /* Memory DMA Stream 1 */
1541#define nIRQ_DMA1 0x0 1552#define WDOG 0x800000 /* Watchdog Timer */
1542#define IRQ_DMA2 0x800 /* DMA Channel 2 */ 1553#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1543#define nIRQ_DMA2 0x0 1554#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
1544#define IRQ_DMA3 0x1000 /* DMA Channel 3 */ 1555#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
1545#define nIRQ_DMA3 0x0 1556#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1546#define IRQ_DMA4 0x2000 /* DMA Channel 4 */ 1557#define SPI1_ERR 0x10000000 /* SPI1 Error */
1547#define nIRQ_DMA4 0x0 1558#define SPI2_ERR 0x20000000 /* SPI2 Error */
1548#define IRQ_DMA6 0x4000 /* DMA Channel 6 */ 1559#define UART1_ERR 0x40000000 /* UART1 Error */
1549#define nIRQ_DMA6 0x0 1560#define UART2_ERR 0x80000000 /* UART2 Error */
1550#define IRQ_DMA7 0x8000 /* DMA Channel 7 */
1551#define nIRQ_DMA7 0x0
1552#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */
1553#define nIRQ_PINT0 0x0
1554#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */
1555#define nIRQ_PINT1 0x0
1556#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */
1557#define nIRQ_MDMA0 0x0
1558#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */
1559#define nIRQ_MDMA1 0x0
1560#define IRQ_WDOG 0x800000 /* Watchdog Timer */
1561#define nIRQ_WDOG 0x0
1562#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1563#define nIRQ_DMA1_ERR 0x0
1564#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */
1565#define nIRQ_SPORT2_ERR 0x0
1566#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */
1567#define nIRQ_SPORT3_ERR 0x0
1568#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1569#define nIRQ_MXVR_SD 0x0
1570#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */
1571#define nIRQ_SPI1_ERR 0x0
1572#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */
1573#define nIRQ_SPI2_ERR 0x0
1574#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */
1575#define nIRQ_UART1_ERR 0x0
1576#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */
1577#define nIRQ_UART2_ERR 0x0
1578 1561
1579/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ 1562/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1580 1563
1581#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ 1564#define CAN0_ERR 0x1 /* CAN0 Error */
1582#define nIRQ_CAN0_ERR 0x0 1565#define DMA18 0x2 /* DMA Channel 18 */
1583#define IRQ_DMA18 0x2 /* DMA Channel 18 */ 1566#define DMA19 0x4 /* DMA Channel 19 */
1584#define nIRQ_DMA18 0x0 1567#define DMA20 0x8 /* DMA Channel 20 */
1585#define IRQ_DMA19 0x4 /* DMA Channel 19 */ 1568#define DMA21 0x10 /* DMA Channel 21 */
1586#define nIRQ_DMA19 0x0 1569#define DMA13 0x20 /* DMA Channel 13 */
1587#define IRQ_DMA20 0x8 /* DMA Channel 20 */ 1570#define DMA14 0x40 /* DMA Channel 14 */
1588#define nIRQ_DMA20 0x0 1571#define DMA5 0x80 /* DMA Channel 5 */
1589#define IRQ_DMA21 0x10 /* DMA Channel 21 */ 1572#define DMA23 0x100 /* DMA Channel 23 */
1590#define nIRQ_DMA21 0x0 1573#define DMA8 0x200 /* DMA Channel 8 */
1591#define IRQ_DMA13 0x20 /* DMA Channel 13 */ 1574#define DMA9 0x400 /* DMA Channel 9 */
1592#define nIRQ_DMA13 0x0 1575#define DMA10 0x800 /* DMA Channel 10 */
1593#define IRQ_DMA14 0x40 /* DMA Channel 14 */ 1576#define DMA11 0x1000 /* DMA Channel 11 */
1594#define nIRQ_DMA14 0x0 1577#define TWI0 0x2000 /* TWI0 */
1595#define IRQ_DMA5 0x80 /* DMA Channel 5 */ 1578#define TWI1 0x4000 /* TWI1 */
1596#define nIRQ_DMA5 0x0 1579#define CAN0_RX 0x8000 /* CAN0 Receive */
1597#define IRQ_DMA23 0x100 /* DMA Channel 23 */ 1580#define CAN0_TX 0x10000 /* CAN0 Transmit */
1598#define nIRQ_DMA23 0x0 1581#define MDMA2 0x20000 /* Memory DMA Stream 0 */
1599#define IRQ_DMA8 0x200 /* DMA Channel 8 */ 1582#define MDMA3 0x40000 /* Memory DMA Stream 1 */
1600#define nIRQ_DMA8 0x0 1583#define MXVR_STAT 0x80000 /* MXVR Status */
1601#define IRQ_DMA9 0x400 /* DMA Channel 9 */ 1584#define MXVR_CM 0x100000 /* MXVR Control Message */
1602#define nIRQ_DMA9 0x0 1585#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1603#define IRQ_DMA10 0x800 /* DMA Channel 10 */ 1586#define EPPI1_ERR 0x400000 /* EPPI1 Error */
1604#define nIRQ_DMA10 0x0 1587#define EPPI2_ERR 0x800000 /* EPPI2 Error */
1605#define IRQ_DMA11 0x1000 /* DMA Channel 11 */ 1588#define UART3_ERR 0x1000000 /* UART3 Error */
1606#define nIRQ_DMA11 0x0 1589#define HOST_ERR 0x2000000 /* Host DMA Port Error */
1607#define IRQ_TWI0 0x2000 /* TWI0 */ 1590#define USB_ERR 0x4000000 /* USB Error */
1608#define nIRQ_TWI0 0x0 1591#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1609#define IRQ_TWI1 0x4000 /* TWI1 */ 1592#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1610#define nIRQ_TWI1 0x0 1593#define ATAPI_ERR 0x20000000 /* ATAPI Error */
1611#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ 1594#define CAN1_ERR 0x40000000 /* CAN1 Error */
1612#define nIRQ_CAN0_RX 0x0 1595#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1613#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ 1596#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1614#define nIRQ_CAN0_TX 0x0 1597#define DMAR0 0x80000000 /* DMAR0 Block */
1615#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ 1598#define DMAR1 0x80000000 /* DMAR1 Block */
1616#define nIRQ_MDMA2 0x0
1617#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */
1618#define nIRQ_MDMA3 0x0
1619#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */
1620#define nIRQ_MXVR_STAT 0x0
1621#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */
1622#define nIRQ_MXVR_CM 0x0
1623#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1624#define nIRQ_MXVR_AP 0x0
1625#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */
1626#define nIRQ_EPPI1_ERR 0x0
1627#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */
1628#define nIRQ_EPPI2_ERR 0x0
1629#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */
1630#define nIRQ_UART3_ERR 0x0
1631#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */
1632#define nIRQ_HOST_ERR 0x0
1633#define IRQ_USB_ERR 0x4000000 /* USB Error */
1634#define nIRQ_USB_ERR 0x0
1635#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1636#define nIRQ_PIXC_ERR 0x0
1637#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1638#define nIRQ_NFC_ERR 0x0
1639#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */
1640#define nIRQ_ATAPI_ERR 0x0
1641#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */
1642#define nIRQ_CAN1_ERR 0x0
1643#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1644#define nIRQ_DMAR0_ERR 0x0
1645#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1646#define nIRQ_DMAR1_ERR 0x0
1647#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */
1648#define nIRQ_DMAR0 0x0
1649#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */
1650#define nIRQ_DMAR1 0x0
1651 1599
1652/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ 1600/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1653 1601
1654#define IRQ_DMA15 0x1 /* DMA Channel 15 */ 1602#define DMA15 0x1 /* DMA Channel 15 */
1655#define nIRQ_DMA15 0x0 1603#define DMA16 0x2 /* DMA Channel 16 */
1656#define IRQ_DMA16 0x2 /* DMA Channel 16 */ 1604#define DMA17 0x4 /* DMA Channel 17 */
1657#define nIRQ_DMA16 0x0 1605#define DMA22 0x8 /* DMA Channel 22 */
1658#define IRQ_DMA17 0x4 /* DMA Channel 17 */ 1606#define CNT 0x10 /* Counter */
1659#define nIRQ_DMA17 0x0 1607#define KEY 0x20 /* Keypad */
1660#define IRQ_DMA22 0x8 /* DMA Channel 22 */ 1608#define CAN1_RX 0x40 /* CAN1 Receive */
1661#define nIRQ_DMA22 0x0 1609#define CAN1_TX 0x80 /* CAN1 Transmit */
1662#define IRQ_CNT 0x10 /* Counter */ 1610#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
1663#define nIRQ_CNT 0x0 1611#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
1664#define IRQ_KEY 0x20 /* Keypad */ 1612#define USB_EINT 0x400 /* USB Exception */
1665#define nIRQ_KEY 0x0 1613#define USB_INT0 0x800 /* USB Interrupt 0 */
1666#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ 1614#define USB_INT1 0x1000 /* USB Interrupt 1 */
1667#define nIRQ_CAN1_RX 0x0 1615#define USB_INT2 0x2000 /* USB Interrupt 2 */
1668#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ 1616#define USB_DMAINT 0x4000 /* USB DMA */
1669#define nIRQ_CAN1_TX 0x0 1617#define OTPSEC 0x8000 /* OTP Access Complete */
1670#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ 1618#define TIMER0 0x400000 /* Timer 0 */
1671#define nIRQ_SDH_MASK0 0x0 1619#define TIMER1 0x800000 /* Timer 1 */
1672#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ 1620#define TIMER2 0x1000000 /* Timer 2 */
1673#define nIRQ_SDH_MASK1 0x0 1621#define TIMER3 0x2000000 /* Timer 3 */
1674#define IRQ_USB_EINT 0x400 /* USB Exception */ 1622#define TIMER4 0x4000000 /* Timer 4 */
1675#define nIRQ_USB_EINT 0x0 1623#define TIMER5 0x8000000 /* Timer 5 */
1676#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ 1624#define TIMER6 0x10000000 /* Timer 6 */
1677#define nIRQ_USB_INT0 0x0 1625#define TIMER7 0x20000000 /* Timer 7 */
1678#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ 1626#define PINT2 0x40000000 /* Pin Interrupt 2 */
1679#define nIRQ_USB_INT1 0x0 1627#define PINT3 0x80000000 /* Pin Interrupt 3 */
1680#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */
1681#define nIRQ_USB_INT2 0x0
1682#define IRQ_USB_DMAINT 0x4000 /* USB DMA */
1683#define nIRQ_USB_DMAINT 0x0
1684#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */
1685#define nIRQ_OTPSEC 0x0
1686#define IRQ_TIMER0 0x400000 /* Timer 0 */
1687#define nIRQ_TIMER0 0x0
1688#define IRQ_TIMER1 0x800000 /* Timer 1 */
1689#define nIRQ_TIMER1 0x0
1690#define IRQ_TIMER2 0x1000000 /* Timer 2 */
1691#define nIRQ_TIMER2 0x0
1692#define IRQ_TIMER3 0x2000000 /* Timer 3 */
1693#define nIRQ_TIMER3 0x0
1694#define IRQ_TIMER4 0x4000000 /* Timer 4 */
1695#define nIRQ_TIMER4 0x0
1696#define IRQ_TIMER5 0x8000000 /* Timer 5 */
1697#define nIRQ_TIMER5 0x0
1698#define IRQ_TIMER6 0x10000000 /* Timer 6 */
1699#define nIRQ_TIMER6 0x0
1700#define IRQ_TIMER7 0x20000000 /* Timer 7 */
1701#define nIRQ_TIMER7 0x0
1702#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */
1703#define nIRQ_PINT2 0x0
1704#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */
1705#define nIRQ_PINT3 0x0
1706 1628
1707/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ 1629/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1708 1630
1709#define DMAEN 0x1 /* DMA Channel Enable */ 1631#define DMAEN 0x1 /* DMA Channel Enable */
1710#define nDMAEN 0x0
1711#define WNR 0x2 /* DMA Direction */ 1632#define WNR 0x2 /* DMA Direction */
1712#define nWNR 0x0 1633#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1713#define WDSIZE 0xc /* Transfer Word Size */ 1634#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1635#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1714#define DMA2D 0x10 /* DMA Mode */ 1636#define DMA2D 0x10 /* DMA Mode */
1715#define nDMA2D 0x0
1716#define RESTART 0x20 /* Work Unit Transitions */ 1637#define RESTART 0x20 /* Work Unit Transitions */
1717#define nRESTART 0x0
1718#define DI_SEL 0x40 /* Data Interrupt Timing Select */ 1638#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1719#define nDI_SEL 0x0
1720#define DI_EN 0x80 /* Data Interrupt Enable */ 1639#define DI_EN 0x80 /* Data Interrupt Enable */
1721#define nDI_EN 0x0
1722#define NDSIZE 0xf00 /* Flex Descriptor Size */ 1640#define NDSIZE 0xf00 /* Flex Descriptor Size */
1723#define DMAFLOW 0xf000 /* Next Operation */ 1641#define DMAFLOW 0xf000 /* Next Operation */
1724 1642
1725/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1643/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1726 1644
1727#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ 1645#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1728#define nDMA_DONE 0x0
1729#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ 1646#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1730#define nDMA_ERR 0x0
1731#define DFETCH 0x4 /* DMA Descriptor Fetch */ 1647#define DFETCH 0x4 /* DMA Descriptor Fetch */
1732#define nDFETCH 0x0
1733#define DMA_RUN 0x8 /* DMA Channel Running */ 1648#define DMA_RUN 0x8 /* DMA Channel Running */
1734#define nDMA_RUN 0x0
1735 1649
1736/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1650/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1737 1651
1738#define CTYPE 0x40 /* DMA Channel Type */ 1652#define CTYPE 0x40 /* DMA Channel Type */
1739#define nCTYPE 0x0
1740#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ 1653#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1741 1654
1742/* Bit masks for DMACx_TCPER */ 1655/* Bit masks for DMACx_TCPER */
@@ -1756,29 +1669,28 @@
1756/* Bit masks for DMAC1_PERIMUX */ 1669/* Bit masks for DMAC1_PERIMUX */
1757 1670
1758#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ 1671#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
1759#define nPMUXSDH 0x0
1760 1672
1761/* Bit masks for EBIU_AMGCTL */ 1673/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1674/* EBIU_AMGCTL Masks */
1675#define AMCKEN 0x0001 /* Enable CLKOUT */
1676#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1677#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1678#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1679#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1680#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1762 1681
1763#define AMCKEN 0x1 /* Async Memory Enable */
1764#define nAMCKEN 0x0
1765#define AMBEN 0xe /* Async bank enable */
1766 1682
1767/* Bit masks for EBIU_AMBCTL0 */ 1683/* Bit masks for EBIU_AMBCTL0 */
1768 1684
1769#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ 1685#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
1770#define nB0RDYEN 0x0
1771#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ 1686#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
1772#define nB0RDYPOL 0x0
1773#define B0TT 0xc /* Bank 0 transition time */ 1687#define B0TT 0xc /* Bank 0 transition time */
1774#define B0ST 0x30 /* Bank 0 Setup time */ 1688#define B0ST 0x30 /* Bank 0 Setup time */
1775#define B0HT 0xc0 /* Bank 0 Hold time */ 1689#define B0HT 0xc0 /* Bank 0 Hold time */
1776#define B0RAT 0xf00 /* Bank 0 Read access time */ 1690#define B0RAT 0xf00 /* Bank 0 Read access time */
1777#define B0WAT 0xf000 /* Bank 0 write access time */ 1691#define B0WAT 0xf000 /* Bank 0 write access time */
1778#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ 1692#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
1779#define nB1RDYEN 0x0
1780#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ 1693#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
1781#define nB1RDYPOL 0x0
1782#define B1TT 0xc0000 /* Bank 1 transition time */ 1694#define B1TT 0xc0000 /* Bank 1 transition time */
1783#define B1ST 0x300000 /* Bank 1 Setup time */ 1695#define B1ST 0x300000 /* Bank 1 Setup time */
1784#define B1HT 0xc00000 /* Bank 1 Hold time */ 1696#define B1HT 0xc00000 /* Bank 1 Hold time */
@@ -1788,18 +1700,14 @@
1788/* Bit masks for EBIU_AMBCTL1 */ 1700/* Bit masks for EBIU_AMBCTL1 */
1789 1701
1790#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ 1702#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
1791#define nB2RDYEN 0x0
1792#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ 1703#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
1793#define nB2RDYPOL 0x0
1794#define B2TT 0xc /* Bank 2 transition time */ 1704#define B2TT 0xc /* Bank 2 transition time */
1795#define B2ST 0x30 /* Bank 2 Setup time */ 1705#define B2ST 0x30 /* Bank 2 Setup time */
1796#define B2HT 0xc0 /* Bank 2 Hold time */ 1706#define B2HT 0xc0 /* Bank 2 Hold time */
1797#define B2RAT 0xf00 /* Bank 2 Read access time */ 1707#define B2RAT 0xf00 /* Bank 2 Read access time */
1798#define B2WAT 0xf000 /* Bank 2 write access time */ 1708#define B2WAT 0xf000 /* Bank 2 write access time */
1799#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ 1709#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
1800#define nB3RDYEN 0x0
1801#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ 1710#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
1802#define nB3RDYPOL 0x0
1803#define B3TT 0xc0000 /* Bank 3 transition time */ 1711#define B3TT 0xc0000 /* Bank 3 transition time */
1804#define B3ST 0x300000 /* Bank 3 Setup time */ 1712#define B3ST 0x300000 /* Bank 3 Setup time */
1805#define B3HT 0xc00000 /* Bank 3 Hold time */ 1713#define B3HT 0xc00000 /* Bank 3 Hold time */
@@ -1823,19 +1731,15 @@
1823/* Bit masks for EBIU_FCTL */ 1731/* Bit masks for EBIU_FCTL */
1824 1732
1825#define TESTSETLOCK 0x1 /* Test set lock */ 1733#define TESTSETLOCK 0x1 /* Test set lock */
1826#define nTESTSETLOCK 0x0
1827#define BCLK 0x6 /* Burst clock frequency */ 1734#define BCLK 0x6 /* Burst clock frequency */
1828#define PGWS 0x38 /* Page wait states */ 1735#define PGWS 0x38 /* Page wait states */
1829#define PGSZ 0x40 /* Page size */ 1736#define PGSZ 0x40 /* Page size */
1830#define nPGSZ 0x0
1831#define RDDL 0x380 /* Read data delay */ 1737#define RDDL 0x380 /* Read data delay */
1832 1738
1833/* Bit masks for EBIU_ARBSTAT */ 1739/* Bit masks for EBIU_ARBSTAT */
1834 1740
1835#define ARBSTAT 0x1 /* Arbitration status */ 1741#define ARBSTAT 0x1 /* Arbitration status */
1836#define nARBSTAT 0x0
1837#define BGSTAT 0x2 /* Bus grant status */ 1742#define BGSTAT 0x2 /* Bus grant status */
1838#define nBGSTAT 0x0
1839 1743
1840/* Bit masks for EBIU_DDRCTL0 */ 1744/* Bit masks for EBIU_DDRCTL0 */
1841 1745
@@ -1861,9 +1765,7 @@
1861#define BURSTLENGTH 0x7 /* Burst length */ 1765#define BURSTLENGTH 0x7 /* Burst length */
1862#define CASLATENCY 0x70 /* CAS latency */ 1766#define CASLATENCY 0x70 /* CAS latency */
1863#define DLLRESET 0x100 /* DLL Reset */ 1767#define DLLRESET 0x100 /* DLL Reset */
1864#define nDLLRESET 0x0
1865#define REGE 0x1000 /* Register mode enable */ 1768#define REGE 0x1000 /* Register mode enable */
1866#define nREGE 0x0
1867 1769
1868/* Bit masks for EBIU_DDRCTL3 */ 1770/* Bit masks for EBIU_DDRCTL3 */
1869 1771
@@ -1876,30 +1778,19 @@
1876#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ 1778#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
1877#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ 1779#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
1878#define DEB1_URGENT 0x1000 /* DEB1 Urgent */ 1780#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
1879#define nDEB1_URGENT 0x0
1880#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ 1781#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
1881#define nDEB2_URGENT 0x0
1882#define DEB3_URGENT 0x4000 /* DEB3 Urgent */ 1782#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
1883#define nDEB3_URGENT 0x0
1884 1783
1885/* Bit masks for EBIU_ERRMST */ 1784/* Bit masks for EBIU_ERRMST */
1886 1785
1887#define DEB1_ERROR 0x1 /* DEB1 Error */ 1786#define DEB1_ERROR 0x1 /* DEB1 Error */
1888#define nDEB1_ERROR 0x0
1889#define DEB2_ERROR 0x2 /* DEB2 Error */ 1787#define DEB2_ERROR 0x2 /* DEB2 Error */
1890#define nDEB2_ERROR 0x0
1891#define DEB3_ERROR 0x4 /* DEB3 Error */ 1788#define DEB3_ERROR 0x4 /* DEB3 Error */
1892#define nDEB3_ERROR 0x0
1893#define CORE_ERROR 0x8 /* Core error */ 1789#define CORE_ERROR 0x8 /* Core error */
1894#define nCORE_ERROR 0x0
1895#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ 1790#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
1896#define nDEB_MERROR 0x0
1897#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ 1791#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
1898#define nDEB2_MERROR 0x0
1899#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ 1792#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1900#define nDEB3_MERROR 0x0
1901#define CORE_MERROR 0x80 /* Core Error (2nd) */ 1793#define CORE_MERROR 0x80 /* Core Error (2nd) */
1902#define nCORE_MERROR 0x0
1903 1794
1904/* Bit masks for EBIU_ERRADD */ 1795/* Bit masks for EBIU_ERRADD */
1905 1796
@@ -1908,15 +1799,10 @@
1908/* Bit masks for EBIU_RSTCTL */ 1799/* Bit masks for EBIU_RSTCTL */
1909 1800
1910#define DDRSRESET 0x1 /* DDR soft reset */ 1801#define DDRSRESET 0x1 /* DDR soft reset */
1911#define nDDRSRESET 0x0
1912#define PFTCHSRESET 0x4 /* DDR prefetch reset */ 1802#define PFTCHSRESET 0x4 /* DDR prefetch reset */
1913#define nPFTCHSRESET 0x0
1914#define SRREQ 0x8 /* Self-refresh request */ 1803#define SRREQ 0x8 /* Self-refresh request */
1915#define nSRREQ 0x0
1916#define SRACK 0x10 /* Self-refresh acknowledge */ 1804#define SRACK 0x10 /* Self-refresh acknowledge */
1917#define nSRACK 0x0
1918#define MDDRENABLE 0x20 /* Mobile DDR enable */ 1805#define MDDRENABLE 0x20 /* Mobile DDR enable */
1919#define nMDDRENABLE 0x0
1920 1806
1921/* Bit masks for EBIU_DDRBRC0 */ 1807/* Bit masks for EBIU_DDRBRC0 */
1922 1808
@@ -2013,136 +1899,74 @@
2013/* Bit masks for EBIU_DDRMCEN */ 1899/* Bit masks for EBIU_DDRMCEN */
2014 1900
2015#define B0WCENABLE 0x1 /* Bank 0 write count enable */ 1901#define B0WCENABLE 0x1 /* Bank 0 write count enable */
2016#define nB0WCENABLE 0x0
2017#define B1WCENABLE 0x2 /* Bank 1 write count enable */ 1902#define B1WCENABLE 0x2 /* Bank 1 write count enable */
2018#define nB1WCENABLE 0x0
2019#define B2WCENABLE 0x4 /* Bank 2 write count enable */ 1903#define B2WCENABLE 0x4 /* Bank 2 write count enable */
2020#define nB2WCENABLE 0x0
2021#define B3WCENABLE 0x8 /* Bank 3 write count enable */ 1904#define B3WCENABLE 0x8 /* Bank 3 write count enable */
2022#define nB3WCENABLE 0x0
2023#define B4WCENABLE 0x10 /* Bank 4 write count enable */ 1905#define B4WCENABLE 0x10 /* Bank 4 write count enable */
2024#define nB4WCENABLE 0x0
2025#define B5WCENABLE 0x20 /* Bank 5 write count enable */ 1906#define B5WCENABLE 0x20 /* Bank 5 write count enable */
2026#define nB5WCENABLE 0x0
2027#define B6WCENABLE 0x40 /* Bank 6 write count enable */ 1907#define B6WCENABLE 0x40 /* Bank 6 write count enable */
2028#define nB6WCENABLE 0x0
2029#define B7WCENABLE 0x80 /* Bank 7 write count enable */ 1908#define B7WCENABLE 0x80 /* Bank 7 write count enable */
2030#define nB7WCENABLE 0x0
2031#define B0RCENABLE 0x100 /* Bank 0 read count enable */ 1909#define B0RCENABLE 0x100 /* Bank 0 read count enable */
2032#define nB0RCENABLE 0x0
2033#define B1RCENABLE 0x200 /* Bank 1 read count enable */ 1910#define B1RCENABLE 0x200 /* Bank 1 read count enable */
2034#define nB1RCENABLE 0x0
2035#define B2RCENABLE 0x400 /* Bank 2 read count enable */ 1911#define B2RCENABLE 0x400 /* Bank 2 read count enable */
2036#define nB2RCENABLE 0x0
2037#define B3RCENABLE 0x800 /* Bank 3 read count enable */ 1912#define B3RCENABLE 0x800 /* Bank 3 read count enable */
2038#define nB3RCENABLE 0x0
2039#define B4RCENABLE 0x1000 /* Bank 4 read count enable */ 1913#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
2040#define nB4RCENABLE 0x0
2041#define B5RCENABLE 0x2000 /* Bank 5 read count enable */ 1914#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
2042#define nB5RCENABLE 0x0
2043#define B6RCENABLE 0x4000 /* Bank 6 read count enable */ 1915#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
2044#define nB6RCENABLE 0x0
2045#define B7RCENABLE 0x8000 /* Bank 7 read count enable */ 1916#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
2046#define nB7RCENABLE 0x0
2047#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ 1917#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
2048#define nROWACTCENABLE 0x0
2049#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ 1918#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
2050#define nRWTCENABLE 0x0
2051#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ 1919#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
2052#define nARCENABLE 0x0
2053#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ 1920#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
2054#define nGC0ENABLE 0x0
2055#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ 1921#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
2056#define nGC1ENABLE 0x0
2057#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ 1922#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
2058#define nGC2ENABLE 0x0
2059#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ 1923#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
2060#define nGC3ENABLE 0x0
2061#define GCCONTROL 0x3000000 /* DDR Grant Count Control */ 1924#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
2062 1925
2063/* Bit masks for EBIU_DDRMCCL */ 1926/* Bit masks for EBIU_DDRMCCL */
2064 1927
2065#define CB0WCOUNT 0x1 /* Clear write count 0 */ 1928#define CB0WCOUNT 0x1 /* Clear write count 0 */
2066#define nCB0WCOUNT 0x0
2067#define CB1WCOUNT 0x2 /* Clear write count 1 */ 1929#define CB1WCOUNT 0x2 /* Clear write count 1 */
2068#define nCB1WCOUNT 0x0
2069#define CB2WCOUNT 0x4 /* Clear write count 2 */ 1930#define CB2WCOUNT 0x4 /* Clear write count 2 */
2070#define nCB2WCOUNT 0x0
2071#define CB3WCOUNT 0x8 /* Clear write count 3 */ 1931#define CB3WCOUNT 0x8 /* Clear write count 3 */
2072#define nCB3WCOUNT 0x0
2073#define CB4WCOUNT 0x10 /* Clear write count 4 */ 1932#define CB4WCOUNT 0x10 /* Clear write count 4 */
2074#define nCB4WCOUNT 0x0
2075#define CB5WCOUNT 0x20 /* Clear write count 5 */ 1933#define CB5WCOUNT 0x20 /* Clear write count 5 */
2076#define nCB5WCOUNT 0x0
2077#define CB6WCOUNT 0x40 /* Clear write count 6 */ 1934#define CB6WCOUNT 0x40 /* Clear write count 6 */
2078#define nCB6WCOUNT 0x0
2079#define CB7WCOUNT 0x80 /* Clear write count 7 */ 1935#define CB7WCOUNT 0x80 /* Clear write count 7 */
2080#define nCB7WCOUNT 0x0
2081#define CBRCOUNT 0x100 /* Clear read count 0 */ 1936#define CBRCOUNT 0x100 /* Clear read count 0 */
2082#define nCBRCOUNT 0x0
2083#define CB1RCOUNT 0x200 /* Clear read count 1 */ 1937#define CB1RCOUNT 0x200 /* Clear read count 1 */
2084#define nCB1RCOUNT 0x0
2085#define CB2RCOUNT 0x400 /* Clear read count 2 */ 1938#define CB2RCOUNT 0x400 /* Clear read count 2 */
2086#define nCB2RCOUNT 0x0
2087#define CB3RCOUNT 0x800 /* Clear read count 3 */ 1939#define CB3RCOUNT 0x800 /* Clear read count 3 */
2088#define nCB3RCOUNT 0x0
2089#define CB4RCOUNT 0x1000 /* Clear read count 4 */ 1940#define CB4RCOUNT 0x1000 /* Clear read count 4 */
2090#define nCB4RCOUNT 0x0
2091#define CB5RCOUNT 0x2000 /* Clear read count 5 */ 1941#define CB5RCOUNT 0x2000 /* Clear read count 5 */
2092#define nCB5RCOUNT 0x0
2093#define CB6RCOUNT 0x4000 /* Clear read count 6 */ 1942#define CB6RCOUNT 0x4000 /* Clear read count 6 */
2094#define nCB6RCOUNT 0x0
2095#define CB7RCOUNT 0x8000 /* Clear read count 7 */ 1943#define CB7RCOUNT 0x8000 /* Clear read count 7 */
2096#define nCB7RCOUNT 0x0
2097#define CRACOUNT 0x10000 /* Clear row activation count */ 1944#define CRACOUNT 0x10000 /* Clear row activation count */
2098#define nCRACOUNT 0x0
2099#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ 1945#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
2100#define nCRWTACOUNT 0x0
2101#define CARCOUNT 0x40000 /* Clear auto-refresh count */ 1946#define CARCOUNT 0x40000 /* Clear auto-refresh count */
2102#define nCARCOUNT 0x0
2103#define CG0COUNT 0x100000 /* Clear grant count 0 */ 1947#define CG0COUNT 0x100000 /* Clear grant count 0 */
2104#define nCG0COUNT 0x0
2105#define CG1COUNT 0x200000 /* Clear grant count 1 */ 1948#define CG1COUNT 0x200000 /* Clear grant count 1 */
2106#define nCG1COUNT 0x0
2107#define CG2COUNT 0x400000 /* Clear grant count 2 */ 1949#define CG2COUNT 0x400000 /* Clear grant count 2 */
2108#define nCG2COUNT 0x0
2109#define CG3COUNT 0x800000 /* Clear grant count 3 */ 1950#define CG3COUNT 0x800000 /* Clear grant count 3 */
2110#define nCG3COUNT 0x0
2111 1951
2112/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ 1952/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2113 1953
2114#define Px0 0x1 /* GPIO 0 */ 1954#define Px0 0x1 /* GPIO 0 */
2115#define nPx0 0x0
2116#define Px1 0x2 /* GPIO 1 */ 1955#define Px1 0x2 /* GPIO 1 */
2117#define nPx1 0x0
2118#define Px2 0x4 /* GPIO 2 */ 1956#define Px2 0x4 /* GPIO 2 */
2119#define nPx2 0x0
2120#define Px3 0x8 /* GPIO 3 */ 1957#define Px3 0x8 /* GPIO 3 */
2121#define nPx3 0x0
2122#define Px4 0x10 /* GPIO 4 */ 1958#define Px4 0x10 /* GPIO 4 */
2123#define nPx4 0x0
2124#define Px5 0x20 /* GPIO 5 */ 1959#define Px5 0x20 /* GPIO 5 */
2125#define nPx5 0x0
2126#define Px6 0x40 /* GPIO 6 */ 1960#define Px6 0x40 /* GPIO 6 */
2127#define nPx6 0x0
2128#define Px7 0x80 /* GPIO 7 */ 1961#define Px7 0x80 /* GPIO 7 */
2129#define nPx7 0x0
2130#define Px8 0x100 /* GPIO 8 */ 1962#define Px8 0x100 /* GPIO 8 */
2131#define nPx8 0x0
2132#define Px9 0x200 /* GPIO 9 */ 1963#define Px9 0x200 /* GPIO 9 */
2133#define nPx9 0x0
2134#define Px10 0x400 /* GPIO 10 */ 1964#define Px10 0x400 /* GPIO 10 */
2135#define nPx10 0x0
2136#define Px11 0x800 /* GPIO 11 */ 1965#define Px11 0x800 /* GPIO 11 */
2137#define nPx11 0x0
2138#define Px12 0x1000 /* GPIO 12 */ 1966#define Px12 0x1000 /* GPIO 12 */
2139#define nPx12 0x0
2140#define Px13 0x2000 /* GPIO 13 */ 1967#define Px13 0x2000 /* GPIO 13 */
2141#define nPx13 0x0
2142#define Px14 0x4000 /* GPIO 14 */ 1968#define Px14 0x4000 /* GPIO 14 */
2143#define nPx14 0x0
2144#define Px15 0x8000 /* GPIO 15 */ 1969#define Px15 0x8000 /* GPIO 15 */
2145#define nPx15 0x0
2146 1970
2147/* Bit masks for PORTA_MUX - PORTJ_MUX */ 1971/* Bit masks for PORTA_MUX - PORTJ_MUX */
2148 1972
@@ -2167,223 +1991,129 @@
2167/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ 1991/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2168 1992
2169#define IB0 0x1 /* Interrupt Bit 0 */ 1993#define IB0 0x1 /* Interrupt Bit 0 */
2170#define nIB0 0x0
2171#define IB1 0x2 /* Interrupt Bit 1 */ 1994#define IB1 0x2 /* Interrupt Bit 1 */
2172#define nIB1 0x0
2173#define IB2 0x4 /* Interrupt Bit 2 */ 1995#define IB2 0x4 /* Interrupt Bit 2 */
2174#define nIB2 0x0
2175#define IB3 0x8 /* Interrupt Bit 3 */ 1996#define IB3 0x8 /* Interrupt Bit 3 */
2176#define nIB3 0x0
2177#define IB4 0x10 /* Interrupt Bit 4 */ 1997#define IB4 0x10 /* Interrupt Bit 4 */
2178#define nIB4 0x0
2179#define IB5 0x20 /* Interrupt Bit 5 */ 1998#define IB5 0x20 /* Interrupt Bit 5 */
2180#define nIB5 0x0
2181#define IB6 0x40 /* Interrupt Bit 6 */ 1999#define IB6 0x40 /* Interrupt Bit 6 */
2182#define nIB6 0x0
2183#define IB7 0x80 /* Interrupt Bit 7 */ 2000#define IB7 0x80 /* Interrupt Bit 7 */
2184#define nIB7 0x0
2185#define IB8 0x100 /* Interrupt Bit 8 */ 2001#define IB8 0x100 /* Interrupt Bit 8 */
2186#define nIB8 0x0
2187#define IB9 0x200 /* Interrupt Bit 9 */ 2002#define IB9 0x200 /* Interrupt Bit 9 */
2188#define nIB9 0x0
2189#define IB10 0x400 /* Interrupt Bit 10 */ 2003#define IB10 0x400 /* Interrupt Bit 10 */
2190#define nIB10 0x0
2191#define IB11 0x800 /* Interrupt Bit 11 */ 2004#define IB11 0x800 /* Interrupt Bit 11 */
2192#define nIB11 0x0
2193#define IB12 0x1000 /* Interrupt Bit 12 */ 2005#define IB12 0x1000 /* Interrupt Bit 12 */
2194#define nIB12 0x0
2195#define IB13 0x2000 /* Interrupt Bit 13 */ 2006#define IB13 0x2000 /* Interrupt Bit 13 */
2196#define nIB13 0x0
2197#define IB14 0x4000 /* Interrupt Bit 14 */ 2007#define IB14 0x4000 /* Interrupt Bit 14 */
2198#define nIB14 0x0
2199#define IB15 0x8000 /* Interrupt Bit 15 */ 2008#define IB15 0x8000 /* Interrupt Bit 15 */
2200#define nIB15 0x0
2201 2009
2202/* Bit masks for TIMERx_CONFIG */ 2010/* Bit masks for TIMERx_CONFIG */
2203 2011
2204#define TMODE 0x3 /* Timer Mode */ 2012#define TMODE 0x3 /* Timer Mode */
2205#define PULSE_HI 0x4 /* Pulse Polarity */ 2013#define PULSE_HI 0x4 /* Pulse Polarity */
2206#define nPULSE_HI 0x0
2207#define PERIOD_CNT 0x8 /* Period Count */ 2014#define PERIOD_CNT 0x8 /* Period Count */
2208#define nPERIOD_CNT 0x0
2209#define IRQ_ENA 0x10 /* Interrupt Request Enable */ 2015#define IRQ_ENA 0x10 /* Interrupt Request Enable */
2210#define nIRQ_ENA 0x0
2211#define TIN_SEL 0x20 /* Timer Input Select */ 2016#define TIN_SEL 0x20 /* Timer Input Select */
2212#define nTIN_SEL 0x0
2213#define OUT_DIS 0x40 /* Output Pad Disable */ 2017#define OUT_DIS 0x40 /* Output Pad Disable */
2214#define nOUT_DIS 0x0
2215#define CLK_SEL 0x80 /* Timer Clock Select */ 2018#define CLK_SEL 0x80 /* Timer Clock Select */
2216#define nCLK_SEL 0x0
2217#define TOGGLE_HI 0x100 /* Toggle Mode */ 2019#define TOGGLE_HI 0x100 /* Toggle Mode */
2218#define nTOGGLE_HI 0x0
2219#define EMU_RUN 0x200 /* Emulation Behavior Select */ 2020#define EMU_RUN 0x200 /* Emulation Behavior Select */
2220#define nEMU_RUN 0x0
2221#define ERR_TYP 0xc000 /* Error Type */ 2021#define ERR_TYP 0xc000 /* Error Type */
2222 2022
2223/* Bit masks for TIMER_ENABLE0 */ 2023/* Bit masks for TIMER_ENABLE0 */
2224 2024
2225#define TIMEN0 0x1 /* Timer 0 Enable */ 2025#define TIMEN0 0x1 /* Timer 0 Enable */
2226#define nTIMEN0 0x0
2227#define TIMEN1 0x2 /* Timer 1 Enable */ 2026#define TIMEN1 0x2 /* Timer 1 Enable */
2228#define nTIMEN1 0x0
2229#define TIMEN2 0x4 /* Timer 2 Enable */ 2027#define TIMEN2 0x4 /* Timer 2 Enable */
2230#define nTIMEN2 0x0
2231#define TIMEN3 0x8 /* Timer 3 Enable */ 2028#define TIMEN3 0x8 /* Timer 3 Enable */
2232#define nTIMEN3 0x0
2233#define TIMEN4 0x10 /* Timer 4 Enable */ 2029#define TIMEN4 0x10 /* Timer 4 Enable */
2234#define nTIMEN4 0x0
2235#define TIMEN5 0x20 /* Timer 5 Enable */ 2030#define TIMEN5 0x20 /* Timer 5 Enable */
2236#define nTIMEN5 0x0
2237#define TIMEN6 0x40 /* Timer 6 Enable */ 2031#define TIMEN6 0x40 /* Timer 6 Enable */
2238#define nTIMEN6 0x0
2239#define TIMEN7 0x80 /* Timer 7 Enable */ 2032#define TIMEN7 0x80 /* Timer 7 Enable */
2240#define nTIMEN7 0x0
2241 2033
2242/* Bit masks for TIMER_DISABLE0 */ 2034/* Bit masks for TIMER_DISABLE0 */
2243 2035
2244#define TIMDIS0 0x1 /* Timer 0 Disable */ 2036#define TIMDIS0 0x1 /* Timer 0 Disable */
2245#define nTIMDIS0 0x0
2246#define TIMDIS1 0x2 /* Timer 1 Disable */ 2037#define TIMDIS1 0x2 /* Timer 1 Disable */
2247#define nTIMDIS1 0x0
2248#define TIMDIS2 0x4 /* Timer 2 Disable */ 2038#define TIMDIS2 0x4 /* Timer 2 Disable */
2249#define nTIMDIS2 0x0
2250#define TIMDIS3 0x8 /* Timer 3 Disable */ 2039#define TIMDIS3 0x8 /* Timer 3 Disable */
2251#define nTIMDIS3 0x0
2252#define TIMDIS4 0x10 /* Timer 4 Disable */ 2040#define TIMDIS4 0x10 /* Timer 4 Disable */
2253#define nTIMDIS4 0x0
2254#define TIMDIS5 0x20 /* Timer 5 Disable */ 2041#define TIMDIS5 0x20 /* Timer 5 Disable */
2255#define nTIMDIS5 0x0
2256#define TIMDIS6 0x40 /* Timer 6 Disable */ 2042#define TIMDIS6 0x40 /* Timer 6 Disable */
2257#define nTIMDIS6 0x0
2258#define TIMDIS7 0x80 /* Timer 7 Disable */ 2043#define TIMDIS7 0x80 /* Timer 7 Disable */
2259#define nTIMDIS7 0x0
2260 2044
2261/* Bit masks for TIMER_STATUS0 */ 2045/* Bit masks for TIMER_STATUS0 */
2262 2046
2263#define TIMIL0 0x1 /* Timer 0 Interrupt */ 2047#define TIMIL0 0x1 /* Timer 0 Interrupt */
2264#define nTIMIL0 0x0
2265#define TIMIL1 0x2 /* Timer 1 Interrupt */ 2048#define TIMIL1 0x2 /* Timer 1 Interrupt */
2266#define nTIMIL1 0x0
2267#define TIMIL2 0x4 /* Timer 2 Interrupt */ 2049#define TIMIL2 0x4 /* Timer 2 Interrupt */
2268#define nTIMIL2 0x0
2269#define TIMIL3 0x8 /* Timer 3 Interrupt */ 2050#define TIMIL3 0x8 /* Timer 3 Interrupt */
2270#define nTIMIL3 0x0
2271#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ 2051#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
2272#define nTOVF_ERR0 0x0
2273#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ 2052#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
2274#define nTOVF_ERR1 0x0
2275#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ 2053#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
2276#define nTOVF_ERR2 0x0
2277#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ 2054#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
2278#define nTOVF_ERR3 0x0
2279#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ 2055#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2280#define nTRUN0 0x0
2281#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ 2056#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2282#define nTRUN1 0x0
2283#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ 2057#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2284#define nTRUN2 0x0
2285#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ 2058#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
2286#define nTRUN3 0x0
2287#define TIMIL4 0x10000 /* Timer 4 Interrupt */ 2059#define TIMIL4 0x10000 /* Timer 4 Interrupt */
2288#define nTIMIL4 0x0
2289#define TIMIL5 0x20000 /* Timer 5 Interrupt */ 2060#define TIMIL5 0x20000 /* Timer 5 Interrupt */
2290#define nTIMIL5 0x0
2291#define TIMIL6 0x40000 /* Timer 6 Interrupt */ 2061#define TIMIL6 0x40000 /* Timer 6 Interrupt */
2292#define nTIMIL6 0x0
2293#define TIMIL7 0x80000 /* Timer 7 Interrupt */ 2062#define TIMIL7 0x80000 /* Timer 7 Interrupt */
2294#define nTIMIL7 0x0
2295#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ 2063#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
2296#define nTOVF_ERR4 0x0
2297#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ 2064#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
2298#define nTOVF_ERR5 0x0
2299#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ 2065#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
2300#define nTOVF_ERR6 0x0
2301#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ 2066#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
2302#define nTOVF_ERR7 0x0
2303#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 2067#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
2304#define nTRUN4 0x0
2305#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 2068#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
2306#define nTRUN5 0x0
2307#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 2069#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2308#define nTRUN6 0x0
2309#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 2070#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2310#define nTRUN7 0x0
2311 2071
2312/* Bit masks for WDOG_CTL */ 2072/* Bit masks for WDOG_CTL */
2313 2073
2314#define WDEV 0x6 /* Watchdog Event */ 2074#define WDEV 0x6 /* Watchdog Event */
2315#define WDEN 0xff0 /* Watchdog Enable */ 2075#define WDEN 0xff0 /* Watchdog Enable */
2316#define WDRO 0x8000 /* Watchdog Rolled Over */ 2076#define WDRO 0x8000 /* Watchdog Rolled Over */
2317#define nWDRO 0x0
2318 2077
2319/* Bit masks for CNT_CONFIG */ 2078/* Bit masks for CNT_CONFIG */
2320 2079
2321#define CNTE 0x1 /* Counter Enable */ 2080#define CNTE 0x1 /* Counter Enable */
2322#define nCNTE 0x0
2323#define DEBE 0x2 /* Debounce Enable */ 2081#define DEBE 0x2 /* Debounce Enable */
2324#define nDEBE 0x0
2325#define CDGINV 0x10 /* CDG Pin Polarity Invert */ 2082#define CDGINV 0x10 /* CDG Pin Polarity Invert */
2326#define nCDGINV 0x0
2327#define CUDINV 0x20 /* CUD Pin Polarity Invert */ 2083#define CUDINV 0x20 /* CUD Pin Polarity Invert */
2328#define nCUDINV 0x0
2329#define CZMINV 0x40 /* CZM Pin Polarity Invert */ 2084#define CZMINV 0x40 /* CZM Pin Polarity Invert */
2330#define nCZMINV 0x0
2331#define CNTMODE 0x700 /* Counter Operating Mode */ 2085#define CNTMODE 0x700 /* Counter Operating Mode */
2332#define ZMZC 0x800 /* CZM Zeroes Counter Enable */ 2086#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
2333#define nZMZC 0x0
2334#define BNDMODE 0x3000 /* Boundary register Mode */ 2087#define BNDMODE 0x3000 /* Boundary register Mode */
2335#define INPDIS 0x8000 /* CUG and CDG Input Disable */ 2088#define INPDIS 0x8000 /* CUG and CDG Input Disable */
2336#define nINPDIS 0x0
2337 2089
2338/* Bit masks for CNT_IMASK */ 2090/* Bit masks for CNT_IMASK */
2339 2091
2340#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ 2092#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
2341#define nICIE 0x0
2342#define UCIE 0x2 /* Up count Interrupt Enable */ 2093#define UCIE 0x2 /* Up count Interrupt Enable */
2343#define nUCIE 0x0
2344#define DCIE 0x4 /* Down count Interrupt Enable */ 2094#define DCIE 0x4 /* Down count Interrupt Enable */
2345#define nDCIE 0x0
2346#define MINCIE 0x8 /* Min Count Interrupt Enable */ 2095#define MINCIE 0x8 /* Min Count Interrupt Enable */
2347#define nMINCIE 0x0
2348#define MAXCIE 0x10 /* Max Count Interrupt Enable */ 2096#define MAXCIE 0x10 /* Max Count Interrupt Enable */
2349#define nMAXCIE 0x0
2350#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ 2097#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
2351#define nCOV31IE 0x0
2352#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ 2098#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
2353#define nCOV15IE 0x0
2354#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ 2099#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
2355#define nCZEROIE 0x0
2356#define CZMIE 0x100 /* CZM Pin Interrupt Enable */ 2100#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
2357#define nCZMIE 0x0
2358#define CZMEIE 0x200 /* CZM Error Interrupt Enable */ 2101#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
2359#define nCZMEIE 0x0
2360#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ 2102#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
2361#define nCZMZIE 0x0
2362 2103
2363/* Bit masks for CNT_STATUS */ 2104/* Bit masks for CNT_STATUS */
2364 2105
2365#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ 2106#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
2366#define nICII 0x0
2367#define UCII 0x2 /* Up count Interrupt Identifier */ 2107#define UCII 0x2 /* Up count Interrupt Identifier */
2368#define nUCII 0x0
2369#define DCII 0x4 /* Down count Interrupt Identifier */ 2108#define DCII 0x4 /* Down count Interrupt Identifier */
2370#define nDCII 0x0
2371#define MINCII 0x8 /* Min Count Interrupt Identifier */ 2109#define MINCII 0x8 /* Min Count Interrupt Identifier */
2372#define nMINCII 0x0
2373#define MAXCII 0x10 /* Max Count Interrupt Identifier */ 2110#define MAXCII 0x10 /* Max Count Interrupt Identifier */
2374#define nMAXCII 0x0
2375#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ 2111#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
2376#define nCOV31II 0x0
2377#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ 2112#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
2378#define nCOV15II 0x0
2379#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ 2113#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
2380#define nCZEROII 0x0
2381#define CZMII 0x100 /* CZM Pin Interrupt Identifier */ 2114#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
2382#define nCZMII 0x0
2383#define CZMEII 0x200 /* CZM Error Interrupt Identifier */ 2115#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
2384#define nCZMEII 0x0
2385#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ 2116#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2386#define nCZMZII 0x0
2387 2117
2388/* Bit masks for CNT_COMMAND */ 2118/* Bit masks for CNT_COMMAND */
2389 2119
@@ -2391,7 +2121,6 @@
2391#define W1LMIN 0xf0 /* Load Min Register */ 2121#define W1LMIN 0xf0 /* Load Min Register */
2392#define W1LMAX 0xf00 /* Load Max Register */ 2122#define W1LMAX 0xf00 /* Load Max Register */
2393#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ 2123#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2394#define nW1ZMONCE 0x0
2395 2124
2396/* Bit masks for CNT_DEBOUNCE */ 2125/* Bit masks for CNT_DEBOUNCE */
2397 2126
@@ -2407,42 +2136,25 @@
2407/* Bit masks for RTC_ICTL */ 2136/* Bit masks for RTC_ICTL */
2408 2137
2409#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ 2138#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2410#define nSTOPWATCH_INTERRUPT_ENABLE 0x0
2411#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ 2139#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2412#define nALARM_INTERRUPT_ENABLE 0x0
2413#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ 2140#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2414#define nSECONDS_INTERRUPT_ENABLE 0x0
2415#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ 2141#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2416#define nMINUTES_INTERRUPT_ENABLE 0x0
2417#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ 2142#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2418#define nHOURS_INTERRUPT_ENABLE 0x0
2419#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ 2143#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2420#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0
2421#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ 2144#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2422#define nDAY_ALARM_INTERRUPT_ENABLE 0x0
2423#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ 2145#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2424#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0
2425 2146
2426/* Bit masks for RTC_ISTAT */ 2147/* Bit masks for RTC_ISTAT */
2427 2148
2428#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ 2149#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2429#define nSTOPWATCH_EVENT_FLAG 0x0
2430#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ 2150#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2431#define nALARM_EVENT_FLAG 0x0
2432#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ 2151#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2433#define nSECONDS_EVENT_FLAG 0x0
2434#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ 2152#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2435#define nMINUTES_EVENT_FLAG 0x0
2436#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ 2153#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2437#define nHOURS_EVENT_FLAG 0x0
2438#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ 2154#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2439#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0
2440#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ 2155#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2441#define nDAY_ALARM_EVENT_FLAG 0x0
2442#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ 2156#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2443#define nWRITE_PENDING__STATUS 0x0
2444#define WRITE_COMPLETE 0x8000 /* Write Complete */ 2157#define WRITE_COMPLETE 0x8000 /* Write Complete */
2445#define nWRITE_COMPLETE 0x0
2446 2158
2447/* Bit masks for RTC_SWCNT */ 2159/* Bit masks for RTC_SWCNT */
2448 2160
@@ -2458,21 +2170,15 @@
2458/* Bit masks for RTC_PREN */ 2170/* Bit masks for RTC_PREN */
2459 2171
2460#define PREN 0x1 /* Prescaler Enable */ 2172#define PREN 0x1 /* Prescaler Enable */
2461#define nPREN 0x0
2462 2173
2463/* Bit masks for OTP_CONTROL */ 2174/* Bit masks for OTP_CONTROL */
2464 2175
2465#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 2176#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2466#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ 2177#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2467#define nFIEN 0x0
2468#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ 2178#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2469#define nFTESTDEC 0x0
2470#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ 2179#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2471#define nFWRTEST 0x0
2472#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ 2180#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2473#define nFRDEN 0x0
2474#define FWREN 0x8000 /* OTP/Fuse Write Enable */ 2181#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2475#define nFWREN 0x0
2476 2182
2477/* Bit masks for OTP_BEN */ 2183/* Bit masks for OTP_BEN */
2478 2184
@@ -2481,15 +2187,10 @@
2481/* Bit masks for OTP_STATUS */ 2187/* Bit masks for OTP_STATUS */
2482 2188
2483#define FCOMP 0x1 /* OTP/Fuse Access Complete */ 2189#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2484#define nFCOMP 0x0
2485#define FERROR 0x2 /* OTP/Fuse Access Error */ 2190#define FERROR 0x2 /* OTP/Fuse Access Error */
2486#define nFERROR 0x0
2487#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ 2191#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2488#define nMMRGLOAD 0x0
2489#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ 2192#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2490#define nMMRGLOCK 0x0
2491#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ 2193#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2492#define nFPGMEN 0x0
2493 2194
2494/* Bit masks for OTP_TIMING */ 2195/* Bit masks for OTP_TIMING */
2495 2196
@@ -2503,42 +2204,29 @@
2503/* Bit masks for SECURE_SYSSWT */ 2204/* Bit masks for SECURE_SYSSWT */
2504 2205
2505#define EMUDABL 0x1 /* Emulation Disable. */ 2206#define EMUDABL 0x1 /* Emulation Disable. */
2506#define nEMUDABL 0x0
2507#define RSTDABL 0x2 /* Reset Disable */ 2207#define RSTDABL 0x2 /* Reset Disable */
2508#define nRSTDABL 0x0
2509#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ 2208#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
2510#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ 2209#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
2511#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ 2210#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
2512#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ 2211#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
2513#define nDMA0OVR 0x0
2514#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ 2212#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
2515#define nDMA1OVR 0x0
2516#define EMUOVR 0x4000 /* Emulation Override */ 2213#define EMUOVR 0x4000 /* Emulation Override */
2517#define nEMUOVR 0x0
2518#define OTPSEN 0x8000 /* OTP Secrets Enable. */ 2214#define OTPSEN 0x8000 /* OTP Secrets Enable. */
2519#define nOTPSEN 0x0
2520#define L2DABL 0x70000 /* L2 Memory Disable. */ 2215#define L2DABL 0x70000 /* L2 Memory Disable. */
2521 2216
2522/* Bit masks for SECURE_CONTROL */ 2217/* Bit masks for SECURE_CONTROL */
2523 2218
2524#define SECURE0 0x1 /* SECURE 0 */ 2219#define SECURE0 0x1 /* SECURE 0 */
2525#define nSECURE0 0x0
2526#define SECURE1 0x2 /* SECURE 1 */ 2220#define SECURE1 0x2 /* SECURE 1 */
2527#define nSECURE1 0x0
2528#define SECURE2 0x4 /* SECURE 2 */ 2221#define SECURE2 0x4 /* SECURE 2 */
2529#define nSECURE2 0x0
2530#define SECURE3 0x8 /* SECURE 3 */ 2222#define SECURE3 0x8 /* SECURE 3 */
2531#define nSECURE3 0x0
2532 2223
2533/* Bit masks for SECURE_STATUS */ 2224/* Bit masks for SECURE_STATUS */
2534 2225
2535#define SECMODE 0x3 /* Secured Mode Control State */ 2226#define SECMODE 0x3 /* Secured Mode Control State */
2536#define NMI 0x4 /* Non Maskable Interrupt */ 2227#define NMI 0x4 /* Non Maskable Interrupt */
2537#define nNMI 0x0
2538#define AFVALID 0x8 /* Authentication Firmware Valid */ 2228#define AFVALID 0x8 /* Authentication Firmware Valid */
2539#define nAFVALID 0x0
2540#define AFEXIT 0x10 /* Authentication Firmware Exit */ 2229#define AFEXIT 0x10 /* Authentication Firmware Exit */
2541#define nAFEXIT 0x0
2542#define SECSTAT 0xe0 /* Secure Status */ 2230#define SECSTAT 0xe0 /* Secure Status */
2543 2231
2544/* Bit masks for PLL_DIV */ 2232/* Bit masks for PLL_DIV */
@@ -2550,42 +2238,25 @@
2550 2238
2551#define MSEL 0x7e00 /* Multiplier Select */ 2239#define MSEL 0x7e00 /* Multiplier Select */
2552#define BYPASS 0x100 /* PLL Bypass Enable */ 2240#define BYPASS 0x100 /* PLL Bypass Enable */
2553#define nBYPASS 0x0
2554#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ 2241#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2555#define nOUTPUT_DELAY 0x0
2556#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ 2242#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2557#define nINPUT_DELAY 0x0
2558#define PDWN 0x20 /* Power Down */ 2243#define PDWN 0x20 /* Power Down */
2559#define nPDWN 0x0
2560#define STOPCK 0x8 /* Stop Clock */ 2244#define STOPCK 0x8 /* Stop Clock */
2561#define nSTOPCK 0x0
2562#define PLL_OFF 0x2 /* Disable PLL */ 2245#define PLL_OFF 0x2 /* Disable PLL */
2563#define nPLL_OFF 0x0
2564#define DF 0x1 /* Divide Frequency */ 2246#define DF 0x1 /* Divide Frequency */
2565#define nDF 0x0
2566 2247
2567/* Bit masks for PLL_STAT */ 2248/* Bit masks for PLL_STAT */
2568 2249
2569#define PLL_LOCKED 0x20 /* PLL Locked Status */ 2250#define PLL_LOCKED 0x20 /* PLL Locked Status */
2570#define nPLL_LOCKED 0x0
2571#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ 2251#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2572#define nACTIVE_PLLDISABLED 0x0
2573#define FULL_ON 0x2 /* Full-On Mode */ 2252#define FULL_ON 0x2 /* Full-On Mode */
2574#define nFULL_ON 0x0
2575#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ 2253#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2576#define nACTIVE_PLLENABLED 0x0
2577#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ 2254#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2578#define nRTCWS 0x0
2579#define CANWS 0x800 /* CAN Wake-Up Status */ 2255#define CANWS 0x800 /* CAN Wake-Up Status */
2580#define nCANWS 0x0
2581#define USBWS 0x2000 /* USB Wake-Up Status */ 2256#define USBWS 0x2000 /* USB Wake-Up Status */
2582#define nUSBWS 0x0
2583#define KPADWS 0x4000 /* Keypad Wake-Up Status */ 2257#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2584#define nKPADWS 0x0
2585#define ROTWS 0x8000 /* Rotary Wake-Up Status */ 2258#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2586#define nROTWS 0x0
2587#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ 2259#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2588#define nGPWS 0x0
2589 2260
2590/* Bit masks for VR_CTL */ 2261/* Bit masks for VR_CTL */
2591 2262
@@ -2593,79 +2264,52 @@
2593#define GAIN 0xc /* Voltage Output Level Gain */ 2264#define GAIN 0xc /* Voltage Output Level Gain */
2594#define VLEV 0xf0 /* Internal Voltage Level */ 2265#define VLEV 0xf0 /* Internal Voltage Level */
2595#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ 2266#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2596#define nSCKELOW 0x0
2597#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ 2267#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2598#define nWAKE 0x0
2599#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ 2268#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2600#define nCANWE 0x0
2601#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ 2269#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2602#define nGPWE 0x0
2603#define USBWE 0x800 /* USB Wake-Up Enable */ 2270#define USBWE 0x800 /* USB Wake-Up Enable */
2604#define nUSBWE 0x0
2605#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 2271#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2606#define nKPADWE 0x0
2607#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 2272#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2608#define nROTWE 0x0
2609 2273
2610/* Bit masks for NFC_CTL */ 2274/* Bit masks for NFC_CTL */
2611 2275
2612#define WR_DLY 0xf /* Write Strobe Delay */ 2276#define WR_DLY 0xf /* Write Strobe Delay */
2613#define RD_DLY 0xf0 /* Read Strobe Delay */ 2277#define RD_DLY 0xf0 /* Read Strobe Delay */
2614#define NWIDTH 0x100 /* NAND Data Width */ 2278#define NWIDTH 0x100 /* NAND Data Width */
2615#define nNWIDTH 0x0
2616#define PG_SIZE 0x200 /* Page Size */ 2279#define PG_SIZE 0x200 /* Page Size */
2617#define nPG_SIZE 0x0
2618 2280
2619/* Bit masks for NFC_STAT */ 2281/* Bit masks for NFC_STAT */
2620 2282
2621#define NBUSY 0x1 /* Not Busy */ 2283#define NBUSY 0x1 /* Not Busy */
2622#define nNBUSY 0x0
2623#define WB_FULL 0x2 /* Write Buffer Full */ 2284#define WB_FULL 0x2 /* Write Buffer Full */
2624#define nWB_FULL 0x0
2625#define PG_WR_STAT 0x4 /* Page Write Pending */ 2285#define PG_WR_STAT 0x4 /* Page Write Pending */
2626#define nPG_WR_STAT 0x0
2627#define PG_RD_STAT 0x8 /* Page Read Pending */ 2286#define PG_RD_STAT 0x8 /* Page Read Pending */
2628#define nPG_RD_STAT 0x0
2629#define WB_EMPTY 0x10 /* Write Buffer Empty */ 2287#define WB_EMPTY 0x10 /* Write Buffer Empty */
2630#define nWB_EMPTY 0x0
2631 2288
2632/* Bit masks for NFC_IRQSTAT */ 2289/* Bit masks for NFC_IRQSTAT */
2633 2290
2634#define NBUSYIRQ 0x1 /* Not Busy IRQ */ 2291#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2635#define nNBUSYIRQ 0x0
2636#define WB_OVF 0x2 /* Write Buffer Overflow */ 2292#define WB_OVF 0x2 /* Write Buffer Overflow */
2637#define nWB_OVF 0x0
2638#define WB_EDGE 0x4 /* Write Buffer Edge Detect */ 2293#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2639#define nWB_EDGE 0x0
2640#define RD_RDY 0x8 /* Read Data Ready */ 2294#define RD_RDY 0x8 /* Read Data Ready */
2641#define nRD_RDY 0x0
2642#define WR_DONE 0x10 /* Page Write Done */ 2295#define WR_DONE 0x10 /* Page Write Done */
2643#define nWR_DONE 0x0
2644 2296
2645/* Bit masks for NFC_IRQMASK */ 2297/* Bit masks for NFC_IRQMASK */
2646 2298
2647#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ 2299#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2648#define nMASK_BUSYIRQ 0x0
2649#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ 2300#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2650#define nMASK_WBOVF 0x0
2651#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ 2301#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2652#define nMASK_WBEMPTY 0x0
2653#define MASK_RDRDY 0x8 /* Mask Read Data Ready */ 2302#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2654#define nMASK_RDRDY 0x0
2655#define MASK_WRDONE 0x10 /* Mask Write Done */ 2303#define MASK_WRDONE 0x10 /* Mask Write Done */
2656#define nMASK_WRDONE 0x0
2657 2304
2658/* Bit masks for NFC_RST */ 2305/* Bit masks for NFC_RST */
2659 2306
2660#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ 2307#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2661#define nECC_RST 0x0
2662 2308
2663/* Bit masks for NFC_PGCTL */ 2309/* Bit masks for NFC_PGCTL */
2664 2310
2665#define PG_RD_START 0x1 /* Page Read Start */ 2311#define PG_RD_START 0x1 /* Page Read Start */
2666#define nPG_RD_START 0x0
2667#define PG_WR_START 0x2 /* Page Write Start */ 2312#define PG_WR_START 0x2 /* Page Write Start */
2668#define nPG_WR_START 0x0
2669 2313
2670/* Bit masks for NFC_ECC0 */ 2314/* Bit masks for NFC_ECC0 */
2671 2315
@@ -2690,56 +2334,34 @@
2690/* Bit masks for CAN0_CONTROL */ 2334/* Bit masks for CAN0_CONTROL */
2691 2335
2692#define SRS 0x1 /* Software Reset */ 2336#define SRS 0x1 /* Software Reset */
2693#define nSRS 0x0
2694#define DNM 0x2 /* DeviceNet Mode */ 2337#define DNM 0x2 /* DeviceNet Mode */
2695#define nDNM 0x0
2696#define ABO 0x4 /* Auto Bus On */ 2338#define ABO 0x4 /* Auto Bus On */
2697#define nABO 0x0
2698#define WBA 0x10 /* Wakeup On CAN Bus Activity */ 2339#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2699#define nWBA 0x0
2700#define SMR 0x20 /* Sleep Mode Request */ 2340#define SMR 0x20 /* Sleep Mode Request */
2701#define nSMR 0x0
2702#define CSR 0x40 /* CAN Suspend Mode Request */ 2341#define CSR 0x40 /* CAN Suspend Mode Request */
2703#define nCSR 0x0
2704#define CCR 0x80 /* CAN Configuration Mode Request */ 2342#define CCR 0x80 /* CAN Configuration Mode Request */
2705#define nCCR 0x0
2706 2343
2707/* Bit masks for CAN0_STATUS */ 2344/* Bit masks for CAN0_STATUS */
2708 2345
2709#define WT 0x1 /* CAN Transmit Warning Flag */ 2346#define WT 0x1 /* CAN Transmit Warning Flag */
2710#define nWT 0x0
2711#define WR 0x2 /* CAN Receive Warning Flag */ 2347#define WR 0x2 /* CAN Receive Warning Flag */
2712#define nWR 0x0
2713#define EP 0x4 /* CAN Error Passive Mode */ 2348#define EP 0x4 /* CAN Error Passive Mode */
2714#define nEP 0x0
2715#define EBO 0x8 /* CAN Error Bus Off Mode */ 2349#define EBO 0x8 /* CAN Error Bus Off Mode */
2716#define nEBO 0x0
2717#define CSA 0x40 /* CAN Suspend Mode Acknowledge */ 2350#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2718#define nCSA 0x0
2719#define CCA 0x80 /* CAN Configuration Mode Acknowledge */ 2351#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2720#define nCCA 0x0
2721#define MBPTR 0x1f00 /* Mailbox Pointer */ 2352#define MBPTR 0x1f00 /* Mailbox Pointer */
2722#define TRM 0x4000 /* Transmit Mode Status */ 2353#define TRM 0x4000 /* Transmit Mode Status */
2723#define nTRM 0x0
2724#define REC 0x8000 /* Receive Mode Status */ 2354#define REC 0x8000 /* Receive Mode Status */
2725#define nREC 0x0
2726 2355
2727/* Bit masks for CAN0_DEBUG */ 2356/* Bit masks for CAN0_DEBUG */
2728 2357
2729#define DEC 0x1 /* Disable Transmit/Receive Error Counters */ 2358#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2730#define nDEC 0x0
2731#define DRI 0x2 /* Disable CANRX Input Pin */ 2359#define DRI 0x2 /* Disable CANRX Input Pin */
2732#define nDRI 0x0
2733#define DTO 0x4 /* Disable CANTX Output Pin */ 2360#define DTO 0x4 /* Disable CANTX Output Pin */
2734#define nDTO 0x0
2735#define DIL 0x8 /* Disable Internal Loop */ 2361#define DIL 0x8 /* Disable Internal Loop */
2736#define nDIL 0x0
2737#define MAA 0x10 /* Mode Auto-Acknowledge */ 2362#define MAA 0x10 /* Mode Auto-Acknowledge */
2738#define nMAA 0x0
2739#define MRB 0x20 /* Mode Read Back */ 2363#define MRB 0x20 /* Mode Read Back */
2740#define nMRB 0x0
2741#define CDE 0x8000 /* CAN Debug Mode Enable */ 2364#define CDE 0x8000 /* CAN Debug Mode Enable */
2742#define nCDE 0x0
2743 2365
2744/* Bit masks for CAN0_CLOCK */ 2366/* Bit masks for CAN0_CLOCK */
2745 2367
@@ -2749,111 +2371,69 @@
2749 2371
2750#define SJW 0x300 /* Synchronization Jump Width */ 2372#define SJW 0x300 /* Synchronization Jump Width */
2751#define SAM 0x80 /* Sampling */ 2373#define SAM 0x80 /* Sampling */
2752#define nSAM 0x0
2753#define TSEG2 0x70 /* Time Segment 2 */ 2374#define TSEG2 0x70 /* Time Segment 2 */
2754#define TSEG1 0xf /* Time Segment 1 */ 2375#define TSEG1 0xf /* Time Segment 1 */
2755 2376
2756/* Bit masks for CAN0_INTR */ 2377/* Bit masks for CAN0_INTR */
2757 2378
2758#define CANRX 0x80 /* Serial Input From Transceiver */ 2379#define CANRX 0x80 /* Serial Input From Transceiver */
2759#define nCANRX 0x0
2760#define CANTX 0x40 /* Serial Output To Transceiver */ 2380#define CANTX 0x40 /* Serial Output To Transceiver */
2761#define nCANTX 0x0
2762#define SMACK 0x8 /* Sleep Mode Acknowledge */ 2381#define SMACK 0x8 /* Sleep Mode Acknowledge */
2763#define nSMACK 0x0
2764#define GIRQ 0x4 /* Global Interrupt Request Status */ 2382#define GIRQ 0x4 /* Global Interrupt Request Status */
2765#define nGIRQ 0x0
2766#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ 2383#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2767#define nMBTIRQ 0x0
2768#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ 2384#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2769#define nMBRIRQ 0x0
2770 2385
2771/* Bit masks for CAN0_GIM */ 2386/* Bit masks for CAN0_GIM */
2772 2387
2773#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ 2388#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2774#define nEWTIM 0x0
2775#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ 2389#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2776#define nEWRIM 0x0
2777#define EPIM 0x4 /* Error Passive Interrupt Mask */ 2390#define EPIM 0x4 /* Error Passive Interrupt Mask */
2778#define nEPIM 0x0
2779#define BOIM 0x8 /* Bus Off Interrupt Mask */ 2391#define BOIM 0x8 /* Bus Off Interrupt Mask */
2780#define nBOIM 0x0
2781#define WUIM 0x10 /* Wakeup Interrupt Mask */ 2392#define WUIM 0x10 /* Wakeup Interrupt Mask */
2782#define nWUIM 0x0
2783#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ 2393#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2784#define nUIAIM 0x0
2785#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ 2394#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2786#define nAAIM 0x0
2787#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ 2395#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2788#define nRMLIM 0x0
2789#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ 2396#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2790#define nUCEIM 0x0
2791#define ADIM 0x400 /* Access Denied Interrupt Mask */ 2397#define ADIM 0x400 /* Access Denied Interrupt Mask */
2792#define nADIM 0x0
2793 2398
2794/* Bit masks for CAN0_GIS */ 2399/* Bit masks for CAN0_GIS */
2795 2400
2796#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ 2401#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2797#define nEWTIS 0x0
2798#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ 2402#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2799#define nEWRIS 0x0
2800#define EPIS 0x4 /* Error Passive Interrupt Status */ 2403#define EPIS 0x4 /* Error Passive Interrupt Status */
2801#define nEPIS 0x0
2802#define BOIS 0x8 /* Bus Off Interrupt Status */ 2404#define BOIS 0x8 /* Bus Off Interrupt Status */
2803#define nBOIS 0x0
2804#define WUIS 0x10 /* Wakeup Interrupt Status */ 2405#define WUIS 0x10 /* Wakeup Interrupt Status */
2805#define nWUIS 0x0
2806#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ 2406#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2807#define nUIAIS 0x0
2808#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ 2407#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2809#define nAAIS 0x0
2810#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ 2408#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2811#define nRMLIS 0x0
2812#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ 2409#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2813#define nUCEIS 0x0
2814#define ADIS 0x400 /* Access Denied Interrupt Status */ 2410#define ADIS 0x400 /* Access Denied Interrupt Status */
2815#define nADIS 0x0
2816 2411
2817/* Bit masks for CAN0_GIF */ 2412/* Bit masks for CAN0_GIF */
2818 2413
2819#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ 2414#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2820#define nEWTIF 0x0
2821#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ 2415#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2822#define nEWRIF 0x0
2823#define EPIF 0x4 /* Error Passive Interrupt Flag */ 2416#define EPIF 0x4 /* Error Passive Interrupt Flag */
2824#define nEPIF 0x0
2825#define BOIF 0x8 /* Bus Off Interrupt Flag */ 2417#define BOIF 0x8 /* Bus Off Interrupt Flag */
2826#define nBOIF 0x0
2827#define WUIF 0x10 /* Wakeup Interrupt Flag */ 2418#define WUIF 0x10 /* Wakeup Interrupt Flag */
2828#define nWUIF 0x0
2829#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ 2419#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2830#define nUIAIF 0x0
2831#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ 2420#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2832#define nAAIF 0x0
2833#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ 2421#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2834#define nRMLIF 0x0
2835#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ 2422#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2836#define nUCEIF 0x0
2837#define ADIF 0x400 /* Access Denied Interrupt Flag */ 2423#define ADIF 0x400 /* Access Denied Interrupt Flag */
2838#define nADIF 0x0
2839 2424
2840/* Bit masks for CAN0_MBTD */ 2425/* Bit masks for CAN0_MBTD */
2841 2426
2842#define TDR 0x80 /* Temporary Disable Request */ 2427#define TDR 0x80 /* Temporary Disable Request */
2843#define nTDR 0x0
2844#define TDA 0x40 /* Temporary Disable Acknowledge */ 2428#define TDA 0x40 /* Temporary Disable Acknowledge */
2845#define nTDA 0x0
2846#define TDPTR 0x1f /* Temporary Disable Pointer */ 2429#define TDPTR 0x1f /* Temporary Disable Pointer */
2847 2430
2848/* Bit masks for CAN0_UCCNF */ 2431/* Bit masks for CAN0_UCCNF */
2849 2432
2850#define UCCNF 0xf /* Universal Counter Configuration */ 2433#define UCCNF 0xf /* Universal Counter Configuration */
2851#define UCRC 0x20 /* Universal Counter Reload/Clear */ 2434#define UCRC 0x20 /* Universal Counter Reload/Clear */
2852#define nUCRC 0x0
2853#define UCCT 0x40 /* Universal Counter CAN Trigger */ 2435#define UCCT 0x40 /* Universal Counter CAN Trigger */
2854#define nUCCT 0x0
2855#define UCE 0x80 /* Universal Counter Enable */ 2436#define UCE 0x80 /* Universal Counter Enable */
2856#define nUCE 0x0
2857 2437
2858/* Bit masks for CAN0_UCCNT */ 2438/* Bit masks for CAN0_UCCNT */
2859 2439
@@ -2871,17 +2451,11 @@
2871/* Bit masks for CAN0_ESR */ 2451/* Bit masks for CAN0_ESR */
2872 2452
2873#define FER 0x80 /* Form Error */ 2453#define FER 0x80 /* Form Error */
2874#define nFER 0x0
2875#define BEF 0x40 /* Bit Error Flag */ 2454#define BEF 0x40 /* Bit Error Flag */
2876#define nBEF 0x0
2877#define SA0 0x20 /* Stuck At Dominant */ 2455#define SA0 0x20 /* Stuck At Dominant */
2878#define nSA0 0x0
2879#define CRCE 0x10 /* CRC Error */ 2456#define CRCE 0x10 /* CRC Error */
2880#define nCRCE 0x0
2881#define SER 0x8 /* Stuff Bit Error */ 2457#define SER 0x8 /* Stuff Bit Error */
2882#define nSER 0x0
2883#define ACKE 0x4 /* Acknowledge Error */ 2458#define ACKE 0x4 /* Acknowledge Error */
2884#define nACKE 0x0
2885 2459
2886/* Bit masks for CAN0_EWR */ 2460/* Bit masks for CAN0_EWR */
2887 2461
@@ -2891,11 +2465,8 @@
2891/* Bit masks for CAN0_AMxx_H */ 2465/* Bit masks for CAN0_AMxx_H */
2892 2466
2893#define FDF 0x8000 /* Filter On Data Field */ 2467#define FDF 0x8000 /* Filter On Data Field */
2894#define nFDF 0x0
2895#define FMD 0x4000 /* Full Mask Data */ 2468#define FMD 0x4000 /* Full Mask Data */
2896#define nFMD 0x0
2897#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ 2469#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2898#define nAMIDE 0x0
2899#define BASEID 0x1ffc /* Base Identifier */ 2470#define BASEID 0x1ffc /* Base Identifier */
2900#define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2471#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2901 2472
@@ -2907,11 +2478,8 @@
2907/* Bit masks for CAN0_MBxx_ID1 */ 2478/* Bit masks for CAN0_MBxx_ID1 */
2908 2479
2909#define AME 0x8000 /* Acceptance Mask Enable */ 2480#define AME 0x8000 /* Acceptance Mask Enable */
2910#define nAME 0x0
2911#define RTR 0x4000 /* Remote Transmission Request */ 2481#define RTR 0x4000 /* Remote Transmission Request */
2912#define nRTR 0x0
2913#define IDE 0x2000 /* Identifier Extension */ 2482#define IDE 0x2000 /* Identifier Extension */
2914#define nIDE 0x0
2915#define BASEID 0x1ffc /* Base Identifier */ 2483#define BASEID 0x1ffc /* Base Identifier */
2916#define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2484#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2917 2485
@@ -2951,977 +2519,534 @@
2951/* Bit masks for CAN0_MC1 */ 2519/* Bit masks for CAN0_MC1 */
2952 2520
2953#define MC0 0x1 /* Mailbox 0 Enable */ 2521#define MC0 0x1 /* Mailbox 0 Enable */
2954#define nMC0 0x0
2955#define MC1 0x2 /* Mailbox 1 Enable */ 2522#define MC1 0x2 /* Mailbox 1 Enable */
2956#define nMC1 0x0
2957#define MC2 0x4 /* Mailbox 2 Enable */ 2523#define MC2 0x4 /* Mailbox 2 Enable */
2958#define nMC2 0x0
2959#define MC3 0x8 /* Mailbox 3 Enable */ 2524#define MC3 0x8 /* Mailbox 3 Enable */
2960#define nMC3 0x0
2961#define MC4 0x10 /* Mailbox 4 Enable */ 2525#define MC4 0x10 /* Mailbox 4 Enable */
2962#define nMC4 0x0
2963#define MC5 0x20 /* Mailbox 5 Enable */ 2526#define MC5 0x20 /* Mailbox 5 Enable */
2964#define nMC5 0x0
2965#define MC6 0x40 /* Mailbox 6 Enable */ 2527#define MC6 0x40 /* Mailbox 6 Enable */
2966#define nMC6 0x0
2967#define MC7 0x80 /* Mailbox 7 Enable */ 2528#define MC7 0x80 /* Mailbox 7 Enable */
2968#define nMC7 0x0
2969#define MC8 0x100 /* Mailbox 8 Enable */ 2529#define MC8 0x100 /* Mailbox 8 Enable */
2970#define nMC8 0x0
2971#define MC9 0x200 /* Mailbox 9 Enable */ 2530#define MC9 0x200 /* Mailbox 9 Enable */
2972#define nMC9 0x0
2973#define MC10 0x400 /* Mailbox 10 Enable */ 2531#define MC10 0x400 /* Mailbox 10 Enable */
2974#define nMC10 0x0
2975#define MC11 0x800 /* Mailbox 11 Enable */ 2532#define MC11 0x800 /* Mailbox 11 Enable */
2976#define nMC11 0x0
2977#define MC12 0x1000 /* Mailbox 12 Enable */ 2533#define MC12 0x1000 /* Mailbox 12 Enable */
2978#define nMC12 0x0
2979#define MC13 0x2000 /* Mailbox 13 Enable */ 2534#define MC13 0x2000 /* Mailbox 13 Enable */
2980#define nMC13 0x0
2981#define MC14 0x4000 /* Mailbox 14 Enable */ 2535#define MC14 0x4000 /* Mailbox 14 Enable */
2982#define nMC14 0x0
2983#define MC15 0x8000 /* Mailbox 15 Enable */ 2536#define MC15 0x8000 /* Mailbox 15 Enable */
2984#define nMC15 0x0
2985 2537
2986/* Bit masks for CAN0_MC2 */ 2538/* Bit masks for CAN0_MC2 */
2987 2539
2988#define MC16 0x1 /* Mailbox 16 Enable */ 2540#define MC16 0x1 /* Mailbox 16 Enable */
2989#define nMC16 0x0
2990#define MC17 0x2 /* Mailbox 17 Enable */ 2541#define MC17 0x2 /* Mailbox 17 Enable */
2991#define nMC17 0x0
2992#define MC18 0x4 /* Mailbox 18 Enable */ 2542#define MC18 0x4 /* Mailbox 18 Enable */
2993#define nMC18 0x0
2994#define MC19 0x8 /* Mailbox 19 Enable */ 2543#define MC19 0x8 /* Mailbox 19 Enable */
2995#define nMC19 0x0
2996#define MC20 0x10 /* Mailbox 20 Enable */ 2544#define MC20 0x10 /* Mailbox 20 Enable */
2997#define nMC20 0x0
2998#define MC21 0x20 /* Mailbox 21 Enable */ 2545#define MC21 0x20 /* Mailbox 21 Enable */
2999#define nMC21 0x0
3000#define MC22 0x40 /* Mailbox 22 Enable */ 2546#define MC22 0x40 /* Mailbox 22 Enable */
3001#define nMC22 0x0
3002#define MC23 0x80 /* Mailbox 23 Enable */ 2547#define MC23 0x80 /* Mailbox 23 Enable */
3003#define nMC23 0x0
3004#define MC24 0x100 /* Mailbox 24 Enable */ 2548#define MC24 0x100 /* Mailbox 24 Enable */
3005#define nMC24 0x0
3006#define MC25 0x200 /* Mailbox 25 Enable */ 2549#define MC25 0x200 /* Mailbox 25 Enable */
3007#define nMC25 0x0
3008#define MC26 0x400 /* Mailbox 26 Enable */ 2550#define MC26 0x400 /* Mailbox 26 Enable */
3009#define nMC26 0x0
3010#define MC27 0x800 /* Mailbox 27 Enable */ 2551#define MC27 0x800 /* Mailbox 27 Enable */
3011#define nMC27 0x0
3012#define MC28 0x1000 /* Mailbox 28 Enable */ 2552#define MC28 0x1000 /* Mailbox 28 Enable */
3013#define nMC28 0x0
3014#define MC29 0x2000 /* Mailbox 29 Enable */ 2553#define MC29 0x2000 /* Mailbox 29 Enable */
3015#define nMC29 0x0
3016#define MC30 0x4000 /* Mailbox 30 Enable */ 2554#define MC30 0x4000 /* Mailbox 30 Enable */
3017#define nMC30 0x0
3018#define MC31 0x8000 /* Mailbox 31 Enable */ 2555#define MC31 0x8000 /* Mailbox 31 Enable */
3019#define nMC31 0x0
3020 2556
3021/* Bit masks for CAN0_MD1 */ 2557/* Bit masks for CAN0_MD1 */
3022 2558
3023#define MD0 0x1 /* Mailbox 0 Receive Enable */ 2559#define MD0 0x1 /* Mailbox 0 Receive Enable */
3024#define nMD0 0x0
3025#define MD1 0x2 /* Mailbox 1 Receive Enable */ 2560#define MD1 0x2 /* Mailbox 1 Receive Enable */
3026#define nMD1 0x0
3027#define MD2 0x4 /* Mailbox 2 Receive Enable */ 2561#define MD2 0x4 /* Mailbox 2 Receive Enable */
3028#define nMD2 0x0
3029#define MD3 0x8 /* Mailbox 3 Receive Enable */ 2562#define MD3 0x8 /* Mailbox 3 Receive Enable */
3030#define nMD3 0x0
3031#define MD4 0x10 /* Mailbox 4 Receive Enable */ 2563#define MD4 0x10 /* Mailbox 4 Receive Enable */
3032#define nMD4 0x0
3033#define MD5 0x20 /* Mailbox 5 Receive Enable */ 2564#define MD5 0x20 /* Mailbox 5 Receive Enable */
3034#define nMD5 0x0
3035#define MD6 0x40 /* Mailbox 6 Receive Enable */ 2565#define MD6 0x40 /* Mailbox 6 Receive Enable */
3036#define nMD6 0x0
3037#define MD7 0x80 /* Mailbox 7 Receive Enable */ 2566#define MD7 0x80 /* Mailbox 7 Receive Enable */
3038#define nMD7 0x0
3039#define MD8 0x100 /* Mailbox 8 Receive Enable */ 2567#define MD8 0x100 /* Mailbox 8 Receive Enable */
3040#define nMD8 0x0
3041#define MD9 0x200 /* Mailbox 9 Receive Enable */ 2568#define MD9 0x200 /* Mailbox 9 Receive Enable */
3042#define nMD9 0x0
3043#define MD10 0x400 /* Mailbox 10 Receive Enable */ 2569#define MD10 0x400 /* Mailbox 10 Receive Enable */
3044#define nMD10 0x0
3045#define MD11 0x800 /* Mailbox 11 Receive Enable */ 2570#define MD11 0x800 /* Mailbox 11 Receive Enable */
3046#define nMD11 0x0
3047#define MD12 0x1000 /* Mailbox 12 Receive Enable */ 2571#define MD12 0x1000 /* Mailbox 12 Receive Enable */
3048#define nMD12 0x0
3049#define MD13 0x2000 /* Mailbox 13 Receive Enable */ 2572#define MD13 0x2000 /* Mailbox 13 Receive Enable */
3050#define nMD13 0x0
3051#define MD14 0x4000 /* Mailbox 14 Receive Enable */ 2573#define MD14 0x4000 /* Mailbox 14 Receive Enable */
3052#define nMD14 0x0
3053#define MD15 0x8000 /* Mailbox 15 Receive Enable */ 2574#define MD15 0x8000 /* Mailbox 15 Receive Enable */
3054#define nMD15 0x0
3055 2575
3056/* Bit masks for CAN0_MD2 */ 2576/* Bit masks for CAN0_MD2 */
3057 2577
3058#define MD16 0x1 /* Mailbox 16 Receive Enable */ 2578#define MD16 0x1 /* Mailbox 16 Receive Enable */
3059#define nMD16 0x0
3060#define MD17 0x2 /* Mailbox 17 Receive Enable */ 2579#define MD17 0x2 /* Mailbox 17 Receive Enable */
3061#define nMD17 0x0
3062#define MD18 0x4 /* Mailbox 18 Receive Enable */ 2580#define MD18 0x4 /* Mailbox 18 Receive Enable */
3063#define nMD18 0x0
3064#define MD19 0x8 /* Mailbox 19 Receive Enable */ 2581#define MD19 0x8 /* Mailbox 19 Receive Enable */
3065#define nMD19 0x0
3066#define MD20 0x10 /* Mailbox 20 Receive Enable */ 2582#define MD20 0x10 /* Mailbox 20 Receive Enable */
3067#define nMD20 0x0
3068#define MD21 0x20 /* Mailbox 21 Receive Enable */ 2583#define MD21 0x20 /* Mailbox 21 Receive Enable */
3069#define nMD21 0x0
3070#define MD22 0x40 /* Mailbox 22 Receive Enable */ 2584#define MD22 0x40 /* Mailbox 22 Receive Enable */
3071#define nMD22 0x0
3072#define MD23 0x80 /* Mailbox 23 Receive Enable */ 2585#define MD23 0x80 /* Mailbox 23 Receive Enable */
3073#define nMD23 0x0
3074#define MD24 0x100 /* Mailbox 24 Receive Enable */ 2586#define MD24 0x100 /* Mailbox 24 Receive Enable */
3075#define nMD24 0x0
3076#define MD25 0x200 /* Mailbox 25 Receive Enable */ 2587#define MD25 0x200 /* Mailbox 25 Receive Enable */
3077#define nMD25 0x0
3078#define MD26 0x400 /* Mailbox 26 Receive Enable */ 2588#define MD26 0x400 /* Mailbox 26 Receive Enable */
3079#define nMD26 0x0
3080#define MD27 0x800 /* Mailbox 27 Receive Enable */ 2589#define MD27 0x800 /* Mailbox 27 Receive Enable */
3081#define nMD27 0x0
3082#define MD28 0x1000 /* Mailbox 28 Receive Enable */ 2590#define MD28 0x1000 /* Mailbox 28 Receive Enable */
3083#define nMD28 0x0
3084#define MD29 0x2000 /* Mailbox 29 Receive Enable */ 2591#define MD29 0x2000 /* Mailbox 29 Receive Enable */
3085#define nMD29 0x0
3086#define MD30 0x4000 /* Mailbox 30 Receive Enable */ 2592#define MD30 0x4000 /* Mailbox 30 Receive Enable */
3087#define nMD30 0x0
3088#define MD31 0x8000 /* Mailbox 31 Receive Enable */ 2593#define MD31 0x8000 /* Mailbox 31 Receive Enable */
3089#define nMD31 0x0
3090 2594
3091/* Bit masks for CAN0_RMP1 */ 2595/* Bit masks for CAN0_RMP1 */
3092 2596
3093#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ 2597#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
3094#define nRMP0 0x0
3095#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ 2598#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
3096#define nRMP1 0x0
3097#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ 2599#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
3098#define nRMP2 0x0
3099#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ 2600#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
3100#define nRMP3 0x0
3101#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ 2601#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
3102#define nRMP4 0x0
3103#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ 2602#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
3104#define nRMP5 0x0
3105#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ 2603#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
3106#define nRMP6 0x0
3107#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ 2604#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
3108#define nRMP7 0x0
3109#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ 2605#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
3110#define nRMP8 0x0
3111#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ 2606#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
3112#define nRMP9 0x0
3113#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ 2607#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
3114#define nRMP10 0x0
3115#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ 2608#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
3116#define nRMP11 0x0
3117#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ 2609#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
3118#define nRMP12 0x0
3119#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ 2610#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
3120#define nRMP13 0x0
3121#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ 2611#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
3122#define nRMP14 0x0
3123#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ 2612#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
3124#define nRMP15 0x0
3125 2613
3126/* Bit masks for CAN0_RMP2 */ 2614/* Bit masks for CAN0_RMP2 */
3127 2615
3128#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ 2616#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
3129#define nRMP16 0x0
3130#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ 2617#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
3131#define nRMP17 0x0
3132#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ 2618#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
3133#define nRMP18 0x0
3134#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ 2619#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
3135#define nRMP19 0x0
3136#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ 2620#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
3137#define nRMP20 0x0
3138#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ 2621#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
3139#define nRMP21 0x0
3140#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ 2622#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
3141#define nRMP22 0x0
3142#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ 2623#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
3143#define nRMP23 0x0
3144#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ 2624#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
3145#define nRMP24 0x0
3146#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ 2625#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
3147#define nRMP25 0x0
3148#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ 2626#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
3149#define nRMP26 0x0
3150#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ 2627#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
3151#define nRMP27 0x0
3152#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ 2628#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
3153#define nRMP28 0x0
3154#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ 2629#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
3155#define nRMP29 0x0
3156#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ 2630#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
3157#define nRMP30 0x0
3158#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ 2631#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
3159#define nRMP31 0x0
3160 2632
3161/* Bit masks for CAN0_RML1 */ 2633/* Bit masks for CAN0_RML1 */
3162 2634
3163#define RML0 0x1 /* Mailbox 0 Receive Message Lost */ 2635#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
3164#define nRML0 0x0
3165#define RML1 0x2 /* Mailbox 1 Receive Message Lost */ 2636#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
3166#define nRML1 0x0
3167#define RML2 0x4 /* Mailbox 2 Receive Message Lost */ 2637#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
3168#define nRML2 0x0
3169#define RML3 0x8 /* Mailbox 3 Receive Message Lost */ 2638#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
3170#define nRML3 0x0
3171#define RML4 0x10 /* Mailbox 4 Receive Message Lost */ 2639#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
3172#define nRML4 0x0
3173#define RML5 0x20 /* Mailbox 5 Receive Message Lost */ 2640#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
3174#define nRML5 0x0
3175#define RML6 0x40 /* Mailbox 6 Receive Message Lost */ 2641#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
3176#define nRML6 0x0
3177#define RML7 0x80 /* Mailbox 7 Receive Message Lost */ 2642#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
3178#define nRML7 0x0
3179#define RML8 0x100 /* Mailbox 8 Receive Message Lost */ 2643#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
3180#define nRML8 0x0
3181#define RML9 0x200 /* Mailbox 9 Receive Message Lost */ 2644#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
3182#define nRML9 0x0
3183#define RML10 0x400 /* Mailbox 10 Receive Message Lost */ 2645#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
3184#define nRML10 0x0
3185#define RML11 0x800 /* Mailbox 11 Receive Message Lost */ 2646#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
3186#define nRML11 0x0
3187#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ 2647#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
3188#define nRML12 0x0
3189#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ 2648#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
3190#define nRML13 0x0
3191#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ 2649#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
3192#define nRML14 0x0
3193#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ 2650#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
3194#define nRML15 0x0
3195 2651
3196/* Bit masks for CAN0_RML2 */ 2652/* Bit masks for CAN0_RML2 */
3197 2653
3198#define RML16 0x1 /* Mailbox 16 Receive Message Lost */ 2654#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
3199#define nRML16 0x0
3200#define RML17 0x2 /* Mailbox 17 Receive Message Lost */ 2655#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
3201#define nRML17 0x0
3202#define RML18 0x4 /* Mailbox 18 Receive Message Lost */ 2656#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
3203#define nRML18 0x0
3204#define RML19 0x8 /* Mailbox 19 Receive Message Lost */ 2657#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
3205#define nRML19 0x0
3206#define RML20 0x10 /* Mailbox 20 Receive Message Lost */ 2658#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
3207#define nRML20 0x0
3208#define RML21 0x20 /* Mailbox 21 Receive Message Lost */ 2659#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
3209#define nRML21 0x0
3210#define RML22 0x40 /* Mailbox 22 Receive Message Lost */ 2660#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
3211#define nRML22 0x0
3212#define RML23 0x80 /* Mailbox 23 Receive Message Lost */ 2661#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
3213#define nRML23 0x0
3214#define RML24 0x100 /* Mailbox 24 Receive Message Lost */ 2662#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
3215#define nRML24 0x0
3216#define RML25 0x200 /* Mailbox 25 Receive Message Lost */ 2663#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
3217#define nRML25 0x0
3218#define RML26 0x400 /* Mailbox 26 Receive Message Lost */ 2664#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
3219#define nRML26 0x0
3220#define RML27 0x800 /* Mailbox 27 Receive Message Lost */ 2665#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
3221#define nRML27 0x0
3222#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ 2666#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
3223#define nRML28 0x0
3224#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ 2667#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
3225#define nRML29 0x0
3226#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ 2668#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
3227#define nRML30 0x0
3228#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ 2669#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
3229#define nRML31 0x0
3230 2670
3231/* Bit masks for CAN0_OPSS1 */ 2671/* Bit masks for CAN0_OPSS1 */
3232 2672
3233#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ 2673#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
3234#define nOPSS0 0x0
3235#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ 2674#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
3236#define nOPSS1 0x0
3237#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ 2675#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
3238#define nOPSS2 0x0
3239#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ 2676#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
3240#define nOPSS3 0x0
3241#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ 2677#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
3242#define nOPSS4 0x0
3243#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ 2678#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
3244#define nOPSS5 0x0
3245#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ 2679#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
3246#define nOPSS6 0x0
3247#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ 2680#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
3248#define nOPSS7 0x0
3249#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ 2681#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
3250#define nOPSS8 0x0
3251#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ 2682#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
3252#define nOPSS9 0x0
3253#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ 2683#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
3254#define nOPSS10 0x0
3255#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ 2684#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
3256#define nOPSS11 0x0
3257#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ 2685#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
3258#define nOPSS12 0x0
3259#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ 2686#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
3260#define nOPSS13 0x0
3261#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ 2687#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
3262#define nOPSS14 0x0
3263#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ 2688#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
3264#define nOPSS15 0x0
3265 2689
3266/* Bit masks for CAN0_OPSS2 */ 2690/* Bit masks for CAN0_OPSS2 */
3267 2691
3268#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ 2692#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
3269#define nOPSS16 0x0
3270#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ 2693#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
3271#define nOPSS17 0x0
3272#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ 2694#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
3273#define nOPSS18 0x0
3274#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ 2695#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
3275#define nOPSS19 0x0
3276#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ 2696#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
3277#define nOPSS20 0x0
3278#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ 2697#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
3279#define nOPSS21 0x0
3280#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ 2698#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
3281#define nOPSS22 0x0
3282#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ 2699#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
3283#define nOPSS23 0x0
3284#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ 2700#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
3285#define nOPSS24 0x0
3286#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ 2701#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
3287#define nOPSS25 0x0
3288#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ 2702#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
3289#define nOPSS26 0x0
3290#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ 2703#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
3291#define nOPSS27 0x0
3292#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ 2704#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
3293#define nOPSS28 0x0
3294#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ 2705#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
3295#define nOPSS29 0x0
3296#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ 2706#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
3297#define nOPSS30 0x0
3298#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ 2707#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
3299#define nOPSS31 0x0
3300 2708
3301/* Bit masks for CAN0_TRS1 */ 2709/* Bit masks for CAN0_TRS1 */
3302 2710
3303#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ 2711#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
3304#define nTRS0 0x0
3305#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ 2712#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
3306#define nTRS1 0x0
3307#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ 2713#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
3308#define nTRS2 0x0
3309#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ 2714#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
3310#define nTRS3 0x0
3311#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ 2715#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
3312#define nTRS4 0x0
3313#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ 2716#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
3314#define nTRS5 0x0
3315#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ 2717#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
3316#define nTRS6 0x0
3317#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ 2718#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
3318#define nTRS7 0x0
3319#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ 2719#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
3320#define nTRS8 0x0
3321#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ 2720#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
3322#define nTRS9 0x0
3323#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ 2721#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
3324#define nTRS10 0x0
3325#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ 2722#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
3326#define nTRS11 0x0
3327#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ 2723#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
3328#define nTRS12 0x0
3329#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ 2724#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
3330#define nTRS13 0x0
3331#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ 2725#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
3332#define nTRS14 0x0
3333#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ 2726#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
3334#define nTRS15 0x0
3335 2727
3336/* Bit masks for CAN0_TRS2 */ 2728/* Bit masks for CAN0_TRS2 */
3337 2729
3338#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ 2730#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
3339#define nTRS16 0x0
3340#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ 2731#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
3341#define nTRS17 0x0
3342#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ 2732#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
3343#define nTRS18 0x0
3344#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ 2733#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
3345#define nTRS19 0x0
3346#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ 2734#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
3347#define nTRS20 0x0
3348#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ 2735#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
3349#define nTRS21 0x0
3350#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ 2736#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
3351#define nTRS22 0x0
3352#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ 2737#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
3353#define nTRS23 0x0
3354#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ 2738#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
3355#define nTRS24 0x0
3356#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ 2739#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
3357#define nTRS25 0x0
3358#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ 2740#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
3359#define nTRS26 0x0
3360#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ 2741#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
3361#define nTRS27 0x0
3362#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ 2742#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
3363#define nTRS28 0x0
3364#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ 2743#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
3365#define nTRS29 0x0
3366#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ 2744#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
3367#define nTRS30 0x0
3368#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ 2745#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
3369#define nTRS31 0x0
3370 2746
3371/* Bit masks for CAN0_TRR1 */ 2747/* Bit masks for CAN0_TRR1 */
3372 2748
3373#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ 2749#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
3374#define nTRR0 0x0
3375#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ 2750#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
3376#define nTRR1 0x0
3377#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ 2751#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
3378#define nTRR2 0x0
3379#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ 2752#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
3380#define nTRR3 0x0
3381#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ 2753#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
3382#define nTRR4 0x0
3383#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ 2754#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
3384#define nTRR5 0x0
3385#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ 2755#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
3386#define nTRR6 0x0
3387#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ 2756#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
3388#define nTRR7 0x0
3389#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ 2757#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
3390#define nTRR8 0x0
3391#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ 2758#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
3392#define nTRR9 0x0
3393#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ 2759#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
3394#define nTRR10 0x0
3395#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ 2760#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
3396#define nTRR11 0x0
3397#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ 2761#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
3398#define nTRR12 0x0
3399#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ 2762#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
3400#define nTRR13 0x0
3401#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ 2763#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
3402#define nTRR14 0x0
3403#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ 2764#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
3404#define nTRR15 0x0
3405 2765
3406/* Bit masks for CAN0_TRR2 */ 2766/* Bit masks for CAN0_TRR2 */
3407 2767
3408#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ 2768#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
3409#define nTRR16 0x0
3410#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ 2769#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
3411#define nTRR17 0x0
3412#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ 2770#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
3413#define nTRR18 0x0
3414#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ 2771#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
3415#define nTRR19 0x0
3416#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ 2772#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
3417#define nTRR20 0x0
3418#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ 2773#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
3419#define nTRR21 0x0
3420#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ 2774#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
3421#define nTRR22 0x0
3422#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ 2775#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
3423#define nTRR23 0x0
3424#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ 2776#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
3425#define nTRR24 0x0
3426#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ 2777#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
3427#define nTRR25 0x0
3428#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ 2778#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
3429#define nTRR26 0x0
3430#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ 2779#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
3431#define nTRR27 0x0
3432#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ 2780#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
3433#define nTRR28 0x0
3434#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ 2781#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
3435#define nTRR29 0x0
3436#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ 2782#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
3437#define nTRR30 0x0
3438#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ 2783#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
3439#define nTRR31 0x0
3440 2784
3441/* Bit masks for CAN0_AA1 */ 2785/* Bit masks for CAN0_AA1 */
3442 2786
3443#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ 2787#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
3444#define nAA0 0x0
3445#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ 2788#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
3446#define nAA1 0x0
3447#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ 2789#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
3448#define nAA2 0x0
3449#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ 2790#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
3450#define nAA3 0x0
3451#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ 2791#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
3452#define nAA4 0x0
3453#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ 2792#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
3454#define nAA5 0x0
3455#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ 2793#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
3456#define nAA6 0x0
3457#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ 2794#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
3458#define nAA7 0x0
3459#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ 2795#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
3460#define nAA8 0x0
3461#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ 2796#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
3462#define nAA9 0x0
3463#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ 2797#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
3464#define nAA10 0x0
3465#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ 2798#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
3466#define nAA11 0x0
3467#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ 2799#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
3468#define nAA12 0x0
3469#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ 2800#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
3470#define nAA13 0x0
3471#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ 2801#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
3472#define nAA14 0x0
3473#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ 2802#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
3474#define nAA15 0x0
3475 2803
3476/* Bit masks for CAN0_AA2 */ 2804/* Bit masks for CAN0_AA2 */
3477 2805
3478#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ 2806#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
3479#define nAA16 0x0
3480#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ 2807#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
3481#define nAA17 0x0
3482#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ 2808#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
3483#define nAA18 0x0
3484#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ 2809#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
3485#define nAA19 0x0
3486#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ 2810#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
3487#define nAA20 0x0
3488#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ 2811#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
3489#define nAA21 0x0
3490#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ 2812#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
3491#define nAA22 0x0
3492#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ 2813#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
3493#define nAA23 0x0
3494#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ 2814#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
3495#define nAA24 0x0
3496#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ 2815#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
3497#define nAA25 0x0
3498#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ 2816#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
3499#define nAA26 0x0
3500#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ 2817#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
3501#define nAA27 0x0
3502#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ 2818#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
3503#define nAA28 0x0
3504#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ 2819#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
3505#define nAA29 0x0
3506#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ 2820#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
3507#define nAA30 0x0
3508#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ 2821#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
3509#define nAA31 0x0
3510 2822
3511/* Bit masks for CAN0_TA1 */ 2823/* Bit masks for CAN0_TA1 */
3512 2824
3513#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ 2825#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
3514#define nTA0 0x0
3515#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ 2826#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
3516#define nTA1 0x0
3517#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ 2827#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
3518#define nTA2 0x0
3519#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ 2828#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
3520#define nTA3 0x0
3521#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ 2829#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
3522#define nTA4 0x0
3523#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ 2830#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
3524#define nTA5 0x0
3525#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ 2831#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
3526#define nTA6 0x0
3527#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ 2832#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
3528#define nTA7 0x0
3529#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ 2833#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
3530#define nTA8 0x0
3531#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ 2834#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
3532#define nTA9 0x0
3533#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ 2835#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
3534#define nTA10 0x0
3535#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ 2836#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
3536#define nTA11 0x0
3537#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ 2837#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
3538#define nTA12 0x0
3539#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ 2838#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
3540#define nTA13 0x0
3541#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ 2839#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
3542#define nTA14 0x0
3543#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ 2840#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
3544#define nTA15 0x0
3545 2841
3546/* Bit masks for CAN0_TA2 */ 2842/* Bit masks for CAN0_TA2 */
3547 2843
3548#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ 2844#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
3549#define nTA16 0x0
3550#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ 2845#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
3551#define nTA17 0x0
3552#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ 2846#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
3553#define nTA18 0x0
3554#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ 2847#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
3555#define nTA19 0x0
3556#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ 2848#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
3557#define nTA20 0x0
3558#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ 2849#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
3559#define nTA21 0x0
3560#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ 2850#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
3561#define nTA22 0x0
3562#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ 2851#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
3563#define nTA23 0x0
3564#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ 2852#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
3565#define nTA24 0x0
3566#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ 2853#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
3567#define nTA25 0x0
3568#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ 2854#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
3569#define nTA26 0x0
3570#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ 2855#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
3571#define nTA27 0x0
3572#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ 2856#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
3573#define nTA28 0x0
3574#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ 2857#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
3575#define nTA29 0x0
3576#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ 2858#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
3577#define nTA30 0x0
3578#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ 2859#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
3579#define nTA31 0x0
3580 2860
3581/* Bit masks for CAN0_RFH1 */ 2861/* Bit masks for CAN0_RFH1 */
3582 2862
3583#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ 2863#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
3584#define nRFH0 0x0
3585#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ 2864#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
3586#define nRFH1 0x0
3587#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ 2865#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
3588#define nRFH2 0x0
3589#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ 2866#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
3590#define nRFH3 0x0
3591#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ 2867#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
3592#define nRFH4 0x0
3593#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ 2868#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
3594#define nRFH5 0x0
3595#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ 2869#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
3596#define nRFH6 0x0
3597#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ 2870#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
3598#define nRFH7 0x0
3599#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ 2871#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
3600#define nRFH8 0x0
3601#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ 2872#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
3602#define nRFH9 0x0
3603#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ 2873#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
3604#define nRFH10 0x0
3605#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ 2874#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
3606#define nRFH11 0x0
3607#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ 2875#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
3608#define nRFH12 0x0
3609#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ 2876#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
3610#define nRFH13 0x0
3611#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ 2877#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
3612#define nRFH14 0x0
3613#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ 2878#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
3614#define nRFH15 0x0
3615 2879
3616/* Bit masks for CAN0_RFH2 */ 2880/* Bit masks for CAN0_RFH2 */
3617 2881
3618#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ 2882#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
3619#define nRFH16 0x0
3620#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ 2883#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
3621#define nRFH17 0x0
3622#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ 2884#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
3623#define nRFH18 0x0
3624#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ 2885#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
3625#define nRFH19 0x0
3626#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ 2886#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
3627#define nRFH20 0x0
3628#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ 2887#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
3629#define nRFH21 0x0
3630#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ 2888#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
3631#define nRFH22 0x0
3632#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ 2889#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
3633#define nRFH23 0x0
3634#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ 2890#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
3635#define nRFH24 0x0
3636#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ 2891#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
3637#define nRFH25 0x0
3638#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ 2892#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
3639#define nRFH26 0x0
3640#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ 2893#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
3641#define nRFH27 0x0
3642#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ 2894#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
3643#define nRFH28 0x0
3644#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ 2895#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
3645#define nRFH29 0x0
3646#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ 2896#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
3647#define nRFH30 0x0
3648#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ 2897#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
3649#define nRFH31 0x0
3650 2898
3651/* Bit masks for CAN0_MBIM1 */ 2899/* Bit masks for CAN0_MBIM1 */
3652 2900
3653#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ 2901#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
3654#define nMBIM0 0x0
3655#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ 2902#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
3656#define nMBIM1 0x0
3657#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ 2903#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
3658#define nMBIM2 0x0
3659#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ 2904#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
3660#define nMBIM3 0x0
3661#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ 2905#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
3662#define nMBIM4 0x0
3663#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ 2906#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
3664#define nMBIM5 0x0
3665#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ 2907#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
3666#define nMBIM6 0x0
3667#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ 2908#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
3668#define nMBIM7 0x0
3669#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ 2909#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
3670#define nMBIM8 0x0
3671#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ 2910#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
3672#define nMBIM9 0x0
3673#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ 2911#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
3674#define nMBIM10 0x0
3675#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ 2912#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
3676#define nMBIM11 0x0
3677#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ 2913#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
3678#define nMBIM12 0x0
3679#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ 2914#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
3680#define nMBIM13 0x0
3681#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ 2915#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
3682#define nMBIM14 0x0
3683#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ 2916#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
3684#define nMBIM15 0x0
3685 2917
3686/* Bit masks for CAN0_MBIM2 */ 2918/* Bit masks for CAN0_MBIM2 */
3687 2919
3688#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ 2920#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
3689#define nMBIM16 0x0
3690#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ 2921#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
3691#define nMBIM17 0x0
3692#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ 2922#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3693#define nMBIM18 0x0
3694#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ 2923#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
3695#define nMBIM19 0x0
3696#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ 2924#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
3697#define nMBIM20 0x0
3698#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ 2925#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
3699#define nMBIM21 0x0
3700#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ 2926#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
3701#define nMBIM22 0x0
3702#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ 2927#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
3703#define nMBIM23 0x0
3704#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ 2928#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
3705#define nMBIM24 0x0
3706#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ 2929#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
3707#define nMBIM25 0x0
3708#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ 2930#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
3709#define nMBIM26 0x0
3710#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ 2931#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
3711#define nMBIM27 0x0
3712#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ 2932#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
3713#define nMBIM28 0x0
3714#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ 2933#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
3715#define nMBIM29 0x0
3716#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ 2934#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
3717#define nMBIM30 0x0
3718#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ 2935#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
3719#define nMBIM31 0x0
3720 2936
3721/* Bit masks for CAN0_MBTIF1 */ 2937/* Bit masks for CAN0_MBTIF1 */
3722 2938
3723#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ 2939#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3724#define nMBTIF0 0x0
3725#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ 2940#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3726#define nMBTIF1 0x0
3727#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ 2941#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3728#define nMBTIF2 0x0
3729#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ 2942#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3730#define nMBTIF3 0x0
3731#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ 2943#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3732#define nMBTIF4 0x0
3733#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ 2944#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3734#define nMBTIF5 0x0
3735#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ 2945#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3736#define nMBTIF6 0x0
3737#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ 2946#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3738#define nMBTIF7 0x0
3739#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ 2947#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3740#define nMBTIF8 0x0
3741#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ 2948#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3742#define nMBTIF9 0x0
3743#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ 2949#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3744#define nMBTIF10 0x0
3745#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ 2950#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3746#define nMBTIF11 0x0
3747#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ 2951#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3748#define nMBTIF12 0x0
3749#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ 2952#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3750#define nMBTIF13 0x0
3751#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ 2953#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3752#define nMBTIF14 0x0
3753#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ 2954#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3754#define nMBTIF15 0x0
3755 2955
3756/* Bit masks for CAN0_MBTIF2 */ 2956/* Bit masks for CAN0_MBTIF2 */
3757 2957
3758#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ 2958#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3759#define nMBTIF16 0x0
3760#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ 2959#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3761#define nMBTIF17 0x0
3762#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ 2960#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3763#define nMBTIF18 0x0
3764#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ 2961#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3765#define nMBTIF19 0x0
3766#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ 2962#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3767#define nMBTIF20 0x0
3768#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ 2963#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
3769#define nMBTIF21 0x0
3770#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ 2964#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
3771#define nMBTIF22 0x0
3772#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ 2965#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
3773#define nMBTIF23 0x0
3774#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ 2966#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
3775#define nMBTIF24 0x0
3776#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ 2967#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
3777#define nMBTIF25 0x0
3778#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ 2968#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
3779#define nMBTIF26 0x0
3780#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ 2969#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
3781#define nMBTIF27 0x0
3782#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ 2970#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
3783#define nMBTIF28 0x0
3784#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ 2971#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
3785#define nMBTIF29 0x0
3786#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ 2972#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
3787#define nMBTIF30 0x0
3788#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ 2973#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
3789#define nMBTIF31 0x0
3790 2974
3791/* Bit masks for CAN0_MBRIF1 */ 2975/* Bit masks for CAN0_MBRIF1 */
3792 2976
3793#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ 2977#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
3794#define nMBRIF0 0x0
3795#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ 2978#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
3796#define nMBRIF1 0x0
3797#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ 2979#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3798#define nMBRIF2 0x0
3799#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ 2980#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
3800#define nMBRIF3 0x0
3801#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ 2981#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
3802#define nMBRIF4 0x0
3803#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ 2982#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
3804#define nMBRIF5 0x0
3805#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ 2983#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
3806#define nMBRIF6 0x0
3807#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ 2984#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
3808#define nMBRIF7 0x0
3809#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ 2985#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
3810#define nMBRIF8 0x0
3811#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ 2986#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
3812#define nMBRIF9 0x0
3813#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ 2987#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
3814#define nMBRIF10 0x0
3815#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ 2988#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
3816#define nMBRIF11 0x0
3817#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ 2989#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
3818#define nMBRIF12 0x0
3819#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ 2990#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
3820#define nMBRIF13 0x0
3821#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ 2991#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
3822#define nMBRIF14 0x0
3823#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ 2992#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
3824#define nMBRIF15 0x0
3825 2993
3826/* Bit masks for CAN0_MBRIF2 */ 2994/* Bit masks for CAN0_MBRIF2 */
3827 2995
3828#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ 2996#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
3829#define nMBRIF16 0x0
3830#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ 2997#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
3831#define nMBRIF17 0x0
3832#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ 2998#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3833#define nMBRIF18 0x0
3834#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ 2999#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
3835#define nMBRIF19 0x0
3836#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ 3000#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
3837#define nMBRIF20 0x0
3838#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ 3001#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
3839#define nMBRIF21 0x0
3840#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ 3002#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
3841#define nMBRIF22 0x0
3842#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ 3003#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
3843#define nMBRIF23 0x0
3844#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ 3004#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
3845#define nMBRIF24 0x0
3846#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ 3005#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
3847#define nMBRIF25 0x0
3848#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ 3006#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
3849#define nMBRIF26 0x0
3850#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ 3007#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
3851#define nMBRIF27 0x0
3852#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ 3008#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
3853#define nMBRIF28 0x0
3854#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ 3009#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
3855#define nMBRIF29 0x0
3856#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ 3010#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
3857#define nMBRIF30 0x0
3858#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ 3011#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
3859#define nMBRIF31 0x0
3860 3012
3861/* Bit masks for EPPIx_STATUS */ 3013/* Bit masks for EPPIx_STATUS */
3862 3014
3863#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ 3015#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
3864#define nCFIFO_ERR 0x0
3865#define YFIFO_ERR 0x2 /* Luma FIFO Error */ 3016#define YFIFO_ERR 0x2 /* Luma FIFO Error */
3866#define nYFIFO_ERR 0x0
3867#define LTERR_OVR 0x4 /* Line Track Overflow */ 3017#define LTERR_OVR 0x4 /* Line Track Overflow */
3868#define nLTERR_OVR 0x0
3869#define LTERR_UNDR 0x8 /* Line Track Underflow */ 3018#define LTERR_UNDR 0x8 /* Line Track Underflow */
3870#define nLTERR_UNDR 0x0
3871#define FTERR_OVR 0x10 /* Frame Track Overflow */ 3019#define FTERR_OVR 0x10 /* Frame Track Overflow */
3872#define nFTERR_OVR 0x0
3873#define FTERR_UNDR 0x20 /* Frame Track Underflow */ 3020#define FTERR_UNDR 0x20 /* Frame Track Underflow */
3874#define nFTERR_UNDR 0x0
3875#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ 3021#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
3876#define nERR_NCOR 0x0
3877#define DMA1URQ 0x80 /* DMA1 Urgent Request */ 3022#define DMA1URQ 0x80 /* DMA1 Urgent Request */
3878#define nDMA1URQ 0x0
3879#define DMA0URQ 0x100 /* DMA0 Urgent Request */ 3023#define DMA0URQ 0x100 /* DMA0 Urgent Request */
3880#define nDMA0URQ 0x0
3881#define ERR_DET 0x4000 /* Preamble Error Detected */ 3024#define ERR_DET 0x4000 /* Preamble Error Detected */
3882#define nERR_DET 0x0
3883#define FLD 0x8000 /* Field */ 3025#define FLD 0x8000 /* Field */
3884#define nFLD 0x0
3885 3026
3886/* Bit masks for EPPIx_CONTROL */ 3027/* Bit masks for EPPIx_CONTROL */
3887 3028
3888#define EPPI_EN 0x1 /* Enable */ 3029#define EPPI_EN 0x1 /* Enable */
3889#define nEPPI_EN 0x0
3890#define EPPI_DIR 0x2 /* Direction */ 3030#define EPPI_DIR 0x2 /* Direction */
3891#define nEPPI_DIR 0x0
3892#define XFR_TYPE 0xc /* Operating Mode */ 3031#define XFR_TYPE 0xc /* Operating Mode */
3893#define FS_CFG 0x30 /* Frame Sync Configuration */ 3032#define FS_CFG 0x30 /* Frame Sync Configuration */
3894#define FLD_SEL 0x40 /* Field Select/Trigger */ 3033#define FLD_SEL 0x40 /* Field Select/Trigger */
3895#define nFLD_SEL 0x0
3896#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ 3034#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
3897#define nITU_TYPE 0x0
3898#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ 3035#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
3899#define nBLANKGEN 0x0
3900#define ICLKGEN 0x200 /* Internal Clock Generation */ 3036#define ICLKGEN 0x200 /* Internal Clock Generation */
3901#define nICLKGEN 0x0
3902#define IFSGEN 0x400 /* Internal Frame Sync Generation */ 3037#define IFSGEN 0x400 /* Internal Frame Sync Generation */
3903#define nIFSGEN 0x0
3904#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ 3038#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
3905#define POLS 0x6000 /* Frame Sync Polarity */ 3039#define POLS 0x6000 /* Frame Sync Polarity */
3906#define DLENGTH 0x38000 /* Data Length */ 3040#define DLENGTH 0x38000 /* Data Length */
3907#define SKIP_EN 0x40000 /* Skip Enable */ 3041#define SKIP_EN 0x40000 /* Skip Enable */
3908#define nSKIP_EN 0x0
3909#define SKIP_EO 0x80000 /* Skip Even or Odd */ 3042#define SKIP_EO 0x80000 /* Skip Even or Odd */
3910#define nSKIP_EO 0x0
3911#define PACKEN 0x100000 /* Packing/Unpacking Enable */ 3043#define PACKEN 0x100000 /* Packing/Unpacking Enable */
3912#define nPACKEN 0x0
3913#define SWAPEN 0x200000 /* Swap Enable */ 3044#define SWAPEN 0x200000 /* Swap Enable */
3914#define nSWAPEN 0x0
3915#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ 3045#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
3916#define nSIGN_EXT 0x0
3917#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ 3046#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
3918#define nSPLT_EVEN_ODD 0x0
3919#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ 3047#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
3920#define nSUBSPLT_ODD 0x0
3921#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ 3048#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
3922#define nDMACFG 0x0
3923#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ 3049#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
3924#define nRGB_FMT_EN 0x0
3925#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ 3050#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
3926#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ 3051#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
3927 3052
@@ -3951,60 +3076,36 @@
3951/* Bit masks for SPIx_CTL */ 3076/* Bit masks for SPIx_CTL */
3952 3077
3953#define SPE 0x4000 /* SPI Enable */ 3078#define SPE 0x4000 /* SPI Enable */
3954#define nSPE 0x0
3955#define WOM 0x2000 /* Write Open Drain Master */ 3079#define WOM 0x2000 /* Write Open Drain Master */
3956#define nWOM 0x0
3957#define MSTR 0x1000 /* Master Mode */ 3080#define MSTR 0x1000 /* Master Mode */
3958#define nMSTR 0x0
3959#define CPOL 0x800 /* Clock Polarity */ 3081#define CPOL 0x800 /* Clock Polarity */
3960#define nCPOL 0x0
3961#define CPHA 0x400 /* Clock Phase */ 3082#define CPHA 0x400 /* Clock Phase */
3962#define nCPHA 0x0
3963#define LSBF 0x200 /* LSB First */ 3083#define LSBF 0x200 /* LSB First */
3964#define nLSBF 0x0
3965#define SIZE 0x100 /* Size of Words */ 3084#define SIZE 0x100 /* Size of Words */
3966#define nSIZE 0x0
3967#define EMISO 0x20 /* Enable MISO Output */ 3085#define EMISO 0x20 /* Enable MISO Output */
3968#define nEMISO 0x0
3969#define PSSE 0x10 /* Slave-Select Enable */ 3086#define PSSE 0x10 /* Slave-Select Enable */
3970#define nPSSE 0x0
3971#define GM 0x8 /* Get More Data */ 3087#define GM 0x8 /* Get More Data */
3972#define nGM 0x0
3973#define SZ 0x4 /* Send Zero */ 3088#define SZ 0x4 /* Send Zero */
3974#define nSZ 0x0
3975#define TIMOD 0x3 /* Transfer Initiation Mode */ 3089#define TIMOD 0x3 /* Transfer Initiation Mode */
3976 3090
3977/* Bit masks for SPIx_FLG */ 3091/* Bit masks for SPIx_FLG */
3978 3092
3979#define FLS1 0x2 /* Slave Select Enable 1 */ 3093#define FLS1 0x2 /* Slave Select Enable 1 */
3980#define nFLS1 0x0
3981#define FLS2 0x4 /* Slave Select Enable 2 */ 3094#define FLS2 0x4 /* Slave Select Enable 2 */
3982#define nFLS2 0x0
3983#define FLS3 0x8 /* Slave Select Enable 3 */ 3095#define FLS3 0x8 /* Slave Select Enable 3 */
3984#define nFLS3 0x0
3985#define FLG1 0x200 /* Slave Select Value 1 */ 3096#define FLG1 0x200 /* Slave Select Value 1 */
3986#define nFLG1 0x0
3987#define FLG2 0x400 /* Slave Select Value 2 */ 3097#define FLG2 0x400 /* Slave Select Value 2 */
3988#define nFLG2 0x0
3989#define FLG3 0x800 /* Slave Select Value 3 */ 3098#define FLG3 0x800 /* Slave Select Value 3 */
3990#define nFLG3 0x0
3991 3099
3992/* Bit masks for SPIx_STAT */ 3100/* Bit masks for SPIx_STAT */
3993 3101
3994#define TXCOL 0x40 /* Transmit Collision Error */ 3102#define TXCOL 0x40 /* Transmit Collision Error */
3995#define nTXCOL 0x0
3996#define RXS 0x20 /* RDBR Data Buffer Status */ 3103#define RXS 0x20 /* RDBR Data Buffer Status */
3997#define nRXS 0x0
3998#define RBSY 0x10 /* Receive Error */ 3104#define RBSY 0x10 /* Receive Error */
3999#define nRBSY 0x0
4000#define TXS 0x8 /* TDBR Data Buffer Status */ 3105#define TXS 0x8 /* TDBR Data Buffer Status */
4001#define nTXS 0x0
4002#define TXE 0x4 /* Transmission Error */ 3106#define TXE 0x4 /* Transmission Error */
4003#define nTXE 0x0
4004#define MODF 0x2 /* Mode Fault Error */ 3107#define MODF 0x2 /* Mode Fault Error */
4005#define nMODF 0x0
4006#define SPIF 0x1 /* SPI Finished */ 3108#define SPIF 0x1 /* SPI Finished */
4007#define nSPIF 0x0
4008 3109
4009/* Bit masks for SPIx_TDBR */ 3110/* Bit masks for SPIx_TDBR */
4010 3111
@@ -4028,9 +3129,7 @@
4028 3129
4029#define PRESCALE 0x7f /* Prescale Value */ 3130#define PRESCALE 0x7f /* Prescale Value */
4030#define TWI_ENA 0x80 /* TWI Enable */ 3131#define TWI_ENA 0x80 /* TWI Enable */
4031#define nTWI_ENA 0x0
4032#define SCCB 0x200 /* Serial Camera Control Bus */ 3132#define SCCB 0x200 /* Serial Camera Control Bus */
4033#define nSCCB 0x0
4034 3133
4035/* Bit maskes for TWIx_CLKDIV */ 3134/* Bit maskes for TWIx_CLKDIV */
4036 3135
@@ -4040,13 +3139,9 @@
4040/* Bit maskes for TWIx_SLAVE_CTL */ 3139/* Bit maskes for TWIx_SLAVE_CTL */
4041 3140
4042#define SEN 0x1 /* Slave Enable */ 3141#define SEN 0x1 /* Slave Enable */
4043#define nSEN 0x0
4044#define STDVAL 0x4 /* Slave Transmit Data Valid */ 3142#define STDVAL 0x4 /* Slave Transmit Data Valid */
4045#define nSTDVAL 0x0
4046#define NAK 0x8 /* Not Acknowledge */ 3143#define NAK 0x8 /* Not Acknowledge */
4047#define nNAK 0x0
4048#define GEN 0x10 /* General Call Enable */ 3144#define GEN 0x10 /* General Call Enable */
4049#define nGEN 0x0
4050 3145
4051/* Bit maskes for TWIx_SLAVE_ADDR */ 3146/* Bit maskes for TWIx_SLAVE_ADDR */
4052 3147
@@ -4055,27 +3150,18 @@
4055/* Bit maskes for TWIx_SLAVE_STAT */ 3150/* Bit maskes for TWIx_SLAVE_STAT */
4056 3151
4057#define SDIR 0x1 /* Slave Transfer Direction */ 3152#define SDIR 0x1 /* Slave Transfer Direction */
4058#define nSDIR 0x0
4059#define GCALL 0x2 /* General Call */ 3153#define GCALL 0x2 /* General Call */
4060#define nGCALL 0x0
4061 3154
4062/* Bit maskes for TWIx_MASTER_CTL */ 3155/* Bit maskes for TWIx_MASTER_CTL */
4063 3156
4064#define MEN 0x1 /* Master Mode Enable */ 3157#define MEN 0x1 /* Master Mode Enable */
4065#define nMEN 0x0
4066#define MDIR 0x4 /* Master Transfer Direction */ 3158#define MDIR 0x4 /* Master Transfer Direction */
4067#define nMDIR 0x0
4068#define FAST 0x8 /* Fast Mode */ 3159#define FAST 0x8 /* Fast Mode */
4069#define nFAST 0x0
4070#define STOP 0x10 /* Issue Stop Condition */ 3160#define STOP 0x10 /* Issue Stop Condition */
4071#define nSTOP 0x0
4072#define RSTART 0x20 /* Repeat Start */ 3161#define RSTART 0x20 /* Repeat Start */
4073#define nRSTART 0x0
4074#define DCNT 0x3fc0 /* Data Transfer Count */ 3162#define DCNT 0x3fc0 /* Data Transfer Count */
4075#define SDAOVR 0x4000 /* Serial Data Override */ 3163#define SDAOVR 0x4000 /* Serial Data Override */
4076#define nSDAOVR 0x0
4077#define SCLOVR 0x8000 /* Serial Clock Override */ 3164#define SCLOVR 0x8000 /* Serial Clock Override */
4078#define nSCLOVR 0x0
4079 3165
4080/* Bit maskes for TWIx_MASTER_ADDR */ 3166/* Bit maskes for TWIx_MASTER_ADDR */
4081 3167
@@ -4084,34 +3170,21 @@
4084/* Bit maskes for TWIx_MASTER_STAT */ 3170/* Bit maskes for TWIx_MASTER_STAT */
4085 3171
4086#define MPROG 0x1 /* Master Transfer in Progress */ 3172#define MPROG 0x1 /* Master Transfer in Progress */
4087#define nMPROG 0x0
4088#define LOSTARB 0x2 /* Lost Arbitration */ 3173#define LOSTARB 0x2 /* Lost Arbitration */
4089#define nLOSTARB 0x0
4090#define ANAK 0x4 /* Address Not Acknowledged */ 3174#define ANAK 0x4 /* Address Not Acknowledged */
4091#define nANAK 0x0
4092#define DNAK 0x8 /* Data Not Acknowledged */ 3175#define DNAK 0x8 /* Data Not Acknowledged */
4093#define nDNAK 0x0
4094#define BUFRDERR 0x10 /* Buffer Read Error */ 3176#define BUFRDERR 0x10 /* Buffer Read Error */
4095#define nBUFRDERR 0x0
4096#define BUFWRERR 0x20 /* Buffer Write Error */ 3177#define BUFWRERR 0x20 /* Buffer Write Error */
4097#define nBUFWRERR 0x0
4098#define SDASEN 0x40 /* Serial Data Sense */ 3178#define SDASEN 0x40 /* Serial Data Sense */
4099#define nSDASEN 0x0
4100#define SCLSEN 0x80 /* Serial Clock Sense */ 3179#define SCLSEN 0x80 /* Serial Clock Sense */
4101#define nSCLSEN 0x0
4102#define BUSBUSY 0x100 /* Bus Busy */ 3180#define BUSBUSY 0x100 /* Bus Busy */
4103#define nBUSBUSY 0x0
4104 3181
4105/* Bit maskes for TWIx_FIFO_CTL */ 3182/* Bit maskes for TWIx_FIFO_CTL */
4106 3183
4107#define XMTFLUSH 0x1 /* Transmit Buffer Flush */ 3184#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
4108#define nXMTFLUSH 0x0
4109#define RCVFLUSH 0x2 /* Receive Buffer Flush */ 3185#define RCVFLUSH 0x2 /* Receive Buffer Flush */
4110#define nRCVFLUSH 0x0
4111#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ 3186#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
4112#define nXMTINTLEN 0x0
4113#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ 3187#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
4114#define nRCVINTLEN 0x0
4115 3188
4116/* Bit maskes for TWIx_FIFO_STAT */ 3189/* Bit maskes for TWIx_FIFO_STAT */
4117 3190
@@ -4121,40 +3194,24 @@
4121/* Bit maskes for TWIx_INT_MASK */ 3194/* Bit maskes for TWIx_INT_MASK */
4122 3195
4123#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ 3196#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
4124#define nSINITM 0x0
4125#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ 3197#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
4126#define nSCOMPM 0x0
4127#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ 3198#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
4128#define nSERRM 0x0
4129#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ 3199#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
4130#define nSOVFM 0x0
4131#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ 3200#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
4132#define nMCOMPM 0x0
4133#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ 3201#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
4134#define nMERRM 0x0
4135#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ 3202#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
4136#define nXMTSERVM 0x0
4137#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ 3203#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
4138#define nRCVSERVM 0x0
4139 3204
4140/* Bit maskes for TWIx_INT_STAT */ 3205/* Bit maskes for TWIx_INT_STAT */
4141 3206
4142#define SINIT 0x1 /* Slave Transfer Initiated */ 3207#define SINIT 0x1 /* Slave Transfer Initiated */
4143#define nSINIT 0x0
4144#define SCOMP 0x2 /* Slave Transfer Complete */ 3208#define SCOMP 0x2 /* Slave Transfer Complete */
4145#define nSCOMP 0x0
4146#define SERR 0x4 /* Slave Transfer Error */ 3209#define SERR 0x4 /* Slave Transfer Error */
4147#define nSERR 0x0
4148#define SOVF 0x8 /* Slave Overflow */ 3210#define SOVF 0x8 /* Slave Overflow */
4149#define nSOVF 0x0
4150#define MCOMP 0x10 /* Master Transfer Complete */ 3211#define MCOMP 0x10 /* Master Transfer Complete */
4151#define nMCOMP 0x0
4152#define MERR 0x20 /* Master Transfer Error */ 3212#define MERR 0x20 /* Master Transfer Error */
4153#define nMERR 0x0
4154#define XMTSERV 0x40 /* Transmit FIFO Service */ 3213#define XMTSERV 0x40 /* Transmit FIFO Service */
4155#define nXMTSERV 0x0
4156#define RCVSERV 0x80 /* Receive FIFO Service */ 3214#define RCVSERV 0x80 /* Receive FIFO Service */
4157#define nRCVSERV 0x0
4158 3215
4159/* Bit maskes for TWIx_XMT_DATA8 */ 3216/* Bit maskes for TWIx_XMT_DATA8 */
4160 3217
@@ -4175,81 +3232,51 @@
4175/* Bit masks for SPORTx_TCR1 */ 3232/* Bit masks for SPORTx_TCR1 */
4176 3233
4177#define TCKFE 0x4000 /* Clock Falling Edge Select */ 3234#define TCKFE 0x4000 /* Clock Falling Edge Select */
4178#define nTCKFE 0x0
4179#define LATFS 0x2000 /* Late Transmit Frame Sync */ 3235#define LATFS 0x2000 /* Late Transmit Frame Sync */
4180#define nLATFS 0x0
4181#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ 3236#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
4182#define nLTFS 0x0
4183#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ 3237#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
4184#define nDITFS 0x0
4185#define TFSR 0x400 /* Transmit Frame Sync Required Select */ 3238#define TFSR 0x400 /* Transmit Frame Sync Required Select */
4186#define nTFSR 0x0
4187#define ITFS 0x200 /* Internal Transmit Frame Sync Select */ 3239#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
4188#define nITFS 0x0
4189#define TLSBIT 0x10 /* Transmit Bit Order */ 3240#define TLSBIT 0x10 /* Transmit Bit Order */
4190#define nTLSBIT 0x0
4191#define TDTYPE 0xc /* Data Formatting Type Select */ 3241#define TDTYPE 0xc /* Data Formatting Type Select */
4192#define ITCLK 0x2 /* Internal Transmit Clock Select */ 3242#define ITCLK 0x2 /* Internal Transmit Clock Select */
4193#define nITCLK 0x0
4194#define TSPEN 0x1 /* Transmit Enable */ 3243#define TSPEN 0x1 /* Transmit Enable */
4195#define nTSPEN 0x0
4196 3244
4197/* Bit masks for SPORTx_TCR2 */ 3245/* Bit masks for SPORTx_TCR2 */
4198 3246
4199#define TRFST 0x400 /* Left/Right Order */ 3247#define TRFST 0x400 /* Left/Right Order */
4200#define nTRFST 0x0
4201#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ 3248#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
4202#define nTSFSE 0x0
4203#define TXSE 0x100 /* TxSEC Enable */ 3249#define TXSE 0x100 /* TxSEC Enable */
4204#define nTXSE 0x0
4205#define SLEN_T 0x1f /* SPORT Word Length */ 3250#define SLEN_T 0x1f /* SPORT Word Length */
4206 3251
4207/* Bit masks for SPORTx_RCR1 */ 3252/* Bit masks for SPORTx_RCR1 */
4208 3253
4209#define RCKFE 0x4000 /* Clock Falling Edge Select */ 3254#define RCKFE 0x4000 /* Clock Falling Edge Select */
4210#define nRCKFE 0x0
4211#define LARFS 0x2000 /* Late Receive Frame Sync */ 3255#define LARFS 0x2000 /* Late Receive Frame Sync */
4212#define nLARFS 0x0
4213#define LRFS 0x1000 /* Low Receive Frame Sync Select */ 3256#define LRFS 0x1000 /* Low Receive Frame Sync Select */
4214#define nLRFS 0x0
4215#define RFSR 0x400 /* Receive Frame Sync Required Select */ 3257#define RFSR 0x400 /* Receive Frame Sync Required Select */
4216#define nRFSR 0x0
4217#define IRFS 0x200 /* Internal Receive Frame Sync Select */ 3258#define IRFS 0x200 /* Internal Receive Frame Sync Select */
4218#define nIRFS 0x0
4219#define RLSBIT 0x10 /* Receive Bit Order */ 3259#define RLSBIT 0x10 /* Receive Bit Order */
4220#define nRLSBIT 0x0
4221#define RDTYPE 0xc /* Data Formatting Type Select */ 3260#define RDTYPE 0xc /* Data Formatting Type Select */
4222#define IRCLK 0x2 /* Internal Receive Clock Select */ 3261#define IRCLK 0x2 /* Internal Receive Clock Select */
4223#define nIRCLK 0x0
4224#define RSPEN 0x1 /* Receive Enable */ 3262#define RSPEN 0x1 /* Receive Enable */
4225#define nRSPEN 0x0
4226 3263
4227/* Bit masks for SPORTx_RCR2 */ 3264/* Bit masks for SPORTx_RCR2 */
4228 3265
4229#define RRFST 0x400 /* Left/Right Order */ 3266#define RRFST 0x400 /* Left/Right Order */
4230#define nRRFST 0x0
4231#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ 3267#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
4232#define nRSFSE 0x0
4233#define RXSE 0x100 /* RxSEC Enable */ 3268#define RXSE 0x100 /* RxSEC Enable */
4234#define nRXSE 0x0
4235#define SLEN_R 0x1f /* SPORT Word Length */ 3269#define SLEN_R 0x1f /* SPORT Word Length */
4236 3270
4237/* Bit masks for SPORTx_STAT */ 3271/* Bit masks for SPORTx_STAT */
4238 3272
4239#define TXHRE 0x40 /* Transmit Hold Register Empty */ 3273#define TXHRE 0x40 /* Transmit Hold Register Empty */
4240#define nTXHRE 0x0
4241#define TOVF 0x20 /* Sticky Transmit Overflow Status */ 3274#define TOVF 0x20 /* Sticky Transmit Overflow Status */
4242#define nTOVF 0x0
4243#define TUVF 0x10 /* Sticky Transmit Underflow Status */ 3275#define TUVF 0x10 /* Sticky Transmit Underflow Status */
4244#define nTUVF 0x0
4245#define TXF 0x8 /* Transmit FIFO Full Status */ 3276#define TXF 0x8 /* Transmit FIFO Full Status */
4246#define nTXF 0x0
4247#define ROVF 0x4 /* Sticky Receive Overflow Status */ 3277#define ROVF 0x4 /* Sticky Receive Overflow Status */
4248#define nROVF 0x0
4249#define RUVF 0x2 /* Sticky Receive Underflow Status */ 3278#define RUVF 0x2 /* Sticky Receive Underflow Status */
4250#define nRUVF 0x0
4251#define RXNE 0x1 /* Receive FIFO Not Empty Status */ 3279#define RXNE 0x1 /* Receive FIFO Not Empty Status */
4252#define nRXNE 0x0
4253 3280
4254/* Bit masks for SPORTx_MCMC1 */ 3281/* Bit masks for SPORTx_MCMC1 */
4255 3282
@@ -4260,13 +3287,9 @@
4260 3287
4261#define MFD 0xf000 /* Multi channel Frame Delay */ 3288#define MFD 0xf000 /* Multi channel Frame Delay */
4262#define FSDR 0x80 /* Frame Sync to Data Relationship */ 3289#define FSDR 0x80 /* Frame Sync to Data Relationship */
4263#define nFSDR 0x0
4264#define MCMEM 0x10 /* Multi channel Frame Mode Enable */ 3290#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
4265#define nMCMEM 0x0
4266#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ 3291#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
4267#define nMCDRXPE 0x0
4268#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ 3292#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
4269#define nMCDTXPE 0x0
4270#define MCCRM 0x3 /* 2X Clock Recovery Mode */ 3293#define MCCRM 0x3 /* 2X Clock Recovery Mode */
4271 3294
4272/* Bit masks for SPORTx_CHNL */ 3295/* Bit masks for SPORTx_CHNL */
@@ -4280,115 +3303,59 @@
4280#define WLS 0x3 /* Word Length Select */ 3303#define WLS 0x3 /* Word Length Select */
4281#endif 3304#endif
4282#define STB 0x4 /* Stop Bits */ 3305#define STB 0x4 /* Stop Bits */
4283#define nSTB 0x0
4284#define PEN 0x8 /* Parity Enable */ 3306#define PEN 0x8 /* Parity Enable */
4285#define nPEN 0x0
4286#define EPS 0x10 /* Even Parity Select */ 3307#define EPS 0x10 /* Even Parity Select */
4287#define nEPS 0x0
4288#define STP 0x20 /* Sticky Parity */ 3308#define STP 0x20 /* Sticky Parity */
4289#define nSTP 0x0
4290#define SB 0x40 /* Set Break */ 3309#define SB 0x40 /* Set Break */
4291#define nSB 0x0
4292 3310
4293/* Bit masks for UARTx_MCR */ 3311/* Bit masks for UARTx_MCR */
4294 3312
4295#define XOFF 0x1 /* Transmitter Off */ 3313#define XOFF 0x1 /* Transmitter Off */
4296#define nXOFF 0x0
4297#define MRTS 0x2 /* Manual Request To Send */ 3314#define MRTS 0x2 /* Manual Request To Send */
4298#define nMRTS 0x0
4299#define RFIT 0x4 /* Receive FIFO IRQ Threshold */ 3315#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
4300#define nRFIT 0x0
4301#define RFRT 0x8 /* Receive FIFO RTS Threshold */ 3316#define RFRT 0x8 /* Receive FIFO RTS Threshold */
4302#define nRFRT 0x0
4303#define LOOP_ENA 0x10 /* Loopback Mode Enable */ 3317#define LOOP_ENA 0x10 /* Loopback Mode Enable */
4304#define nLOOP_ENA 0x0
4305#define FCPOL 0x20 /* Flow Control Pin Polarity */ 3318#define FCPOL 0x20 /* Flow Control Pin Polarity */
4306#define nFCPOL 0x0
4307#define ARTS 0x40 /* Automatic Request To Send */ 3319#define ARTS 0x40 /* Automatic Request To Send */
4308#define nARTS 0x0
4309#define ACTS 0x80 /* Automatic Clear To Send */ 3320#define ACTS 0x80 /* Automatic Clear To Send */
4310#define nACTS 0x0
4311 3321
4312/* Bit masks for UARTx_LSR */ 3322/* Bit masks for UARTx_LSR */
4313 3323
4314#define DR 0x1 /* Data Ready */ 3324#define DR 0x1 /* Data Ready */
4315#define nDR 0x0
4316#define OE 0x2 /* Overrun Error */ 3325#define OE 0x2 /* Overrun Error */
4317#define nOE 0x0
4318#define PE 0x4 /* Parity Error */ 3326#define PE 0x4 /* Parity Error */
4319#define nPE 0x0
4320#define FE 0x8 /* Framing Error */ 3327#define FE 0x8 /* Framing Error */
4321#define nFE 0x0
4322#define BI 0x10 /* Break Interrupt */ 3328#define BI 0x10 /* Break Interrupt */
4323#define nBI 0x0
4324#define THRE 0x20 /* THR Empty */ 3329#define THRE 0x20 /* THR Empty */
4325#define nTHRE 0x0
4326#define TEMT 0x40 /* Transmitter Empty */ 3330#define TEMT 0x40 /* Transmitter Empty */
4327#define nTEMT 0x0
4328#define TFI 0x80 /* Transmission Finished Indicator */ 3331#define TFI 0x80 /* Transmission Finished Indicator */
4329#define nTFI 0x0
4330 3332
4331/* Bit masks for UARTx_MSR */ 3333/* Bit masks for UARTx_MSR */
4332 3334
4333#define SCTS 0x1 /* Sticky CTS */ 3335#define SCTS 0x1 /* Sticky CTS */
4334#define nSCTS 0x0
4335#define CTS 0x10 /* Clear To Send */ 3336#define CTS 0x10 /* Clear To Send */
4336#define nCTS 0x0
4337#define RFCS 0x20 /* Receive FIFO Count Status */ 3337#define RFCS 0x20 /* Receive FIFO Count Status */
4338#define nRFCS 0x0 3338
4339 3339/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
4340/* Bit masks for UARTx_IER_SET */ 3340
4341 3341#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
4342#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ 3342#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
4343#define nERBFI_S 0x0 3343#define ELSI 0x4 /* Enable Receive Status Interrupt */
4344#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ 3344#define EDSSI 0x8 /* Enable Modem Status Interrupt */
4345#define nETBEI_S 0x0 3345#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4346#define ELSI_S 0x4 /* Enable Receive Status Interrupt */ 3346#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
4347#define nELSI_S 0x0 3347#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
4348#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */
4349#define nEDSSI_S 0x0
4350#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4351#define nEDTPTI_S 0x0
4352#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */
4353#define nETFI_S 0x0
4354#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */
4355#define nERFCI_S 0x0
4356
4357/* Bit masks for UARTx_IER_CLEAR */
4358
4359#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */
4360#define nERBFI_C 0x0
4361#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */
4362#define nETBEI_C 0x0
4363#define ELSI_C 0x4 /* Enable Receive Status Interrupt */
4364#define nELSI_C 0x0
4365#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */
4366#define nEDSSI_C 0x0
4367#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4368#define nEDTPTI_C 0x0
4369#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */
4370#define nETFI_C 0x0
4371#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */
4372#define nERFCI_C 0x0
4373 3348
4374/* Bit masks for UARTx_GCTL */ 3349/* Bit masks for UARTx_GCTL */
4375 3350
4376#define UCEN 0x1 /* UART Enable */ 3351#define UCEN 0x1 /* UART Enable */
4377#define nUCEN 0x0
4378#define IREN 0x2 /* IrDA Mode Enable */ 3352#define IREN 0x2 /* IrDA Mode Enable */
4379#define nIREN 0x0
4380#define TPOLC 0x4 /* IrDA TX Polarity Change */ 3353#define TPOLC 0x4 /* IrDA TX Polarity Change */
4381#define nTPOLC 0x0
4382#define RPOLC 0x8 /* IrDA RX Polarity Change */ 3354#define RPOLC 0x8 /* IrDA RX Polarity Change */
4383#define nRPOLC 0x0
4384#define FPE 0x10 /* Force Parity Error */ 3355#define FPE 0x10 /* Force Parity Error */
4385#define nFPE 0x0
4386#define FFE 0x20 /* Force Framing Error */ 3356#define FFE 0x20 /* Force Framing Error */
4387#define nFFE 0x0
4388#define EDBO 0x40 /* Enable Divide-by-One */ 3357#define EDBO 0x40 /* Enable Divide-by-One */
4389#define nEDBO 0x0
4390#define EGLSI 0x80 /* Enable Global LS Interrupt */ 3358#define EGLSI 0x80 /* Enable Global LS Interrupt */
4391#define nEGLSI 0x0
4392 3359
4393 3360
4394/* ******************************************* */ 3361/* ******************************************* */
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
index 5a334c813c79..fcc8b4c34c6a 100644
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -44,7 +44,6 @@
44#define CH_UART1_TX 9 44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10 45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11 46#define CH_ATAPI_TX 11
47
48#define CH_EPPI0 12 47#define CH_EPPI0 12
49#define CH_EPPI1 13 48#define CH_EPPI1 13
50#define CH_EPPI2 14 49#define CH_EPPI2 14
@@ -58,6 +57,17 @@
58#define CH_SDH 22 57#define CH_SDH 22
59#define CH_SPI2 23 58#define CH_SPI2 23
60 59
61#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2 60#define CH_MEM_STREAM0_DEST 24
61#define CH_MEM_STREAM0_SRC 25
62#define CH_MEM_STREAM1_DEST 26
63#define CH_MEM_STREAM1_SRC 27
64#define CH_MEM_STREAM2_DEST 28
65#define CH_MEM_STREAM2_SRC 29
66#define CH_MEM_STREAM3_DEST 30
67#define CH_MEM_STREAM3_SRC 31
68
69#define MAX_BLACKFIN_DMA_CHANNEL 32
62 70
71extern int channel2irq(unsigned int channel);
72extern struct dma_register *base_addr[];
63#endif 73#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
new file mode 100644
index 000000000000..45289425ce59
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/gpio.h
@@ -0,0 +1,212 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30
31
32#define GPIO_PA0 0
33#define GPIO_PA1 1
34#define GPIO_PA2 2
35#define GPIO_PA3 3
36#define GPIO_PA4 4
37#define GPIO_PA5 5
38#define GPIO_PA6 6
39#define GPIO_PA7 7
40#define GPIO_PA8 8
41#define GPIO_PA9 9
42#define GPIO_PA10 10
43#define GPIO_PA11 11
44#define GPIO_PA12 12
45#define GPIO_PA13 13
46#define GPIO_PA14 14
47#define GPIO_PA15 15
48#define GPIO_PB0 16
49#define GPIO_PB1 17
50#define GPIO_PB2 18
51#define GPIO_PB3 19
52#define GPIO_PB4 20
53#define GPIO_PB5 21
54#define GPIO_PB6 22
55#define GPIO_PB7 23
56#define GPIO_PB8 24
57#define GPIO_PB9 25
58#define GPIO_PB10 26
59#define GPIO_PB11 27
60#define GPIO_PB12 28
61#define GPIO_PB13 29
62#define GPIO_PB14 30
63#define GPIO_PB15 31 /* N/A */
64#define GPIO_PC0 32
65#define GPIO_PC1 33
66#define GPIO_PC2 34
67#define GPIO_PC3 35
68#define GPIO_PC4 36
69#define GPIO_PC5 37
70#define GPIO_PC6 38
71#define GPIO_PC7 39
72#define GPIO_PC8 40
73#define GPIO_PC9 41
74#define GPIO_PC10 42
75#define GPIO_PC11 43
76#define GPIO_PC12 44
77#define GPIO_PC13 45
78#define GPIO_PC14 46 /* N/A */
79#define GPIO_PC15 47 /* N/A */
80#define GPIO_PD0 48
81#define GPIO_PD1 49
82#define GPIO_PD2 50
83#define GPIO_PD3 51
84#define GPIO_PD4 52
85#define GPIO_PD5 53
86#define GPIO_PD6 54
87#define GPIO_PD7 55
88#define GPIO_PD8 56
89#define GPIO_PD9 57
90#define GPIO_PD10 58
91#define GPIO_PD11 59
92#define GPIO_PD12 60
93#define GPIO_PD13 61
94#define GPIO_PD14 62
95#define GPIO_PD15 63
96#define GPIO_PE0 64
97#define GPIO_PE1 65
98#define GPIO_PE2 66
99#define GPIO_PE3 67
100#define GPIO_PE4 68
101#define GPIO_PE5 69
102#define GPIO_PE6 70
103#define GPIO_PE7 71
104#define GPIO_PE8 72
105#define GPIO_PE9 73
106#define GPIO_PE10 74
107#define GPIO_PE11 75
108#define GPIO_PE12 76
109#define GPIO_PE13 77
110#define GPIO_PE14 78
111#define GPIO_PE15 79
112#define GPIO_PF0 80
113#define GPIO_PF1 81
114#define GPIO_PF2 82
115#define GPIO_PF3 83
116#define GPIO_PF4 84
117#define GPIO_PF5 85
118#define GPIO_PF6 86
119#define GPIO_PF7 87
120#define GPIO_PF8 88
121#define GPIO_PF9 89
122#define GPIO_PF10 90
123#define GPIO_PF11 91
124#define GPIO_PF12 92
125#define GPIO_PF13 93
126#define GPIO_PF14 94
127#define GPIO_PF15 95
128#define GPIO_PG0 96
129#define GPIO_PG1 97
130#define GPIO_PG2 98
131#define GPIO_PG3 99
132#define GPIO_PG4 100
133#define GPIO_PG5 101
134#define GPIO_PG6 102
135#define GPIO_PG7 103
136#define GPIO_PG8 104
137#define GPIO_PG9 105
138#define GPIO_PG10 106
139#define GPIO_PG11 107
140#define GPIO_PG12 108
141#define GPIO_PG13 109
142#define GPIO_PG14 110
143#define GPIO_PG15 111
144#define GPIO_PH0 112
145#define GPIO_PH1 113
146#define GPIO_PH2 114
147#define GPIO_PH3 115
148#define GPIO_PH4 116
149#define GPIO_PH5 117
150#define GPIO_PH6 118
151#define GPIO_PH7 119
152#define GPIO_PH8 120
153#define GPIO_PH9 121
154#define GPIO_PH10 122
155#define GPIO_PH11 123
156#define GPIO_PH12 124
157#define GPIO_PH13 125
158#define GPIO_PH14 126 /* N/A */
159#define GPIO_PH15 127 /* N/A */
160#define GPIO_PI0 128
161#define GPIO_PI1 129
162#define GPIO_PI2 130
163#define GPIO_PI3 131
164#define GPIO_PI4 132
165#define GPIO_PI5 133
166#define GPIO_PI6 134
167#define GPIO_PI7 135
168#define GPIO_PI8 136
169#define GPIO_PI9 137
170#define GPIO_PI10 138
171#define GPIO_PI11 139
172#define GPIO_PI12 140
173#define GPIO_PI13 141
174#define GPIO_PI14 142
175#define GPIO_PI15 143
176#define GPIO_PJ0 144
177#define GPIO_PJ1 145
178#define GPIO_PJ2 146
179#define GPIO_PJ3 147
180#define GPIO_PJ4 148
181#define GPIO_PJ5 149
182#define GPIO_PJ6 150
183#define GPIO_PJ7 151
184#define GPIO_PJ8 152
185#define GPIO_PJ9 153
186#define GPIO_PJ10 154
187#define GPIO_PJ11 155
188#define GPIO_PJ12 156
189#define GPIO_PJ13 157
190#define GPIO_PJ14 158
191#define GPIO_PJ15 159
192
193#define MAX_BLACKFIN_GPIOS 160
194
195struct gpio_port_t {
196 unsigned short port_fer;
197 unsigned short dummy1;
198 unsigned short port_data;
199 unsigned short dummy2;
200 unsigned short port_set;
201 unsigned short dummy3;
202 unsigned short port_clear;
203 unsigned short dummy4;
204 unsigned short port_dir_set;
205 unsigned short dummy5;
206 unsigned short port_dir_clear;
207 unsigned short dummy6;
208 unsigned short port_inen;
209 unsigned short dummy7;
210 unsigned int port_mux;
211};
212
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index a7f6703ea1dd..93f5db0f4657 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -51,7 +51,7 @@ Events (highest priority) EMU 0
51 (lowest priority) IVG15 32 * 51 (lowest priority) IVG15 32 *
52 */ 52 */
53 53
54#define NR_PERI_INTS 32 54#define NR_PERI_INTS (32 * 3)
55 55
56/* The ABSTRACT IRQ definitions */ 56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/ 57/** the first seven of the following are fixed, the rest you change if you need to **/
@@ -92,7 +92,7 @@ Events (highest priority) EMU 0
92#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ 92#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ 93#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ 94#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */ 95#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
96#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ 96#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ 97#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ 98#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
@@ -102,8 +102,8 @@ Events (highest priority) EMU 0
102#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ 102#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
103#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ 103#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
104#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ 104#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
105#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ 105#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
106#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ 106#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
107#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ 107#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
108#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ 108#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
109#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ 109#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
@@ -143,14 +143,14 @@ Events (highest priority) EMU 0
143#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ 143#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
144#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ 144#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
145#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ 145#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
146#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */ 146#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
147#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */ 147#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
148#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */ 148#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
149#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */ 149#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
150#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */ 150#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
151#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */ 151#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
152#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */ 152#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
153#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */ 153#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
154#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ 154#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
155#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ 155#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
156 156
@@ -248,9 +248,9 @@ Events (highest priority) EMU 0
248 248
249 249
250#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 250#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
251#define NR_IRQS (IRQ_PH15+1) 251#define NR_IRQS (IRQ_PE15+1)
252#else 252#else
253#define NR_IRQS (IRQ_UART1_ERROR+1) 253#define NR_IRQS (SYS_IRQS+1)
254#endif 254#endif
255 255
256#define IVG7 7 256#define IVG7 7
@@ -263,44 +263,116 @@ Events (highest priority) EMU 0
263#define IVG14 14 263#define IVG14 14
264#define IVG15 15 264#define IVG15 15
265 265
266/* IAR0 BIT FIELDS*/ 266/* IAR0 BIT FIELDS */
267#define IRQ_PLL_WAKEUP_POS 0 267#define IRQ_PLL_WAKEUP_POS 0
268#define IRQ_DMA_ERROR_POS 4 268#define IRQ_DMAC0_ERR_POS 4
269#define IRQ_ERROR_POS 8 269#define IRQ_EPPI0_ERR_POS 8
270#define IRQ_RTC_POS 12 270#define IRQ_SPORT0_ERR_POS 12
271#define IRQ_PPI_POS 16 271#define IRQ_SPORT1_ERR_POS 16
272#define IRQ_SPORT0_RX_POS 20 272#define IRQ_SPI0_ERR_POS 20
273#define IRQ_SPORT0_TX_POS 24 273#define IRQ_UART0_ERR_POS 24
274#define IRQ_SPORT1_RX_POS 28 274#define IRQ_RTC_POS 28
275 275
276/* IAR1 BIT FIELDS*/ 276/* IAR1 BIT FIELDS */
277#define IRQ_SPORT1_TX_POS 0 277#define IRQ_EPPI0_POS 0
278#define IRQ_TWI_POS 4 278#define IRQ_SPORT0_RX_POS 4
279#define IRQ_SPI_POS 8 279#define IRQ_SPORT0_TX_POS 8
280#define IRQ_UART0_RX_POS 12 280#define IRQ_SPORT1_RX_POS 12
281#define IRQ_UART0_TX_POS 16 281#define IRQ_SPORT1_TX_POS 16
282#define IRQ_UART1_RX_POS 20 282#define IRQ_SPI0_POS 20
283#define IRQ_UART1_TX_POS 24 283#define IRQ_UART0_RX_POS 24
284#define IRQ_CAN_RX_POS 28 284#define IRQ_UART0_TX_POS 28
285 285
286/* IAR2 BIT FIELDS*/ 286/* IAR2 BIT FIELDS */
287#define IRQ_CAN_TX_POS 0 287#define IRQ_TIMER8_POS 0
288#define IRQ_MAC_RX_POS 4 288#define IRQ_TIMER9_POS 4
289#define IRQ_MAC_TX_POS 8 289#define IRQ_TIMER10_POS 8
290#define IRQ_TMR0_POS 12 290#define IRQ_PINT0_POS 12
291#define IRQ_TMR1_POS 16 291#define IRQ_PINT1_POS 16
292#define IRQ_TMR2_POS 20 292#define IRQ_MDMAS0_POS 20
293#define IRQ_TMR3_POS 24 293#define IRQ_MDMAS1_POS 24
294#define IRQ_TMR4_POS 28 294#define IRQ_WATCHDOG_POS 28
295 295
296/* IAR3 BIT FIELDS*/ 296/* IAR3 BIT FIELDS */
297#define IRQ_TMR5_POS 0 297#define IRQ_DMAC1_ERR_POS 0
298#define IRQ_TMR6_POS 4 298#define IRQ_SPORT2_ERR_POS 4
299#define IRQ_TMR7_POS 8 299#define IRQ_SPORT3_ERR_POS 8
300#define IRQ_PROG_INTA_POS 12 300#define IRQ_MXVR_DATA_POS 12
301#define IRQ_PORTG_INTB_POS 16 301#define IRQ_SPI1_ERR_POS 16
302#define IRQ_MEM_DMA0_POS 20 302#define IRQ_SPI2_ERR_POS 20
303#define IRQ_MEM_DMA1_POS 24 303#define IRQ_UART1_ERR_POS 24
304#define IRQ_WATCH_POS 28 304#define IRQ_UART2_ERR_POS 28
305 305
306#endif /* _BF537_IRQ_H_ */ 306/* IAR4 BIT FILEDS */
307#define IRQ_CAN0_ERR_POS 0
308#define IRQ_SPORT2_RX_POS 4
309#define IRQ_SPORT2_TX_POS 8
310#define IRQ_SPORT3_RX_POS 12
311#define IRQ_SPORT3_TX_POS 16
312#define IRQ_EPPI1_POS 20
313#define IRQ_EPPI2_POS 24
314#define IRQ_SPI1_POS 28
315
316/* IAR5 BIT FIELDS */
317#define IRQ_SPI2_POS 0
318#define IRQ_UART1_RX_POS 4
319#define IRQ_UART1_TX_POS 8
320#define IRQ_ATAPI_RX_POS 12
321#define IRQ_ATAPI_TX_POS 16
322#define IRQ_TWI0_POS 20
323#define IRQ_TWI1_POS 24
324#define IRQ_CAN0_RX_POS 28
325
326/* IAR6 BIT FIELDS */
327#define IRQ_CAN0_TX_POS 0
328#define IRQ_MDMAS2_POS 4
329#define IRQ_MDMAS3_POS 8
330#define IRQ_MXVR_ERR_POS 12
331#define IRQ_MXVR_MSG_POS 16
332#define IRQ_MXVR_PKT_POS 20
333#define IRQ_EPPI1_ERR_POS 24
334#define IRQ_EPPI2_ERR_POS 28
335
336/* IAR7 BIT FIELDS */
337#define IRQ_UART3_ERR_POS 0
338#define IRQ_HOST_ERR_POS 4
339#define IRQ_PIXC_ERR_POS 12
340#define IRQ_NFC_ERR_POS 16
341#define IRQ_ATAPI_ERR_POS 20
342#define IRQ_CAN1_ERR_POS 24
343#define IRQ_HS_DMA_ERR_POS 28
344
345/* IAR8 BIT FIELDS */
346#define IRQ_PIXC_IN0_POS 0
347#define IRQ_PIXC_IN1_POS 4
348#define IRQ_PIXC_OUT_POS 8
349#define IRQ_SDH_POS 12
350#define IRQ_CNT_POS 16
351#define IRQ_KEY_POS 20
352#define IRQ_CAN1_RX_POS 24
353#define IRQ_CAN1_TX_POS 28
354
355/* IAR9 BIT FIELDS */
356#define IRQ_SDH_MASK0_POS 0
357#define IRQ_SDH_MASK1_POS 4
358#define IRQ_USB_INT0_POS 12
359#define IRQ_USB_INT1_POS 16
360#define IRQ_USB_INT2_POS 20
361#define IRQ_USB_DMA_POS 24
362#define IRQ_OTPSEC_POS 28
363
364/* IAR10 BIT FIELDS */
365#define IRQ_TIMER0_POS 24
366#define IRQ_TIMER1_POS 28
367
368/* IAR11 BIT FIELDS */
369#define IRQ_TIMER2_POS 0
370#define IRQ_TIMER3_POS 4
371#define IRQ_TIMER4_POS 8
372#define IRQ_TIMER5_POS 12
373#define IRQ_TIMER6_POS 16
374#define IRQ_TIMER7_POS 20
375#define IRQ_PINT2_POS 24
376#define IRQ_PINT3_POS 28
377
378#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
index 21d982003e75..766334b7d8ab 100644
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -32,4 +32,7 @@
32#define CH_IMEM_STREAM1_SRC 34 32#define CH_IMEM_STREAM1_SRC 34
33#define CH_IMEM_STREAM1_DEST 35 33#define CH_IMEM_STREAM1_DEST 35
34 34
35extern int channel2irq(unsigned int channel);
36extern struct dma_register *base_addr[];
37
35#endif 38#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 10:15:02 -0400