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authorPaul Mundt <lethal@linux-sh.org>2007-11-19 04:26:19 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:18:47 -0500
commit249cfea914002baac0af4b080306e6b820cd86b2 (patch)
tree32102587d3cd80986274db5deaee2ab5b7f5adab /include
parent2b6a8d455b1368d769da234336314b8364feb781 (diff)
sh: Split out pgtable.h in to _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-sh/page.h10
-rw-r--r--include/asm-sh/pgtable.h491
-rw-r--r--include/asm-sh/pgtable_32.h473
-rw-r--r--include/asm-sh/pgtable_64.h (renamed from include/asm-sh64/pgtable.h)234
4 files changed, 511 insertions, 697 deletions
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index d0273dbce6be..93a89841227f 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -96,12 +96,18 @@ typedef struct { unsigned long long pgd; } pgd_t;
96 ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) 96 ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
97#define __pte(x) \ 97#define __pte(x) \
98 ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) 98 ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
99#else 99#elif defined(CONFIG_SUPERH32)
100typedef struct { unsigned long pte_low; } pte_t; 100typedef struct { unsigned long pte_low; } pte_t;
101typedef struct { unsigned long pgprot; } pgprot_t; 101typedef struct { unsigned long pgprot; } pgprot_t;
102typedef struct { unsigned long pgd; } pgd_t; 102typedef struct { unsigned long pgd; } pgd_t;
103#define pte_val(x) ((x).pte_low) 103#define pte_val(x) ((x).pte_low)
104#define __pte(x) ((pte_t) { (x) } ) 104#define __pte(x) ((pte_t) { (x) } )
105#else
106typedef struct { unsigned long long pte_low; } pte_t;
107typedef struct { unsigned long pgprot; } pgprot_t;
108typedef struct { unsigned long pgd; } pgd_t;
109#define pte_val(x) ((x).pte_low)
110#define __pte(x) ((pte_t) { (x) } )
105#endif 111#endif
106 112
107#define pgd_val(x) ((x).pgd) 113#define pgd_val(x) ((x).pgd)
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index b0bb76a6864f..5a800c69e049 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -3,7 +3,7 @@
3 * use the SuperH page table tree. 3 * use the SuperH page table tree.
4 * 4 *
5 * Copyright (C) 1999 Niibe Yutaka 5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2005 Paul Mundt 6 * Copyright (C) 2002 - 2007 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this 9 * Public License. See the file "COPYING" in the main directory of this
@@ -78,278 +78,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
78#endif 78#endif
79#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 79#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
80 80
81/* 81#if defined(CONFIG_SUPERH32)
82 * Linux PTEL encoding. 82#include <asm/pgtable_32.h>
83 *
84 * Hardware and software bit definitions for the PTEL value (see below for
85 * notes on SH-X2 MMUs and 64-bit PTEs):
86 *
87 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
88 *
89 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
90 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
91 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
92 *
93 * In order to keep this relatively clean, do not use these for defining
94 * SH-3 specific flags until all of the other unused bits have been
95 * exhausted.
96 *
97 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
98 *
99 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
100 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
101 *
102 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
103 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
104 *
105 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
106 *
107 * SH-X2 MMUs and extended PTEs
108 *
109 * SH-X2 supports an extended mode TLB with split data arrays due to the
110 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
111 * SZ bit placeholders still exist in data array 1, but are implemented as
112 * reserved bits, with the real logic existing in data array 2.
113 *
114 * The downside to this is that we can no longer fit everything in to a 32-bit
115 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
116 * side, this gives us quite a few spare bits to play with for future usage.
117 */
118/* Legacy and compat mode bits */
119#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
120#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
121#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
122#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
123#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
124#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
125#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
126#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
127#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
128#define _PAGE_PROTNONE 0x200 /* software: if not present */
129#define _PAGE_ACCESSED 0x400 /* software: page referenced */
130#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
131
132#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
133#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
134
135/* Extended mode bits */
136#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
137#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
138#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
139#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
140
141#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
142#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
143#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
144
145#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
146#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
147#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
148
149/* Wrapper for extended mode pgprot twiddling */
150#define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
151
152/* software: moves to PTEA.TC (Timing Control) */
153#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
154#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
155
156/* software: moves to PTEA.SA[2:0] (Space Attributes) */
157#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
158#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
159#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
160#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
161#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
162#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
163#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
164
165/* Mask which drops unused bits from the PTEL value */
166#if defined(CONFIG_CPU_SH3)
167#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
168 _PAGE_FILE | _PAGE_SZ1 | \
169 _PAGE_HW_SHARED)
170#elif defined(CONFIG_X2TLB)
171/* Get rid of the legacy PR/SZ bits when using extended mode */
172#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \
173 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
174#else
175#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
176#endif
177
178#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
179
180/* Hardware flags, page size encoding */
181#if defined(CONFIG_X2TLB)
182# if defined(CONFIG_PAGE_SIZE_4KB)
183# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
184# elif defined(CONFIG_PAGE_SIZE_8KB)
185# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
186# elif defined(CONFIG_PAGE_SIZE_64KB)
187# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
188# endif
189#else
190# if defined(CONFIG_PAGE_SIZE_4KB)
191# define _PAGE_FLAGS_HARD _PAGE_SZ0
192# elif defined(CONFIG_PAGE_SIZE_64KB)
193# define _PAGE_FLAGS_HARD _PAGE_SZ1
194# endif
195#endif
196
197#if defined(CONFIG_X2TLB)
198# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
199# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
200# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
201# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
202# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
203# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
204# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
205# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
206# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
207# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
208# endif
209#else 83#else
210# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 84#include <asm/pgtable_64.h>
211# define _PAGE_SZHUGE (_PAGE_SZ1)
212# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
213# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
214# endif
215#endif
216
217/*
218 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
219 * to make pte_mkhuge() happy.
220 */
221#ifndef _PAGE_SZHUGE
222# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
223#endif
224
225#define _PAGE_CHG_MASK \
226 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
227
228#ifndef __ASSEMBLY__
229
230#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
231#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
232 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
233
234#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
235 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
236 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
237 _PAGE_EXT_KERN_WRITE | \
238 _PAGE_EXT_USER_READ | \
239 _PAGE_EXT_USER_WRITE))
240
241#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
242 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
243 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
244 _PAGE_EXT_KERN_READ | \
245 _PAGE_EXT_USER_EXEC | \
246 _PAGE_EXT_USER_READ))
247
248#define PAGE_COPY PAGE_EXECREAD
249
250#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
251 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
252 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
253 _PAGE_EXT_USER_READ))
254
255#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
256 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
257 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
258 _PAGE_EXT_USER_WRITE))
259
260#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
261 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
262 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
263 _PAGE_EXT_KERN_READ | \
264 _PAGE_EXT_KERN_EXEC | \
265 _PAGE_EXT_USER_WRITE | \
266 _PAGE_EXT_USER_READ | \
267 _PAGE_EXT_USER_EXEC))
268
269#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
270 _PAGE_DIRTY | _PAGE_ACCESSED | \
271 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
272 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
273 _PAGE_EXT_KERN_WRITE | \
274 _PAGE_EXT_KERN_EXEC))
275
276#define PAGE_KERNEL_NOCACHE \
277 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
278 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
279 _PAGE_FLAGS_HARD | \
280 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
281 _PAGE_EXT_KERN_WRITE | \
282 _PAGE_EXT_KERN_EXEC))
283
284#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
285 _PAGE_DIRTY | _PAGE_ACCESSED | \
286 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
287 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
288 _PAGE_EXT_KERN_EXEC))
289
290#define PAGE_KERNEL_PCC(slot, type) \
291 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
292 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
293 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
294 _PAGE_EXT_KERN_WRITE | \
295 _PAGE_EXT_KERN_EXEC) \
296 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
297 (type))
298
299#elif defined(CONFIG_MMU) /* SH-X TLB */
300#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
301 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
302
303#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
304 _PAGE_CACHABLE | _PAGE_ACCESSED | \
305 _PAGE_FLAGS_HARD)
306
307#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
308 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
309
310#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
311 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
312
313#define PAGE_EXECREAD PAGE_READONLY
314#define PAGE_RWX PAGE_SHARED
315#define PAGE_WRITEONLY PAGE_SHARED
316
317#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
318 _PAGE_DIRTY | _PAGE_ACCESSED | \
319 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
320
321#define PAGE_KERNEL_NOCACHE \
322 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
323 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
324 _PAGE_FLAGS_HARD)
325
326#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
327 _PAGE_DIRTY | _PAGE_ACCESSED | \
328 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
329
330#define PAGE_KERNEL_PCC(slot, type) \
331 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
332 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
333 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
334 (type))
335#else /* no mmu */
336#define PAGE_NONE __pgprot(0)
337#define PAGE_SHARED __pgprot(0)
338#define PAGE_COPY __pgprot(0)
339#define PAGE_EXECREAD __pgprot(0)
340#define PAGE_RWX __pgprot(0)
341#define PAGE_READONLY __pgprot(0)
342#define PAGE_WRITEONLY __pgprot(0)
343#define PAGE_KERNEL __pgprot(0)
344#define PAGE_KERNEL_NOCACHE __pgprot(0)
345#define PAGE_KERNEL_RO __pgprot(0)
346
347#define PAGE_KERNEL_PCC(slot, type) \
348 __pgprot(0)
349#endif 85#endif
350 86
351#endif /* __ASSEMBLY__ */
352
353/* 87/*
354 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page 88 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
355 * protection for execute, and considers it the same as a read. Also, write 89 * protection for execute, and considers it the same as a read. Also, write
@@ -378,208 +112,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
378#define __S110 PAGE_RWX 112#define __S110 PAGE_RWX
379#define __S111 PAGE_RWX 113#define __S111 PAGE_RWX
380 114
381#ifndef __ASSEMBLY__
382
383/*
384 * Certain architectures need to do special things when PTEs
385 * within a page table are directly modified. Thus, the following
386 * hook is made available.
387 */
388#ifdef CONFIG_X2TLB
389static inline void set_pte(pte_t *ptep, pte_t pte)
390{
391 ptep->pte_high = pte.pte_high;
392 smp_wmb();
393 ptep->pte_low = pte.pte_low;
394}
395#else
396#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
397#endif
398
399#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
400
401/*
402 * (pmds are folded into pgds so this doesn't get actually called,
403 * but the define is needed for a generic inline function.)
404 */
405#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
406
407#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
408
409#define pfn_pte(pfn, prot) \
410 __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
411#define pfn_pmd(pfn, prot) \
412 __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
413
414#define pte_none(x) (!pte_val(x))
415#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
416
417#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
418
419#define pmd_none(x) (!pmd_val(x))
420#define pmd_present(x) (pmd_val(x))
421#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
422#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
423
424#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
425#define pte_page(x) pfn_to_page(pte_pfn(x))
426
427/*
428 * The following only work if pte_present() is true.
429 * Undefined behaviour if not..
430 */
431#define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT))
432#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
433#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
434#define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
435
436#ifdef CONFIG_X2TLB
437#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
438#else
439#define pte_write(pte) ((pte).pte_low & _PAGE_RW)
440#endif
441
442#define PTE_BIT_FUNC(h,fn,op) \
443static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
444
445#ifdef CONFIG_X2TLB
446/*
447 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
448 * individually toggled (and user permissions are entirely decoupled from
449 * kernel permissions), we attempt to couple them a bit more sanely here.
450 */
451PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
452PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
453PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
454#else
455PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
456PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
457PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
458#endif
459
460PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
461PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
462PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
463PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
464
465/*
466 * Macro and implementation to make a page protection as uncachable.
467 */
468#define pgprot_writecombine(prot) \
469 __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
470
471#define pgprot_noncached pgprot_writecombine
472
473/*
474 * Conversion functions: convert a page and protection to a page entry,
475 * and a page entry and page directory to the page they refer to.
476 *
477 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
478 */
479#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
480
481static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
482{
483 pte.pte_low &= _PAGE_CHG_MASK;
484 pte.pte_low |= pgprot_val(newprot);
485
486#ifdef CONFIG_X2TLB
487 pte.pte_high |= pgprot_val(newprot) >> 32;
488#endif
489
490 return pte;
491}
492
493#define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd))
494#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
495
496/* to find an entry in a page-table-directory. */
497#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
498#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
499
500/* to find an entry in a kernel page-table-directory */
501#define pgd_offset_k(address) pgd_offset(&init_mm, address)
502
503/* Find an entry in the third-level page table.. */
504#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
505#define pte_offset_kernel(dir, address) \
506 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
507#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
508#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
509
510#define pte_unmap(pte) do { } while (0)
511#define pte_unmap_nested(pte) do { } while (0)
512
513#ifdef CONFIG_X2TLB
514#define pte_ERROR(e) \
515 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
516 &(e), (e).pte_high, (e).pte_low)
517#define pgd_ERROR(e) \
518 printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
519#else
520#define pte_ERROR(e) \
521 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
522#define pgd_ERROR(e) \
523 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
524#endif
525
526struct vm_area_struct;
527extern void update_mmu_cache(struct vm_area_struct * vma,
528 unsigned long address, pte_t pte);
529
530/*
531 * Encode and de-code a swap entry
532 *
533 * Constraints:
534 * _PAGE_FILE at bit 0
535 * _PAGE_PRESENT at bit 8
536 * _PAGE_PROTNONE at bit 9
537 *
538 * For the normal case, we encode the swap type into bits 0:7 and the
539 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
540 * preserved bits in the low 32-bits and use the upper 32 as the swap
541 * offset (along with a 5-bit type), following the same approach as x86
542 * PAE. This keeps the logic quite simple, and allows for a full 32
543 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
544 * in the pte_low case.
545 *
546 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
547 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
548 * much cleaner..
549 *
550 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
551 * and _PAGE_PROTNONE bits
552 */
553#ifdef CONFIG_X2TLB
554#define __swp_type(x) ((x).val & 0x1f)
555#define __swp_offset(x) ((x).val >> 5)
556#define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
557#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
558#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
559
560/*
561 * Encode and decode a nonlinear file mapping entry
562 */
563#define pte_to_pgoff(pte) ((pte).pte_high)
564#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
565
566#define PTE_FILE_MAX_BITS 32
567#else
568#define __swp_type(x) ((x).val & 0xff)
569#define __swp_offset(x) ((x).val >> 10)
570#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
571
572#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
573#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
574
575/*
576 * Encode and decode a nonlinear file mapping entry
577 */
578#define PTE_FILE_MAX_BITS 29
579#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
580#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
581#endif
582
583typedef pte_t *pte_addr_t; 115typedef pte_t *pte_addr_t;
584 116
585#define kern_addr_valid(addr) (1) 117#define kern_addr_valid(addr) (1)
@@ -587,27 +119,26 @@ typedef pte_t *pte_addr_t;
587#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 119#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
588 remap_pfn_range(vma, vaddr, pfn, size, prot) 120 remap_pfn_range(vma, vaddr, pfn, size, prot)
589 121
590struct mm_struct; 122#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
591 123
592/* 124/*
593 * No page table caches to initialise 125 * No page table caches to initialise
594 */ 126 */
595#define pgtable_cache_init() do { } while (0) 127#define pgtable_cache_init() do { } while (0)
596 128
597#ifndef CONFIG_MMU
598extern unsigned int kobjsize(const void *objp);
599#endif /* !CONFIG_MMU */
600
601#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ 129#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
602 defined(CONFIG_SH7705_CACHE_32KB)) 130 defined(CONFIG_SH7705_CACHE_32KB))
131struct mm_struct;
603#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 132#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
604extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 133pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
605#endif 134#endif
606 135
136struct vm_area_struct;
137extern void update_mmu_cache(struct vm_area_struct * vma,
138 unsigned long address, pte_t pte);
607extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 139extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
608extern void paging_init(void); 140extern void paging_init(void);
609 141
610#include <asm-generic/pgtable.h> 142#include <asm-generic/pgtable.h>
611 143
612#endif /* !__ASSEMBLY__ */ 144#endif /* __ASM_SH_PGTABLE_H */
613#endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/pgtable_32.h b/include/asm-sh/pgtable_32.h
new file mode 100644
index 000000000000..70303603e89d
--- /dev/null
+++ b/include/asm-sh/pgtable_32.h
@@ -0,0 +1,473 @@
1#ifndef __ASM_SH_PGTABLE_32_H
2#define __ASM_SH_PGTABLE_32_H
3
4/*
5 * Linux PTEL encoding.
6 *
7 * Hardware and software bit definitions for the PTEL value (see below for
8 * notes on SH-X2 MMUs and 64-bit PTEs):
9 *
10 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
11 *
12 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
13 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
14 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
15 *
16 * In order to keep this relatively clean, do not use these for defining
17 * SH-3 specific flags until all of the other unused bits have been
18 * exhausted.
19 *
20 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
21 *
22 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
23 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
24 *
25 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
26 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
27 *
28 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
29 *
30 * SH-X2 MMUs and extended PTEs
31 *
32 * SH-X2 supports an extended mode TLB with split data arrays due to the
33 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
34 * SZ bit placeholders still exist in data array 1, but are implemented as
35 * reserved bits, with the real logic existing in data array 2.
36 *
37 * The downside to this is that we can no longer fit everything in to a 32-bit
38 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
39 * side, this gives us quite a few spare bits to play with for future usage.
40 */
41/* Legacy and compat mode bits */
42#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
43#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
44#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
45#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
46#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
47#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
48#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
49#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
50#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
51#define _PAGE_PROTNONE 0x200 /* software: if not present */
52#define _PAGE_ACCESSED 0x400 /* software: page referenced */
53#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
54
55#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
56#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
57
58/* Extended mode bits */
59#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
60#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
61#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
62#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
63
64#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
65#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
66#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
67
68#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
69#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
70#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
71
72/* Wrapper for extended mode pgprot twiddling */
73#define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
74
75/* software: moves to PTEA.TC (Timing Control) */
76#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
77#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
78
79/* software: moves to PTEA.SA[2:0] (Space Attributes) */
80#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
81#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
82#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
83#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
84#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
85#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
86#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
87
88/* Mask which drops unused bits from the PTEL value */
89#if defined(CONFIG_CPU_SH3)
90#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
91 _PAGE_FILE | _PAGE_SZ1 | \
92 _PAGE_HW_SHARED)
93#elif defined(CONFIG_X2TLB)
94/* Get rid of the legacy PR/SZ bits when using extended mode */
95#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \
96 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
97#else
98#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
99#endif
100
101#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
102
103/* Hardware flags, page size encoding */
104#if defined(CONFIG_X2TLB)
105# if defined(CONFIG_PAGE_SIZE_4KB)
106# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
107# elif defined(CONFIG_PAGE_SIZE_8KB)
108# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
109# elif defined(CONFIG_PAGE_SIZE_64KB)
110# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
111# endif
112#else
113# if defined(CONFIG_PAGE_SIZE_4KB)
114# define _PAGE_FLAGS_HARD _PAGE_SZ0
115# elif defined(CONFIG_PAGE_SIZE_64KB)
116# define _PAGE_FLAGS_HARD _PAGE_SZ1
117# endif
118#endif
119
120#if defined(CONFIG_X2TLB)
121# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
122# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
123# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
124# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
125# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
126# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
127# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
128# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
129# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
130# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
131# endif
132#else
133# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
134# define _PAGE_SZHUGE (_PAGE_SZ1)
135# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
136# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
137# endif
138#endif
139
140/*
141 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
142 * to make pte_mkhuge() happy.
143 */
144#ifndef _PAGE_SZHUGE
145# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
146#endif
147
148#define _PAGE_CHG_MASK \
149 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
150
151#ifndef __ASSEMBLY__
152
153#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
154#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
155 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
156
157#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
158 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
159 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
160 _PAGE_EXT_KERN_WRITE | \
161 _PAGE_EXT_USER_READ | \
162 _PAGE_EXT_USER_WRITE))
163
164#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
165 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
166 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
167 _PAGE_EXT_KERN_READ | \
168 _PAGE_EXT_USER_EXEC | \
169 _PAGE_EXT_USER_READ))
170
171#define PAGE_COPY PAGE_EXECREAD
172
173#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
174 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
175 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
176 _PAGE_EXT_USER_READ))
177
178#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
179 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
180 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
181 _PAGE_EXT_USER_WRITE))
182
183#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
184 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
185 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
186 _PAGE_EXT_KERN_READ | \
187 _PAGE_EXT_KERN_EXEC | \
188 _PAGE_EXT_USER_WRITE | \
189 _PAGE_EXT_USER_READ | \
190 _PAGE_EXT_USER_EXEC))
191
192#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
193 _PAGE_DIRTY | _PAGE_ACCESSED | \
194 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
195 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
196 _PAGE_EXT_KERN_WRITE | \
197 _PAGE_EXT_KERN_EXEC))
198
199#define PAGE_KERNEL_NOCACHE \
200 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
201 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
202 _PAGE_FLAGS_HARD | \
203 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
204 _PAGE_EXT_KERN_WRITE | \
205 _PAGE_EXT_KERN_EXEC))
206
207#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
208 _PAGE_DIRTY | _PAGE_ACCESSED | \
209 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
210 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
211 _PAGE_EXT_KERN_EXEC))
212
213#define PAGE_KERNEL_PCC(slot, type) \
214 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
215 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
216 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
217 _PAGE_EXT_KERN_WRITE | \
218 _PAGE_EXT_KERN_EXEC) \
219 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
220 (type))
221
222#elif defined(CONFIG_MMU) /* SH-X TLB */
223#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
224 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
225
226#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
227 _PAGE_CACHABLE | _PAGE_ACCESSED | \
228 _PAGE_FLAGS_HARD)
229
230#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
231 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
232
233#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
234 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
235
236#define PAGE_EXECREAD PAGE_READONLY
237#define PAGE_RWX PAGE_SHARED
238#define PAGE_WRITEONLY PAGE_SHARED
239
240#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
241 _PAGE_DIRTY | _PAGE_ACCESSED | \
242 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
243
244#define PAGE_KERNEL_NOCACHE \
245 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
246 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
247 _PAGE_FLAGS_HARD)
248
249#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
250 _PAGE_DIRTY | _PAGE_ACCESSED | \
251 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
252
253#define PAGE_KERNEL_PCC(slot, type) \
254 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
255 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
256 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
257 (type))
258#else /* no mmu */
259#define PAGE_NONE __pgprot(0)
260#define PAGE_SHARED __pgprot(0)
261#define PAGE_COPY __pgprot(0)
262#define PAGE_EXECREAD __pgprot(0)
263#define PAGE_RWX __pgprot(0)
264#define PAGE_READONLY __pgprot(0)
265#define PAGE_WRITEONLY __pgprot(0)
266#define PAGE_KERNEL __pgprot(0)
267#define PAGE_KERNEL_NOCACHE __pgprot(0)
268#define PAGE_KERNEL_RO __pgprot(0)
269
270#define PAGE_KERNEL_PCC(slot, type) \
271 __pgprot(0)
272#endif
273
274#endif /* __ASSEMBLY__ */
275
276#ifndef __ASSEMBLY__
277
278/*
279 * Certain architectures need to do special things when PTEs
280 * within a page table are directly modified. Thus, the following
281 * hook is made available.
282 */
283#ifdef CONFIG_X2TLB
284static inline void set_pte(pte_t *ptep, pte_t pte)
285{
286 ptep->pte_high = pte.pte_high;
287 smp_wmb();
288 ptep->pte_low = pte.pte_low;
289}
290#else
291#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
292#endif
293
294#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
295
296/*
297 * (pmds are folded into pgds so this doesn't get actually called,
298 * but the define is needed for a generic inline function.)
299 */
300#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
301
302#define pfn_pte(pfn, prot) \
303 __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
304#define pfn_pmd(pfn, prot) \
305 __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
306
307#define pte_none(x) (!pte_val(x))
308#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
309
310#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
311
312#define pmd_none(x) (!pmd_val(x))
313#define pmd_present(x) (pmd_val(x))
314#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
315#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
316
317#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
318#define pte_page(x) pfn_to_page(pte_pfn(x))
319
320/*
321 * The following only work if pte_present() is true.
322 * Undefined behaviour if not..
323 */
324#define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT))
325#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
326#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
327#define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
328
329#ifdef CONFIG_X2TLB
330#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
331#else
332#define pte_write(pte) ((pte).pte_low & _PAGE_RW)
333#endif
334
335#define PTE_BIT_FUNC(h,fn,op) \
336static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
337
338#ifdef CONFIG_X2TLB
339/*
340 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
341 * individually toggled (and user permissions are entirely decoupled from
342 * kernel permissions), we attempt to couple them a bit more sanely here.
343 */
344PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
345PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
346PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
347#else
348PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
349PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
350PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
351#endif
352
353PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
354PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
355PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
356PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
357
358/*
359 * Macro and implementation to make a page protection as uncachable.
360 */
361#define pgprot_writecombine(prot) \
362 __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
363
364#define pgprot_noncached pgprot_writecombine
365
366/*
367 * Conversion functions: convert a page and protection to a page entry,
368 * and a page entry and page directory to the page they refer to.
369 *
370 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
371 */
372#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
373
374static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
375{
376 pte.pte_low &= _PAGE_CHG_MASK;
377 pte.pte_low |= pgprot_val(newprot);
378
379#ifdef CONFIG_X2TLB
380 pte.pte_high |= pgprot_val(newprot) >> 32;
381#endif
382
383 return pte;
384}
385
386#define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd))
387#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
388
389/* to find an entry in a page-table-directory. */
390#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
391#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
392
393/* to find an entry in a kernel page-table-directory */
394#define pgd_offset_k(address) pgd_offset(&init_mm, address)
395
396/* Find an entry in the third-level page table.. */
397#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
398#define pte_offset_kernel(dir, address) \
399 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
400#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
401#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
402
403#define pte_unmap(pte) do { } while (0)
404#define pte_unmap_nested(pte) do { } while (0)
405
406#ifdef CONFIG_X2TLB
407#define pte_ERROR(e) \
408 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
409 &(e), (e).pte_high, (e).pte_low)
410#define pgd_ERROR(e) \
411 printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
412#else
413#define pte_ERROR(e) \
414 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
415#define pgd_ERROR(e) \
416 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
417#endif
418
419/*
420 * Encode and de-code a swap entry
421 *
422 * Constraints:
423 * _PAGE_FILE at bit 0
424 * _PAGE_PRESENT at bit 8
425 * _PAGE_PROTNONE at bit 9
426 *
427 * For the normal case, we encode the swap type into bits 0:7 and the
428 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
429 * preserved bits in the low 32-bits and use the upper 32 as the swap
430 * offset (along with a 5-bit type), following the same approach as x86
431 * PAE. This keeps the logic quite simple, and allows for a full 32
432 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
433 * in the pte_low case.
434 *
435 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
436 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
437 * much cleaner..
438 *
439 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
440 * and _PAGE_PROTNONE bits
441 */
442#ifdef CONFIG_X2TLB
443#define __swp_type(x) ((x).val & 0x1f)
444#define __swp_offset(x) ((x).val >> 5)
445#define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
446#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
447#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
448
449/*
450 * Encode and decode a nonlinear file mapping entry
451 */
452#define pte_to_pgoff(pte) ((pte).pte_high)
453#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
454
455#define PTE_FILE_MAX_BITS 32
456#else
457#define __swp_type(x) ((x).val & 0xff)
458#define __swp_offset(x) ((x).val >> 10)
459#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
460
461#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
462#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
463
464/*
465 * Encode and decode a nonlinear file mapping entry
466 */
467#define PTE_FILE_MAX_BITS 29
468#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
469#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
470#endif
471
472#endif /* __ASSEMBLY__ */
473#endif /* __ASM_SH_PGTABLE_32_H */
diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh/pgtable_64.h
index 3488fe32e436..d422111006f4 100644
--- a/include/asm-sh64/pgtable.h
+++ b/include/asm-sh/pgtable_64.h
@@ -1,8 +1,6 @@
1#ifndef __ASM_SH64_PGTABLE_H 1#ifndef __ASM_SH64_PGTABLE_H
2#define __ASM_SH64_PGTABLE_H 2#define __ASM_SH64_PGTABLE_H
3 3
4#include <asm-generic/4level-fixup.h>
5
6/* 4/*
7 * This file is subject to the terms and conditions of the GNU General Public 5 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 6 * License. See the file "COPYING" in the main directory of this archive
@@ -18,119 +16,26 @@
18 * the SuperH page table tree. 16 * the SuperH page table tree.
19 */ 17 */
20 18
21#ifndef __ASSEMBLY__ 19#include <linux/threads.h>
22#include <asm/processor.h> 20#include <asm/processor.h>
23#include <asm/page.h> 21#include <asm/page.h>
24#include <linux/threads.h>
25
26struct vm_area_struct;
27
28extern void paging_init(void);
29
30/* We provide our own get_unmapped_area to avoid cache synonym issue */
31#define HAVE_ARCH_UNMAPPED_AREA
32
33/*
34 * Basically we have the same two-level (which is the logical three level
35 * Linux page table layout folded) page tables as the i386.
36 */
37
38/*
39 * ZERO_PAGE is a global shared page that is always zero: used
40 * for zero-mapped memory areas etc..
41 */
42extern unsigned char empty_zero_page[PAGE_SIZE];
43#define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page))
44
45#endif /* !__ASSEMBLY__ */
46
47/*
48 * NEFF and NPHYS related defines.
49 * FIXME : These need to be model-dependent. For now this is OK, SH5-101 and SH5-103
50 * implement 32 bits effective and 32 bits physical. But future implementations may
51 * extend beyond this.
52 */
53#define NEFF 32
54#define NEFF_SIGN (1LL << (NEFF - 1))
55#define NEFF_MASK (-1LL << NEFF)
56
57#define NPHYS 32
58#define NPHYS_SIGN (1LL << (NPHYS - 1))
59#define NPHYS_MASK (-1LL << NPHYS)
60
61/* Typically 2-level is sufficient up to 32 bits of virtual address space, beyond
62 that 3-level would be appropriate. */
63#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
64/* For 4k pages, this contains 512 entries, i.e. 9 bits worth of address. */
65#define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
66#define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
67#define PTE_SHIFT PAGE_SHIFT
68#define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
69
70/* top level: PMD. */
71#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
72#define PGD_BITS (NEFF - PGDIR_SHIFT)
73#define PTRS_PER_PGD (1<<PGD_BITS)
74
75/* middle level: PMD. This doesn't do anything for the 2-level case. */
76#define PTRS_PER_PMD (1)
77
78#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
79#define PGDIR_MASK (~(PGDIR_SIZE-1))
80#define PMD_SHIFT PGDIR_SHIFT
81#define PMD_SIZE PGDIR_SIZE
82#define PMD_MASK PGDIR_MASK
83
84#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
85/*
86 * three-level asymmetric paging structure: PGD is top level.
87 * The asymmetry comes from 32-bit pointers and 64-bit PTEs.
88 */
89/* bottom level: PTE. It's 9 bits = 512 pointers */
90#define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
91#define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
92#define PTE_SHIFT PAGE_SHIFT
93#define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
94
95/* middle level: PMD. It's 10 bits = 1024 pointers */
96#define PTRS_PER_PMD ((1<<PAGE_SHIFT)/sizeof(unsigned long long *))
97#define PMD_MAGNITUDE 2 /* sizeof(unsigned long long *) magnit. */
98#define PMD_SHIFT (PTE_SHIFT + PTE_BITS)
99#define PMD_BITS (PAGE_SHIFT - PMD_MAGNITUDE)
100
101/* top level: PMD. It's 1 bit = 2 pointers */
102#define PGDIR_SHIFT (PMD_SHIFT + PMD_BITS)
103#define PGD_BITS (NEFF - PGDIR_SHIFT)
104#define PTRS_PER_PGD (1<<PGD_BITS)
105
106#define PMD_SIZE (1UL << PMD_SHIFT)
107#define PMD_MASK (~(PMD_SIZE-1))
108#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
109#define PGDIR_MASK (~(PGDIR_SIZE-1))
110
111#else
112#error "No defined number of page table levels"
113#endif
114 22
115/* 23/*
116 * Error outputs. 24 * Error outputs.
117 */ 25 */
118#define pte_ERROR(e) \ 26#define pte_ERROR(e) \
119 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) 27 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
120#define pmd_ERROR(e) \
121 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
122#define pgd_ERROR(e) \ 28#define pgd_ERROR(e) \
123 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 29 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
124 30
125/* 31/*
126 * Table setting routines. Used within arch/mm only. 32 * Table setting routines. Used within arch/mm only.
127 */ 33 */
128#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
129#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 34#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
130 35
131static __inline__ void set_pte(pte_t *pteptr, pte_t pteval) 36static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
132{ 37{
133 unsigned long long x = ((unsigned long long) pteval.pte); 38 unsigned long long x = ((unsigned long long) pteval.pte_low);
134 unsigned long long *xp = (unsigned long long *) pteptr; 39 unsigned long long *xp = (unsigned long long *) pteptr;
135 /* 40 /*
136 * Sign-extend based on NPHYS. 41 * Sign-extend based on NPHYS.
@@ -157,61 +62,6 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
157#define pgd_offset_k(address) pgd_offset(&init_mm, address) 62#define pgd_offset_k(address) pgd_offset(&init_mm, address)
158 63
159/* 64/*
160 * PGD level access routines.
161 *
162 * Note1:
163 * There's no need to use physical addresses since the tree walk is all
164 * in performed in software, until the PTE translation.
165 *
166 * Note 2:
167 * A PGD entry can be uninitialized (_PGD_UNUSED), generically bad,
168 * clear (_PGD_EMPTY), present. When present, lower 3 nibbles contain
169 * _KERNPG_TABLE. Being a kernel virtual pointer also bit 31 must
170 * be 1. Assuming an arbitrary clear value of bit 31 set to 0 and
171 * lower 3 nibbles set to 0xFFF (_PGD_EMPTY) any other value is a
172 * bad pgd that must be notified via printk().
173 *
174 */
175#define _PGD_EMPTY 0x0
176
177#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
178static inline int pgd_none(pgd_t pgd) { return 0; }
179static inline int pgd_bad(pgd_t pgd) { return 0; }
180#define pgd_present(pgd) ((pgd_val(pgd) & _PAGE_PRESENT) ? 1 : 0)
181#define pgd_clear(xx) do { } while(0)
182
183#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
184#define pgd_present(pgd_entry) (1)
185#define pgd_none(pgd_entry) (pgd_val((pgd_entry)) == _PGD_EMPTY)
186/* TODO: Think later about what a useful definition of 'bad' would be now. */
187#define pgd_bad(pgd_entry) (0)
188#define pgd_clear(pgd_entry_p) (set_pgd((pgd_entry_p), __pgd(_PGD_EMPTY)))
189
190#endif
191
192
193#define pgd_page_vaddr(pgd_entry) ((unsigned long) (pgd_val(pgd_entry) & PAGE_MASK))
194#define pgd_page(pgd) (virt_to_page(pgd_val(pgd)))
195
196
197/*
198 * PMD defines. Middle level.
199 */
200
201/* PGD to PMD dereferencing */
202#if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
203static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
204{
205 return (pmd_t *) dir;
206}
207#elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
208#define __pmd_offset(address) \
209 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
210#define pmd_offset(dir, addr) \
211 ((pmd_t *) ((pgd_val(*(dir))) & PAGE_MASK) + __pmd_offset((addr)))
212#endif
213
214/*
215 * PMD level access routines. Same notes as above. 65 * PMD level access routines. Same notes as above.
216 */ 66 */
217#define _PMD_EMPTY 0x0 67#define _PMD_EMPTY 0x0
@@ -239,15 +89,7 @@ static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
239#define pte_unmap(pte) do { } while (0) 89#define pte_unmap(pte) do { } while (0)
240#define pte_unmap_nested(pte) do { } while (0) 90#define pte_unmap_nested(pte) do { } while (0)
241 91
242/* Round it up ! */
243#define USER_PTRS_PER_PGD ((TASK_SIZE+PGDIR_SIZE-1)/PGDIR_SIZE)
244#define FIRST_USER_ADDRESS 0
245
246#ifndef __ASSEMBLY__ 92#ifndef __ASSEMBLY__
247#define VMALLOC_END 0xff000000
248#define VMALLOC_START 0xf0000000
249#define VMALLOC_VMADDR(x) ((unsigned long)(x))
250
251#define IOBASE_VADDR 0xff000000 93#define IOBASE_VADDR 0xff000000
252#define IOBASE_END 0xffffffff 94#define IOBASE_END 0xffffffff
253 95
@@ -315,43 +157,28 @@ static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
315 157
316#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 158#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
317 159
160/*
161 * We have full permissions (Read/Write/Execute/Shared).
162 */
163#define _PAGE_COMMON (_PAGE_PRESENT | _PAGE_USER | \
164 _PAGE_CACHABLE | _PAGE_ACCESSED)
165
318#define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED) 166#define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
319#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 167#define PAGE_SHARED __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_WRITE | \
320 _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_USER | \
321 _PAGE_SHARED) 168 _PAGE_SHARED)
322/* We need to include PAGE_EXECUTE in PAGE_COPY because it is the default 169#define PAGE_EXECREAD __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_EXECUTE)
323 * protection mode for the stack. */
324#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
325 _PAGE_ACCESSED | _PAGE_USER | _PAGE_EXECUTE)
326#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
327 _PAGE_ACCESSED | _PAGE_USER)
328#define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
329
330 170
331/* 171/*
332 * In ST50 we have full permissions (Read/Write/Execute/Shared). 172 * We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
333 * Just match'em all. These are for mmap(), therefore all at least 173 * protection mode for the stack.
334 * User/Cachable/Present/Accessed. No point in making Fault on Write.
335 */ 174 */
336#define __MMAP_COMMON (_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED) 175#define PAGE_COPY PAGE_EXECREAD
337 /* sxwr */ 176
338#define __P000 __pgprot(__MMAP_COMMON) 177#define PAGE_READONLY __pgprot(_PAGE_COMMON | _PAGE_READ)
339#define __P001 __pgprot(__MMAP_COMMON | _PAGE_READ) 178#define PAGE_WRITEONLY __pgprot(_PAGE_COMMON | _PAGE_WRITE)
340#define __P010 __pgprot(__MMAP_COMMON) 179#define PAGE_RWX __pgprot(_PAGE_COMMON | _PAGE_READ | \
341#define __P011 __pgprot(__MMAP_COMMON | _PAGE_READ) 180 _PAGE_WRITE | _PAGE_EXECUTE)
342#define __P100 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE) 181#define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
343#define __P101 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
344#define __P110 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE)
345#define __P111 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
346
347#define __S000 __pgprot(__MMAP_COMMON | _PAGE_SHARED)
348#define __S001 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ)
349#define __S010 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_WRITE)
350#define __S011 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ | _PAGE_WRITE)
351#define __S100 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE)
352#define __S101 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ)
353#define __S110 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_WRITE)
354#define __S111 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ | _PAGE_WRITE)
355 182
356/* Make it a device mapping for maximum safety (e.g. for mapping device 183/* Make it a device mapping for maximum safety (e.g. for mapping device
357 registers into user-space via /dev/map). */ 184 registers into user-space via /dev/map). */
@@ -453,12 +280,6 @@ static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _
453static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 280static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
454{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; } 281{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
455 282
456typedef pte_t *pte_addr_t;
457#define pgtable_cache_init() do { } while (0)
458
459extern void update_mmu_cache(struct vm_area_struct * vma,
460 unsigned long address, pte_t pte);
461
462/* Encode and decode a swap entry */ 283/* Encode and decode a swap entry */
463#define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c)) 284#define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c))
464#define __swp_offset(x) ((x).val >> 8) 285#define __swp_offset(x) ((x).val >> 8)
@@ -471,26 +292,9 @@ extern void update_mmu_cache(struct vm_area_struct * vma,
471#define pte_to_pgoff(pte) (pte_val(pte)) 292#define pte_to_pgoff(pte) (pte_val(pte))
472#define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE }) 293#define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE })
473 294
474/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
475#define PageSkip(page) (0)
476#define kern_addr_valid(addr) (1)
477
478#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
479 remap_pfn_range(vma, vaddr, pfn, size, prot)
480
481#endif /* !__ASSEMBLY__ */ 295#endif /* !__ASSEMBLY__ */
482 296
483/*
484 * No page table caches to initialise
485 */
486#define pgtable_cache_init() do { } while (0)
487
488#define pte_pfn(x) (((unsigned long)((x).pte)) >> PAGE_SHIFT)
489#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 297#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
490#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 298#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
491 299
492extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
493
494#include <asm-generic/pgtable.h>
495
496#endif /* __ASM_SH64_PGTABLE_H */ 300#endif /* __ASM_SH64_PGTABLE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-06-01 11:28:25 -0400