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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-21 01:43:18 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-21 01:43:18 -0400
commit2046219364a40bcb13482ff68eb6ccec13405633 (patch)
tree5f4f951da5a0326318cd1abcd535ea40dc90c3b7 /include
parent0c5564bd91ad237212871d52deaf79ffe06bcc64 (diff)
parent0af666fa6cf4bc639fb6170600b5fb0d8b6504b9 (diff)
Merge branch 'fixes-2.6.23' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc
* 'fixes-2.6.23' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc: [POWERPC] Fix 8xx compile failure [POWERPC] Fix FSL BookE machine check reporting [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards [POWERPC] Add interrupt resource for RTC CMOS driver
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/reg_booke.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 064405c207bf..8fdc2b47afb9 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -223,7 +223,6 @@
223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
224#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 224#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
225#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 225#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
226#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
227#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 226#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
228#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ 227#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
229#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ 228#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
@@ -232,6 +231,12 @@
232#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ 231#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
233#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 232#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
234#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 233#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
234
235/* e500 parts may set unused bits in MCSR; mask these off */
236#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
237 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
238 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
239 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
235#endif 240#endif
236#ifdef CONFIG_E200 241#ifdef CONFIG_E200
237#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 242#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
@@ -243,6 +248,11 @@
243#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 248#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
244#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 249#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
245 store or cache line push */ 250 store or cache line push */
251
252/* e200 parts may set unused bits in MCSR; mask these off */
253#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
254 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
255 MCSR_BUS_WRERR)
246#endif 256#endif
247 257
248/* Bit definitions for the DBSR. */ 258/* Bit definitions for the DBSR. */