Merge tag 'tegra-for-3.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt2

Pull "ARM: tegra: Device tree changes for v3.19" from Thierry Reding:

The bulk of these changes add memory controller nodes for Tegra30,
Tegra114 and Tegra124. The memory controller implements an IOMMU that
the display controllers are attached to. This allows them to scan out
physically non-contiguous framebuffers and removes one of the primary
users of CMA.

The only other change adds a new MIPI pad control bank to the pin
controller on Tegra124. The corresponding driver patch for this went
into v3.18 as:

        3ccc11f6b82c pinctrl: tegra: Add MIPI pad control

* tag 'tegra-for-3.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Enable IOMMU for display controllers on Tegra124
  ARM: tegra: Enable IOMMU for display controllers on Tegra114
  ARM: tegra: Enable IOMMU for display controllers on Tegra30
  ARM: tegra: Add memory controller support for Tegra124
  ARM: tegra: Add memory controller support for Tegra114
  ARM: tegra: Add memory controller support for Tegra30
  ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank

These additional commits are merged as dependencies:

  memory: Add NVIDIA Tegra memory controller support
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  powerpc/iommu: Rename iommu_[un]map_sg functions
  iommu: Improve error handling when setting bus iommu
  iommu: Do more input validation in iommu_map_sg()
  iommu: Add iommu_map_sg() function

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

8 files changed, 212 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index fc12621fb432..534c03f8ad72 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
 #define TEGRA114_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA114_CLK_MC 32
 /* 33 */
 #define TEGRA114_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 6bac637fd635..af9bc9a3ddbc 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -48,7 +48,7 @@
 #define TEGRA124_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA124_CLK_MC 32
 /* 33 */
 #define TEGRA124_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index 9406207cfac8..04500b243a4d 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
 /* 30 */
 #define TEGRA20_CLK_CACHE2 31
 
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
 #define TEGRA20_CLK_AHBDMA 33
 #define TEGRA20_CLK_APBDMA 34
 /* 35 */
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
new file mode 100644
index 000000000000..8f48985a3139
--- /dev/null
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -0,0 +1,25 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_EPP       3
+#define TEGRA_SWGROUP_G2        4
+#define TEGRA_SWGROUP_AVPC      5
+#define TEGRA_SWGROUP_NV        6
+#define TEGRA_SWGROUP_HDA       7
+#define TEGRA_SWGROUP_HC        8
+#define TEGRA_SWGROUP_MSENC     9
+#define TEGRA_SWGROUP_PPCS      10
+#define TEGRA_SWGROUP_VDE       11
+#define TEGRA_SWGROUP_MPCORELP  12
+#define TEGRA_SWGROUP_MPCORE    13
+#define TEGRA_SWGROUP_VI        14
+#define TEGRA_SWGROUP_ISP       15
+#define TEGRA_SWGROUP_XUSB_HOST 16
+#define TEGRA_SWGROUP_XUSB_DEV  17
+#define TEGRA_SWGROUP_EMUCIF    18
+#define TEGRA_SWGROUP_TSEC      19
+
+#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
new file mode 100644
index 000000000000..7d8ee798f34e
--- /dev/null
+++ b/include/dt-bindings/memory/tegra124-mc.h
@@ -0,0 +1,31 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_AFI       3
+#define TEGRA_SWGROUP_AVPC      4
+#define TEGRA_SWGROUP_HDA       5
+#define TEGRA_SWGROUP_HC        6
+#define TEGRA_SWGROUP_MSENC     7
+#define TEGRA_SWGROUP_PPCS      8
+#define TEGRA_SWGROUP_SATA      9
+#define TEGRA_SWGROUP_VDE       10
+#define TEGRA_SWGROUP_MPCORELP  11
+#define TEGRA_SWGROUP_MPCORE    12
+#define TEGRA_SWGROUP_ISP2      13
+#define TEGRA_SWGROUP_XUSB_HOST 14
+#define TEGRA_SWGROUP_XUSB_DEV  15
+#define TEGRA_SWGROUP_ISP2B     16
+#define TEGRA_SWGROUP_TSEC      17
+#define TEGRA_SWGROUP_A9AVP     18
+#define TEGRA_SWGROUP_GPU       19
+#define TEGRA_SWGROUP_SDMMC1A   20
+#define TEGRA_SWGROUP_SDMMC2A   21
+#define TEGRA_SWGROUP_SDMMC3A   22
+#define TEGRA_SWGROUP_SDMMC4A   23
+#define TEGRA_SWGROUP_VIC       24
+#define TEGRA_SWGROUP_VI        25
+
+#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
new file mode 100644
index 000000000000..502beb03d777
--- /dev/null
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -0,0 +1,24 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
+
+#define TEGRA_SWGROUP_PTC       0
+#define TEGRA_SWGROUP_DC        1
+#define TEGRA_SWGROUP_DCB       2
+#define TEGRA_SWGROUP_EPP       3
+#define TEGRA_SWGROUP_G2        4
+#define TEGRA_SWGROUP_MPE       5
+#define TEGRA_SWGROUP_VI        6
+#define TEGRA_SWGROUP_AFI       7
+#define TEGRA_SWGROUP_AVPC      8
+#define TEGRA_SWGROUP_NV        9
+#define TEGRA_SWGROUP_NV2       10
+#define TEGRA_SWGROUP_HDA       11
+#define TEGRA_SWGROUP_HC        12
+#define TEGRA_SWGROUP_PPCS      13
+#define TEGRA_SWGROUP_SATA      14
+#define TEGRA_SWGROUP_VDE       15
+#define TEGRA_SWGROUP_MPCORELP  16
+#define TEGRA_SWGROUP_MPCORE    17
+#define TEGRA_SWGROUP_ISP       18
+
+#endif
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e6a7c9ff72f2..b29a5982e1c3 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/types.h>
+#include <linux/scatterlist.h>
 #include <trace/events/iommu.h>
 
 #define IOMMU_READ      (1 << 0)
@@ -97,6 +98,8 @@ enum iommu_attr {
  * @detach_dev: detach device from an iommu domain
  * @map: map a physically contiguous memory region to an iommu domain
  * @unmap: unmap a physically contiguous memory region from an iommu domain
+ * @map_sg: map a scatter-gather list of physically contiguous memory chunks
+ * to an iommu domain
  * @iova_to_phys: translate iova to physical address
  * @add_device: add device to iommu grouping
  * @remove_device: remove device from iommu grouping
@@ -114,6 +117,8 @@ struct iommu_ops {
                    phys_addr_t paddr, size_t size, int prot);
         size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
                      size_t size);
+        size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova,
+                         struct scatterlist *sg, unsigned int nents, int prot);
         phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova);
         int (*add_device)(struct device *dev);
         void (*remove_device)(struct device *dev);
@@ -156,6 +161,9 @@ extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
                      phys_addr_t paddr, size_t size, int prot);
 extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
                        size_t size);
+extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
+                                struct scatterlist *sg,unsigned int nents,
+                                int prot);
 extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
 extern void iommu_set_fault_handler(struct iommu_domain *domain,
                         iommu_fault_handler_t handler, void *token);
@@ -241,6 +249,13 @@ static inline int report_iommu_fault(struct iommu_domain *domain,
         return ret;
 }
 
+static inline size_t iommu_map_sg(struct iommu_domain *domain,
+                                  unsigned long iova, struct scatterlist *sg,
+                                  unsigned int nents, int prot)
+{
+        return domain->ops->map_sg(domain, iova, sg, nents, prot);
+}
+
 #else /* CONFIG_IOMMU_API */
 
 struct iommu_ops {};
@@ -293,6 +308,13 @@ static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova,
         return -ENODEV;
 }
 
+static inline size_t iommu_map_sg(struct iommu_domain *domain,
+                                  unsigned long iova, struct scatterlist *sg,
+                                  unsigned int nents, int prot)
+{
+        return -ENODEV;
+}
+
 static inline int iommu_domain_window_enable(struct iommu_domain *domain,
                                              u32 wnd_nr, phys_addr_t paddr,
                                              u64 size, int prot)
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
new file mode 100644
index 000000000000..63deb8d9f82a
--- /dev/null
+++ b/include/soc/tegra/mc.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_MC_H__
+#define __SOC_TEGRA_MC_H__
+
+#include <linux/types.h>
+
+struct clk;
+struct device;
+struct page;
+
+struct tegra_smmu_enable {
+        unsigned int reg;
+        unsigned int bit;
+};
+
+/* latency allowance */
+struct tegra_mc_la {
+        unsigned int reg;
+        unsigned int shift;
+        unsigned int mask;
+        unsigned int def;
+};
+
+struct tegra_mc_client {
+        unsigned int id;
+        const char *name;
+        unsigned int swgroup;
+
+        unsigned int fifo_size;
+
+        struct tegra_smmu_enable smmu;
+        struct tegra_mc_la la;
+};
+
+struct tegra_smmu_swgroup {
+        unsigned int swgroup;
+        unsigned int reg;
+};
+
+struct tegra_smmu_ops {
+        void (*flush_dcache)(struct page *page, unsigned long offset,
+                             size_t size);
+};
+
+struct tegra_smmu_soc {
+        const struct tegra_mc_client *clients;
+        unsigned int num_clients;
+
+        const struct tegra_smmu_swgroup *swgroups;
+        unsigned int num_swgroups;
+
+        bool supports_round_robin_arbitration;
+        bool supports_request_limit;
+
+        unsigned int num_asids;
+
+        const struct tegra_smmu_ops *ops;
+};
+
+struct tegra_mc;
+struct tegra_smmu;
+
+#ifdef CONFIG_TEGRA_IOMMU_SMMU
+struct tegra_smmu *tegra_smmu_probe(struct device *dev,
+                                    const struct tegra_smmu_soc *soc,
+                                    struct tegra_mc *mc);
+#else
+static inline struct tegra_smmu *
+tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
+                 struct tegra_mc *mc)
+{
+        return NULL;
+}
+#endif
+
+struct tegra_mc_soc {
+        const struct tegra_mc_client *clients;
+        unsigned int num_clients;
+
+        const unsigned int *emem_regs;
+        unsigned int num_emem_regs;
+
+        unsigned int num_address_bits;
+        unsigned int atom_size;
+
+        const struct tegra_smmu_soc *smmu;
+};
+
+struct tegra_mc {
+        struct device *dev;
+        struct tegra_smmu *smmu;
+        void __iomem *regs;
+        struct clk *clk;
+        int irq;
+
+        const struct tegra_mc_soc *soc;
+        unsigned long tick;
+};
+
+#endif /* __SOC_TEGRA_MC_H__ */