Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (30 commits)
  [ARM] constify function pointer tables
  [ARM] 4823/1: AT91 section fix
  [ARM] 4824/1: pxa: clear RDH bit after any reset
  [ARM] pxa: remove debugging PM: printk
  ARM: OMAP1: Misc clean-up
  ARM: OMAP1: Update defconfigs for omap1
  ARM: OMAP1: Palm Tungsten E board clean-up
  ARM: OMAP1: Use I2C bus registration helper for omap1
  ARM: OMAP1: Remove omap_sram_idle()
  ARM: OMAP1: PM fixes for OMAP1
  ARM: OMAP1: Use MMC multislot structures for Siemens SX1 board
  ARM: OMAP1: Make omap1 use MMC multislot structures
  ARM: OMAP1: Change the comments to C style
  ARM: OMAP1: Make omap1 boards to use omap_nand_platform_data
  ARM: OMAP: Add helper module for board specific I2C bus registration
  ARM: OMAP: Add dmtimer support for OMAP3
  ARM: OMAP: Pre-3430 clean-up for dmtimer.c
  ARM: OMAP: Add DMA support for chaining and 3430
  ARM: OMAP: Add 24xx GPIO debounce support
  ARM: OMAP: Get rid of unnecessary ifdefs in GPIO code
  ...

16 files changed, 356 insertions, 106 deletions

diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
index dcb587b311f1..547125a4695e 100644
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ b/include/asm-arm/arch-omap/board-apollon.h
@@ -29,6 +29,8 @@
 #ifndef __ASM_ARCH_OMAP_APOLLON_H
 #define __ASM_ARCH_OMAP_APOLLON_H
 
+extern void apollon_mmc_init(void);
+
 /* Placeholder for APOLLON specific defines */
 #define APOLLON_ETHR_GPIO_IRQ           74
 
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index b2888ef9e9b4..c322796d0d26 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,5 +34,8 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
 
+extern void h2_mmc_init(void);
+extern void h2_mmc_slot_cover_handler(void *arg, int state);
+
 #endif /*  __ASM_ARCH_OMAP_H2_H */
 
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 761ea0a17897..1c2b55c61ca0 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -36,5 +36,7 @@
 
 #define NR_IRQS                         (MAXIRQNUM + 1)
 
+extern void __init h3_mmc_init(void);
+extern void h3_mmc_slot_cover_handler(void *arg, int state);
 
 #endif /*  __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h
index 2bb8dd6e2d14..355adbdaae33 100644
--- a/include/asm-arm/arch-omap/board-sx1.h
+++ b/include/asm-arm/arch-omap/board-sx1.h
@@ -41,6 +41,12 @@ int sx1_getkeylight(u8 *keylight);
 
 int sx1_setmmipower(u8 onoff);
 int sx1_setusbpower(u8 onoff);
-int sx1_setmmcpower(u8 onoff);
+int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
+int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
+
+/* MMC prototypes */
+
+extern void sx1_mmc_init(void);
+extern void sx1_mmc_slot_cover_handler(void *arg, int state);
 
 #endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 08d58abd8218..442aecbb8f44 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -27,10 +27,21 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
 
+#ifdef CONFIG_I2C_OMAP
+#include <linux/i2c.h>
+#endif
+
 struct sys_timer;
 
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 extern void omap_serial_init(void);
+#ifdef CONFIG_I2C_OMAP
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+#define omap_register_i2c_bus(a, b, c, d)       0
+#endif
 
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index ec7eb675d922..e8a4cf52778b 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -28,7 +28,7 @@
 
 extern unsigned int system_rev;
 
-#define omap2_cpu_rev()         ((system_rev >> 8) & 0x0f)
+#define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
 
 /*
  * Test if multicore OMAP support is needed
@@ -61,12 +61,33 @@ extern unsigned int system_rev;
 #  define OMAP_NAME omap16xx
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP24XX
+#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
 # if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
 #  error "OMAP1 and OMAP2 can't be selected at the same time"
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
 # else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3430
+# ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
-#  define OMAP_NAME omap24xx
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3430
 # endif
 #endif
 
@@ -79,8 +100,9 @@ extern unsigned int system_rev;
  * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
  * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
  * cpu_is_omap243x():   True for OMAP2430
+ * cpu_is_omap343x():   True for OMAP3430
  */
-#define GET_OMAP_CLASS  (system_rev & 0xff)
+#define GET_OMAP_CLASS  ((system_rev >> 24) & 0xff)
 
 #define IS_OMAP_CLASS(class, id)                        \
 static inline int is_omap ##class (void)                \
@@ -100,9 +122,11 @@ IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_CLASS(34xx, 0x34)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
+IS_OMAP_SUBCLASS(343x, 0x343)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -110,6 +134,8 @@ IS_OMAP_SUBCLASS(243x, 0x243)
 #define cpu_is_omap24xx()               0
 #define cpu_is_omap242x()               0
 #define cpu_is_omap243x()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap343x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -137,14 +163,44 @@ IS_OMAP_SUBCLASS(243x, 0x243)
 #  undef  cpu_is_omap16xx
 #  define cpu_is_omap16xx()             1
 # endif
+#endif
+
+#if defined(MULTI_OMAP2)
 # if defined(CONFIG_ARCH_OMAP24XX)
 #  undef  cpu_is_omap24xx
 #  undef  cpu_is_omap242x
 #  undef  cpu_is_omap243x
-#  define cpu_is_omap24xx()             1
+#  define cpu_is_omap24xx()             is_omap24xx()
 #  define cpu_is_omap242x()             is_omap242x()
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
+# if defined(CONFIG_ARCH_OMAP34XX)
+#  undef  cpu_is_omap34xx
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap34xx()             is_omap34xx()
+#  define cpu_is_omap343x()             is_omap343x()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP24XX)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP34XX)
+#  undef  cpu_is_omap34xx
+#  define cpu_is_omap34xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP3430)
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap343x()             1
+# endif
 #endif
 
 /*
@@ -162,6 +218,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
  * cpu_is_omap2422():   True for OMAP2422
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
+ * cpu_is_omap3430():   True for OMAP3430
  */
 #define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
 
@@ -183,6 +240,7 @@ IS_OMAP_TYPE(2420, 0x2420)
 IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
+IS_OMAP_TYPE(3430, 0x3430)
 
 #define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
@@ -196,6 +254,7 @@ IS_OMAP_TYPE(2430, 0x2430)
 #define cpu_is_omap2422()               0
 #define cpu_is_omap2423()               0
 #define cpu_is_omap2430()               0
+#define cpu_is_omap3430()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -244,9 +303,65 @@ IS_OMAP_TYPE(2430, 0x2430)
 # define cpu_is_omap2430()              is_omap2430()
 #endif
 
+#if defined(CONFIG_ARCH_OMAP34XX)
+# undef cpu_is_omap3430
+# define cpu_is_omap3430()              is_omap3430()
+#endif
+
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap730() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
-#define cpu_class_is_omap2()    cpu_is_omap24xx()
+#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+/*
+ * Macros to detect silicon revision of OMAP2/3 processors.
+ * is_sil_rev_greater_than:     true if passed cpu type & its rev is greater.
+ * is_sil_rev_lesser_than:      true if passed cpu type & its rev is lesser.
+ * is_sil_rev_equal_to:         true if passed cpu type & its rev is equal.
+ * get_sil_rev:                 return the silicon rev value.
+ */
+#define get_sil_omap_type(rev)  ((rev & 0xffff0000) >> 16)
+#define get_sil_revision(rev)   ((rev & 0x0000f000) >> 12)
+
+#define is_sil_rev_greater_than(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) > get_sil_revision(rev)))
+
+#define is_sil_rev_less_than(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) < get_sil_revision(rev)))
+
+#define is_sil_rev_equal_to(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) == get_sil_revision(rev)))
+
+#define get_sil_rev() \
+                get_sil_revision(system_rev)
+
+/* Various silicon macros defined here */
+#define OMAP2420_REV_ES1_0      0x24200000
+#define OMAP2420_REV_ES2_0      0x24201000
+#define OMAP2430_REV_ES1_0      0x24300000
+#define OMAP3430_REV_ES1_0      0x34300000
+#define OMAP3430_REV_ES2_0      0x34301000
+
+/*
+ * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define DEVICE_TYPE_TEST        0
+#define DEVICE_TYPE_EMU         1
+#define DEVICE_TYPE_SEC         2
+#define DEVICE_TYPE_GP          3
+#define DEVICE_TYPE_BAD         4
+
+#define get_device_type()       ((system_rev & 0x700) >> 8)
+#define is_device_type_test()   (get_device_type() == DEVICE_TYPE_TEST)
+#define is_device_type_emu()    (get_device_type() == DEVICE_TYPE_EMU)
+#define is_device_type_sec()    (get_device_type() == DEVICE_TYPE_SEC)
+#define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
+#define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
+
+#endif
 
 #endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f33b467fddb7..24acf090030d 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -45,22 +45,28 @@
 #define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
 
 /* Hardware registers for omap2 */
-#define OMAP24XX_DMA_BASE               (L4_24XX_BASE + 0x56000)
-#define OMAP_DMA4_REVISION              (OMAP24XX_DMA_BASE + 0x00)
-#define OMAP_DMA4_GCR_REG               (OMAP24XX_DMA_BASE + 0x78)
-#define OMAP_DMA4_IRQSTATUS_L0          (OMAP24XX_DMA_BASE + 0x08)
-#define OMAP_DMA4_IRQSTATUS_L1          (OMAP24XX_DMA_BASE + 0x0c)
-#define OMAP_DMA4_IRQSTATUS_L2          (OMAP24XX_DMA_BASE + 0x10)
-#define OMAP_DMA4_IRQSTATUS_L3          (OMAP24XX_DMA_BASE + 0x14)
-#define OMAP_DMA4_IRQENABLE_L0          (OMAP24XX_DMA_BASE + 0x18)
-#define OMAP_DMA4_IRQENABLE_L1          (OMAP24XX_DMA_BASE + 0x1c)
-#define OMAP_DMA4_IRQENABLE_L2          (OMAP24XX_DMA_BASE + 0x20)
-#define OMAP_DMA4_IRQENABLE_L3          (OMAP24XX_DMA_BASE + 0x24)
-#define OMAP_DMA4_SYSSTATUS             (OMAP24XX_DMA_BASE + 0x28)
-#define OMAP_DMA4_CAPS_0                (OMAP24XX_DMA_BASE + 0x64)
-#define OMAP_DMA4_CAPS_2                (OMAP24XX_DMA_BASE + 0x6c)
-#define OMAP_DMA4_CAPS_3                (OMAP24XX_DMA_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4                (OMAP24XX_DMA_BASE + 0x74)
+#if defined(CONFIG_ARCH_OMAP3)
+#define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
+#else   /* CONFIG_ARCH_OMAP2 */
+#define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
+#endif
+
+#define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
+#define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
+#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
+#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
+#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
+#define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
+#define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
+#define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
+#define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
 
 #ifdef CONFIG_ARCH_OMAP1
 
@@ -86,19 +92,19 @@
 #define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
 
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
-#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
-#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
-#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
-#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
-#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
-#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
-#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
-#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
-#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
-#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
+#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
 
 #endif
 
@@ -113,11 +119,11 @@
 #define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
 
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
+#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
+#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
+#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
+#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
+#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
 
 /*----------------------------------------------------------------------------*/
 
@@ -297,6 +303,10 @@
 #define OMAP_DMA_SYNC_ELEMENT           0x00
 #define OMAP_DMA_SYNC_FRAME             0x01
 #define OMAP_DMA_SYNC_BLOCK             0x02
+#define OMAP_DMA_SYNC_PACKET            0x03
+
+#define OMAP_DMA_SRC_SYNC               0x01
+#define OMAP_DMA_DST_SYNC               0x00
 
 #define OMAP_DMA_PORT_EMIFF             0x00
 #define OMAP_DMA_PORT_EMIFS             0x01
@@ -310,6 +320,29 @@
 #define OMAP_DMA_AMODE_SINGLE_IDX       0x02
 #define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
 
+#define DMA_DEFAULT_FIFO_DEPTH          0x10
+#define DMA_DEFAULT_ARB_RATE            0x01
+/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
+#define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
+#define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
+#define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
+#define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
+#define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
+#define DMA_THREAD_FIFO_75              (0x01 << 14)
+#define DMA_THREAD_FIFO_25              (0x02 << 14)
+#define DMA_THREAD_FIFO_50              (0x03 << 14)
+
+/* Chaining modes*/
+#ifndef CONFIG_ARCH_OMAP1
+#define OMAP_DMA_STATIC_CHAIN           0x1
+#define OMAP_DMA_DYNAMIC_CHAIN          0x2
+#define OMAP_DMA_CHAIN_ACTIVE           0x1
+#define OMAP_DMA_CHAIN_INACTIVE         0x0
+#endif
+
+#define DMA_CH_PRIO_HIGH                0x1
+#define DMA_CH_PRIO_LOW                 0x0 /* Def */
+
 /* LCD DMA block numbers */
 enum {
         OMAP_LCD_DMA_B1_TOP,
@@ -359,6 +392,13 @@ struct omap_dma_channel_params {
         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 
         int ie;                 /* interrupt enabled */
+
+        unsigned char read_prio;/* read priority */
+        unsigned char write_prio;/* write priority */
+
+#ifndef CONFIG_ARCH_OMAP1
+        enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
+#endif
 };
 
 
@@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch);
 extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
 extern int omap_dma_running(void);
+extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
+                                       int tparams);
+extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
+                                 unsigned char write_prio);
+
+/* Chaining APIs */
+#ifndef CONFIG_ARCH_OMAP1
+extern int omap_request_dma_chain(int dev_id, const char *dev_name,
+                                  void (*callback) (int chain_id, u16 ch_status,
+                                                    void *data),
+                                  int *chain_id, int no_of_chans,
+                                  int chain_mode,
+                                  struct omap_dma_channel_params params);
+extern int omap_free_dma_chain(int chain_id);
+extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
+                                     int dest_start, int elem_count,
+                                     int frame_count, void *callbk_data);
+extern int omap_start_dma_chain_transfers(int chain_id);
+extern int omap_stop_dma_chain_transfers(int chain_id);
+extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
+extern int omap_get_dma_chain_dst_pos(int chain_id);
+extern int omap_get_dma_chain_src_pos(int chain_id);
+
+extern int omap_modify_dma_chain_params(int chain_id,
+                                        struct omap_dma_channel_params params);
+extern int omap_dma_chain_status(int chain_id);
+#endif
 
 /* LCD DMA functions */
 extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 97b397dd7e87..164da09be095 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -62,6 +62,8 @@
 #define OMAP_MPUIO_LATCH                0x34
 #endif
 
+#define OMAP34XX_NR_GPIOS               6
+
 #define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
 
@@ -75,6 +77,8 @@ extern void omap_free_gpio(int gpio);
 extern void omap_set_gpio_direction(int gpio, int is_input);
 extern void omap_set_gpio_dataout(int gpio, int enable);
 extern int omap_get_gpio_datain(int gpio);
+extern void omap_set_gpio_debounce(int gpio, int enable);
+extern void omap_set_gpio_debounce_time(int gpio, int enable);
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 3ede58b51db2..87973654e625 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -263,6 +263,8 @@
 #define INT_24XX_GPTIMER10      46
 #define INT_24XX_GPTIMER11      47
 #define INT_24XX_GPTIMER12      48
+#define INT_24XX_I2C1_IRQ       56
+#define INT_24XX_I2C2_IRQ       57
 #define INT_24XX_MCBSP1_IRQ_TX  59
 #define INT_24XX_MCBSP1_IRQ_RX  60
 #define INT_24XX_MCBSP2_IRQ_TX  62
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h
new file mode 100644
index 000000000000..17ae26e35353
--- /dev/null
+++ b/include/asm-arm/arch-omap/nand.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-omap/nand.h
+ *
+ * Copyright (C) 2006 Micron Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/mtd/partitions.h>
+
+struct omap_nand_platform_data {
+        unsigned int            options;
+        int                     cs;
+        int                     gpio_irq;
+        struct mtd_partition    *parts;
+        int                     nr_parts;
+        int                     (*nand_setup)(void __iomem *);
+        int                     (*dev_ready)(struct omap_nand_platform_data *);
+        int                     dma_channel;
+        void __iomem            *gpmc_cs_baseaddr;
+        void __iomem            *gpmc_baseaddr;
+};
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
index e2a80641f214..2746220f5d85 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -8,9 +8,14 @@
  * published by the Free Software Foundation.
 */
 
+#include <asm/arch/orion.h>
+
         .macro  addruart,rx
-        mov   \rx, #0xf1000000
-        orr   \rx, \rx, #0x00012000
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =ORION_REGS_PHYS_BASE
+        ldrne   \rx, =ORION_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
index b76075a7e44b..cda096b2acfd 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -3,8 +3,8 @@
  *
  * Low-level IRQ helper macros for Orion platforms
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
index 8a12d213fbdc..65da374de735 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -4,7 +4,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
  */
 
 #ifndef __ASM_ARCH_HARDWARE_H__
@@ -12,13 +11,11 @@
 
 #include "orion.h"
 
-#define PCI_MEMORY_VADDR        ORION_PCI_SYS_MEM_BASE
-#define PCI_IO_VADDR            ORION_PCI_SYS_IO_BASE
+#define pcibios_assign_all_busses()     1
 
-#define pcibios_assign_all_busses()  1
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         0x01000000
+#define PCIMEM_BASE             ORION_PCIE_MEM_PHYS_BASE
 
-#define PCIBIOS_MIN_IO  0x1000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE     PCI_MEMORY_VADDR /* mem base for VGA */
 
-#endif  /* _ASM_ARCH_HARDWARE_H */
+#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
index f787f752e58c..673a418a7419 100644
--- a/include/asm-arm/arch-orion/orion.h
+++ b/include/asm-arm/arch-orion/orion.h
@@ -14,32 +14,40 @@
 #ifndef __ASM_ARCH_ORION_H__
 #define __ASM_ARCH_ORION_H__
 
-/*******************************************************************************
+/*****************************************************************************
  * Orion Address Map
- * Use the same mapping (1:1 virtual:physical) of internal registers and
- * PCI system (PCI+PCIE) for all machines.
- * Each machine defines the rest of its mapping (e.g. device bus flashes)
- ******************************************************************************/
-#define ORION_REGS_BASE         0xf1000000
+ *
+ * virt         phys            size
+ * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fde00000     f2000000        1M      PCIe I/O space
+ * fdf00000     f2100000        1M      PCI I/O space
+ * fe000000     f0000000        16M     PCIe WA space (Orion-NAS only)
+ ****************************************************************************/
+#define ORION_REGS_PHYS_BASE    0xf1000000
+#define ORION_REGS_VIRT_BASE    0xfdd00000
 #define ORION_REGS_SIZE         SZ_1M
 
-#define ORION_PCI_SYS_MEM_BASE  0xe0000000
-#define ORION_PCIE_MEM_BASE     ORION_PCI_SYS_MEM_BASE
-#define ORION_PCIE_MEM_SIZE     SZ_128M
-#define ORION_PCI_MEM_BASE      (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
-#define ORION_PCI_MEM_SIZE      SZ_128M
-
-#define ORION_PCI_SYS_IO_BASE   0xf2000000
-#define ORION_PCIE_IO_BASE      ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
+#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
+#define ORION_PCIE_IO_BUS_BASE  0x00000000
 #define ORION_PCIE_IO_SIZE      SZ_1M
-#define ORION_PCIE_IO_REMAP     (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
-#define ORION_PCI_IO_BASE       (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+
+#define ORION_PCI_IO_PHYS_BASE  0xf2100000
+#define ORION_PCI_IO_VIRT_BASE  0xfdf00000
+#define ORION_PCI_IO_BUS_BASE   0x00100000
 #define ORION_PCI_IO_SIZE       SZ_1M
-#define ORION_PCI_IO_REMAP      (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+
 /* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_BASE      0xf0000000
+#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
 #define ORION_PCIE_WA_SIZE      SZ_16M
 
+#define ORION_PCIE_MEM_PHYS_BASE        0xe0000000
+#define ORION_PCIE_MEM_SIZE             SZ_128M
+
+#define ORION_PCI_MEM_PHYS_BASE         0xe8000000
+#define ORION_PCI_MEM_SIZE              SZ_128M
+
 /*******************************************************************************
  * Supported Devices & Revisions
  ******************************************************************************/
@@ -57,25 +65,42 @@
 /*******************************************************************************
  * Orion Registers Map
  ******************************************************************************/
-#define ORION_DDR_REG_BASE      (ORION_REGS_BASE | 0x00000)
-#define ORION_DEV_BUS_REG_BASE  (ORION_REGS_BASE | 0x10000)
-#define ORION_BRIDGE_REG_BASE   (ORION_REGS_BASE | 0x20000)
-#define ORION_PCI_REG_BASE      (ORION_REGS_BASE | 0x30000)
-#define ORION_PCIE_REG_BASE     (ORION_REGS_BASE | 0x40000)
-#define ORION_USB0_REG_BASE     (ORION_REGS_BASE | 0x50000)
-#define ORION_ETH_REG_BASE      (ORION_REGS_BASE | 0x70000)
-#define ORION_SATA_REG_BASE     (ORION_REGS_BASE | 0x80000)
-#define ORION_USB1_REG_BASE     (ORION_REGS_BASE | 0xa0000)
-
-#define ORION_DDR_REG(x)        (ORION_DDR_REG_BASE | (x))
-#define ORION_DEV_BUS_REG(x)    (ORION_DEV_BUS_REG_BASE | (x))
-#define ORION_BRIDGE_REG(x)     (ORION_BRIDGE_REG_BASE | (x))
-#define ORION_PCI_REG(x)        (ORION_PCI_REG_BASE | (x))
-#define ORION_PCIE_REG(x)       (ORION_PCIE_REG_BASE | (x))
-#define ORION_USB0_REG(x)       (ORION_USB0_REG_BASE | (x))
-#define ORION_USB1_REG(x)       (ORION_USB1_REG_BASE | (x))
-#define ORION_ETH_REG(x)        (ORION_ETH_REG_BASE | (x))
-#define ORION_SATA_REG(x)       (ORION_SATA_REG_BASE | (x))
+#define ORION_DDR_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x00000)
+#define ORION_DDR_REG(x)                (ORION_DDR_VIRT_BASE | (x))
+
+#define ORION_DEV_BUS_PHYS_BASE         (ORION_REGS_PHYS_BASE | 0x10000)
+#define ORION_DEV_BUS_VIRT_BASE         (ORION_REGS_VIRT_BASE | 0x10000)
+#define ORION_DEV_BUS_REG(x)            (ORION_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION_BRIDGE_VIRT_BASE          (ORION_REGS_VIRT_BASE | 0x20000)
+#define ORION_BRIDGE_REG(x)             (ORION_BRIDGE_VIRT_BASE | (x))
+
+#define ORION_PCI_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x30000)
+#define ORION_PCI_REG(x)                (ORION_PCI_VIRT_BASE | (x))
+
+#define ORION_PCIE_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x40000)
+#define ORION_PCIE_REG(x)               (ORION_PCIE_VIRT_BASE | (x))
+
+#define ORION_USB0_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x50000)
+#define ORION_USB0_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x50000)
+#define ORION_USB0_REG(x)               (ORION_USB0_VIRT_BASE | (x))
+
+#define ORION_ETH_PHYS_BASE             (ORION_REGS_PHYS_BASE | 0x70000)
+#define ORION_ETH_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x70000)
+#define ORION_ETH_REG(x)                (ORION_ETH_VIRT_BASE | (x))
+
+#define ORION_SATA_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x80000)
+#define ORION_SATA_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x80000)
+#define ORION_SATA_REG(x)               (ORION_SATA_VIRT_BASE | (x))
+
+#define ORION_USB1_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0xa0000)
+#define ORION_USB1_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0xa0000)
+#define ORION_USB1_REG(x)               (ORION_USB1_VIRT_BASE | (x))
 
 /*******************************************************************************
  * Device Bus Registers
@@ -100,9 +125,6 @@
 #define DEV_BUS_CTRL            ORION_DEV_BUS_REG(0x4c0)
 #define DEV_BUS_INT_CAUSE       ORION_DEV_BUS_REG(0x4d0)
 #define DEV_BUS_INT_MASK        ORION_DEV_BUS_REG(0x4d4)
-#define I2C_BASE                ORION_DEV_BUS_REG(0x1000)
-#define UART0_BASE              ORION_DEV_BUS_REG(0x2000)
-#define UART1_BASE              ORION_DEV_BUS_REG(0x2100)
 #define GPIO_MAX                32
 
 /***************************************************************************
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
index a1a222fb438c..59f44039909a 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -10,8 +10,8 @@
 
 #include <asm/arch/orion.h>
 
-#define MV_UART_LSR     ((volatile unsigned char *)(UART0_BASE + 0x14))
-#define MV_UART_THR     ((volatile unsigned char *)(UART0_BASE + 0x0))
+#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
 
 #define LSR_THRE        0x20
 
@@ -27,16 +27,6 @@ static void flush(void)
 {
 }
 
-static void orion_early_putstr(const char *ptr)
-{
-        char c;
-        while ((c = *ptr++) != '\0') {
-                if (c == '\n')
-                        putc('\r');
-                putc(c);
-        }
-}
-
 /*
  * nothing to do
  */
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
index 23e2a102fe0c..9d580278d2bc 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -2,4 +2,4 @@
  * include/asm-arm/arch-orion/vmalloc.h
  */
 
-#define VMALLOC_END       0xf0000000
+#define VMALLOC_END       0xfd800000