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authorDan Williams <dan.j.williams@intel.com>2011-02-14 06:36:51 -0500
committerDan Williams <dan.j.williams@intel.com>2011-02-14 06:36:51 -0500
commit0670e7157f75ec6d2231fbc6f67b075d6b6d486f (patch)
tree64591858de42da54afc979338ee083d1e6d672a0 /include
parent80cc07af0f6692a7d8fdc5087594d1988a701266 (diff)
parent4aa5f366431fef0afca0df348ca9782c63ac9911 (diff)
Merge branch 'dw_dmac' into dmaengine
Diffstat (limited to 'include')
-rw-r--r--include/linux/dw_dmac.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index c8aad713a046..deec66b37180 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -16,9 +16,12 @@
16/** 16/**
17 * struct dw_dma_platform_data - Controller configuration parameters 17 * struct dw_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8) 18 * @nr_channels: Number of channels supported by hardware (max 8)
19 * @is_private: The device channels should be marked as private and not for
20 * by the general purpose DMA channel allocator.
19 */ 21 */
20struct dw_dma_platform_data { 22struct dw_dma_platform_data {
21 unsigned int nr_channels; 23 unsigned int nr_channels;
24 bool is_private;
22}; 25};
23 26
24/** 27/**
@@ -52,6 +55,8 @@ struct dw_dma_slave {
52 enum dw_dma_slave_width reg_width; 55 enum dw_dma_slave_width reg_width;
53 u32 cfg_hi; 56 u32 cfg_hi;
54 u32 cfg_lo; 57 u32 cfg_lo;
58 int src_master;
59 int dst_master;
55}; 60};
56 61
57/* Platform-configurable bits in CFG_HI */ 62/* Platform-configurable bits in CFG_HI */