diff options
| author | Jingoo Han <jg1.han@samsung.com> | 2012-09-25 02:48:20 -0400 |
|---|---|---|
| committer | Jingoo Han <jg1.han@samsung.com> | 2012-11-25 23:35:34 -0500 |
| commit | 9d07a0bf444c7bafc940ea8f3ba1b1bbbed09793 (patch) | |
| tree | 4695f151793bd48925542ce25d2ab563447107a3 /include/video | |
| parent | 36ff8d54ca6f3c251f0b7536bac3c38c57439e23 (diff) | |
video: s3c-fb: move the address definitions for VIDTCON registers
The address definitions for VIDTCON registers are moved to right
place.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'include/video')
| -rw-r--r-- | include/video/samsung_fimd.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index bd0a04e478eb..bc22f3ccb7b1 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h | |||
| @@ -116,6 +116,7 @@ | |||
| 116 | 116 | ||
| 117 | /* VIDTCON0 */ | 117 | /* VIDTCON0 */ |
| 118 | 118 | ||
| 119 | #define VIDTCON0 (0x10) | ||
| 119 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | 120 | #define VIDTCON0_VBPDE_MASK (0xff << 24) |
| 120 | #define VIDTCON0_VBPDE_SHIFT (24) | 121 | #define VIDTCON0_VBPDE_SHIFT (24) |
| 121 | #define VIDTCON0_VBPDE_LIMIT (0xff) | 122 | #define VIDTCON0_VBPDE_LIMIT (0xff) |
| @@ -138,6 +139,7 @@ | |||
| 138 | 139 | ||
| 139 | /* VIDTCON1 */ | 140 | /* VIDTCON1 */ |
| 140 | 141 | ||
| 142 | #define VIDTCON1 (0x14) | ||
| 141 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | 143 | #define VIDTCON1_VFPDE_MASK (0xff << 24) |
| 142 | #define VIDTCON1_VFPDE_SHIFT (24) | 144 | #define VIDTCON1_VFPDE_SHIFT (24) |
| 143 | #define VIDTCON1_VFPDE_LIMIT (0xff) | 145 | #define VIDTCON1_VFPDE_LIMIT (0xff) |
| @@ -159,6 +161,7 @@ | |||
| 159 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | 161 | #define VIDTCON1_HSPW(_x) ((_x) << 0) |
| 160 | 162 | ||
| 161 | #define VIDTCON2 (0x18) | 163 | #define VIDTCON2 (0x18) |
| 164 | #define VIDTCON2 (0x18) | ||
| 162 | #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) | 165 | #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) |
| 163 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | 166 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) |
| 164 | #define VIDTCON2_LINEVAL_SHIFT (11) | 167 | #define VIDTCON2_LINEVAL_SHIFT (11) |
| @@ -405,11 +408,6 @@ | |||
| 405 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | 408 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ |
| 406 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | 409 | #define VIDCON1_FSTATUS_EVEN (1 << 15) |
| 407 | 410 | ||
| 408 | /* Video timing controls */ | ||
| 409 | #define VIDTCON0 (0x10) | ||
| 410 | #define VIDTCON1 (0x14) | ||
| 411 | #define VIDTCON2 (0x18) | ||
| 412 | |||
| 413 | /* OSD1 and OSD4 do not have register D */ | 411 | /* OSD1 and OSD4 do not have register D */ |
| 414 | 412 | ||
| 415 | #define VIDOSD_BASE (0x40) | 413 | #define VIDOSD_BASE (0x40) |
