drm/radeon: add si tile mode array query v3

Allow userspace to query for the tile mode array so userspace can properly
compute surface pitch and alignment requirement depending on tiling.

v2: Make strict aliasing safer by casting to char when copying
v3: merge fix from Christian

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 05ed0107584d..321d4ac5c512 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -977,6 +977,8 @@ struct drm_radeon_cs {
 #define RADEON_INFO_FASTFB_WORKING      0x14
 /* query if a RADEON_CS_RING_* submission is supported */
 #define RADEON_INFO_RING_WORKING        0x15
+/* SI tile mode array */
+#define RADEON_INFO_SI_TILE_MODE_ARRAY  0x16
 
 
 struct drm_radeon_info {
@@ -985,4 +987,22 @@ struct drm_radeon_info {
         uint64_t                value;
 };
 
+/* Those correspond to the tile index to use, this is to explicitly state
+ * the API that is implicitly defined by the tile mode array.
+ */
+#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED       8
+#define SI_TILE_MODE_COLOR_1D                   13
+#define SI_TILE_MODE_COLOR_1D_SCANOUT           9
+#define SI_TILE_MODE_COLOR_2D_8BPP              14
+#define SI_TILE_MODE_COLOR_2D_16BPP             15
+#define SI_TILE_MODE_COLOR_2D_32BPP             16
+#define SI_TILE_MODE_COLOR_2D_64BPP             17
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP     11
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP     12
+#define SI_TILE_MODE_DEPTH_STENCIL_1D           4
+#define SI_TILE_MODE_DEPTH_STENCIL_2D           0
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA       3
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA       3
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA       2
+
 #endif