diff options
| author | Stephane Eranian <eranian@google.com> | 2013-04-05 10:49:41 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2013-04-08 07:54:24 -0400 |
| commit | cc2f5a8adbc7ab1fdb7d9bcf4ea9838c73e82dfe (patch) | |
| tree | a98f82a6060c5f59f1a8bea19986076343148a67 /include/uapi/linux | |
| parent | 529801898b24544f93532217ce18a7ebbb2b8c4f (diff) | |
perf: Fix comments in PERF_MEM_LVL bitmask
This small patch fixes a mistake in the comments
for the PERF_MEM_LVL_* events. The L2, L3 bits simply
represent cache levels, not hits or misses. That is
encoded in PERF_MEM_LVL_MISS/PERF_MEM_LVL_HIT.
Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: jolsa@redhat.com
Link: http://lkml.kernel.org/r/20130405144941.GA30503@quad
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/perf_event.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 964a450a6e2c..fb104e51496e 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h | |||
| @@ -645,8 +645,8 @@ union perf_mem_data_src { | |||
| 645 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ | 645 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ |
| 646 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ | 646 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ |
| 647 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ | 647 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ |
| 648 | #define PERF_MEM_LVL_L2 0x20 /* L2 hit */ | 648 | #define PERF_MEM_LVL_L2 0x20 /* L2 */ |
| 649 | #define PERF_MEM_LVL_L3 0x40 /* L3 hit */ | 649 | #define PERF_MEM_LVL_L3 0x40 /* L3 */ |
| 650 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ | 650 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ |
| 651 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ | 651 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ |
| 652 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ | 652 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ |
