Merge remote branch 'origin/master' into next-merge

7 files changed, 217 insertions, 69 deletions

diff --git a/include/uapi/linux/cm4000_cs.h b/include/uapi/linux/cm4000_cs.h
index bc51f77db918..1217f751a1bc 100644
--- a/include/uapi/linux/cm4000_cs.h
+++ b/include/uapi/linux/cm4000_cs.h
@@ -2,6 +2,7 @@
 #define _UAPI_CM4000_H_
 
 #include <linux/types.h>
+#include <linux/ioctl.h>
 
 #define MAX_ATR                 33
 
diff --git a/include/uapi/linux/ip.h b/include/uapi/linux/ip.h
index 6cf06bfd841b..2fee45bdec0a 100644
--- a/include/uapi/linux/ip.h
+++ b/include/uapi/linux/ip.h
@@ -133,4 +133,38 @@ struct ip_beet_phdr {
         __u8 reserved;
 };
 
+/* index values for the variables in ipv4_devconf */
+enum
+{
+        IPV4_DEVCONF_FORWARDING=1,
+        IPV4_DEVCONF_MC_FORWARDING,
+        IPV4_DEVCONF_PROXY_ARP,
+        IPV4_DEVCONF_ACCEPT_REDIRECTS,
+        IPV4_DEVCONF_SECURE_REDIRECTS,
+        IPV4_DEVCONF_SEND_REDIRECTS,
+        IPV4_DEVCONF_SHARED_MEDIA,
+        IPV4_DEVCONF_RP_FILTER,
+        IPV4_DEVCONF_ACCEPT_SOURCE_ROUTE,
+        IPV4_DEVCONF_BOOTP_RELAY,
+        IPV4_DEVCONF_LOG_MARTIANS,
+        IPV4_DEVCONF_TAG,
+        IPV4_DEVCONF_ARPFILTER,
+        IPV4_DEVCONF_MEDIUM_ID,
+        IPV4_DEVCONF_NOXFRM,
+        IPV4_DEVCONF_NOPOLICY,
+        IPV4_DEVCONF_FORCE_IGMP_VERSION,
+        IPV4_DEVCONF_ARP_ANNOUNCE,
+        IPV4_DEVCONF_ARP_IGNORE,
+        IPV4_DEVCONF_PROMOTE_SECONDARIES,
+        IPV4_DEVCONF_ARP_ACCEPT,
+        IPV4_DEVCONF_ARP_NOTIFY,
+        IPV4_DEVCONF_ACCEPT_LOCAL,
+        IPV4_DEVCONF_SRC_VMARK,
+        IPV4_DEVCONF_PROXY_ARP_PVLAN,
+        IPV4_DEVCONF_ROUTE_LOCALNET,
+        __IPV4_DEVCONF_MAX
+};
+
+#define IPV4_DEVCONF_MAX (__IPV4_DEVCONF_MAX - 1)
+
 #endif /* _UAPI_LINUX_IP_H */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index c3cc01d474b0..baa7852468ef 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -421,24 +421,24 @@
 #define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
 #define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCIe to PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIe Bridge */
 #define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 #define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
-#define  PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
-#define  PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
-#define  PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
-#define  PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
-#define  PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
-#define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
-#define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
-#define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
-#define  PCI_EXP_DEVCAP_RBER    0x8000  /* Role-Based Error Reporting */
-#define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
-#define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
+#define  PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
+#define  PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */
+#define  PCI_EXP_DEVCAP_L0S     0x000001c0 /* L0s Acceptable Latency */
+#define  PCI_EXP_DEVCAP_L1      0x00000e00 /* L1 Acceptable Latency */
+#define  PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */
+#define  PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBER    0x00008000 /* Role-Based Error Reporting */
+#define  PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */
+#define  PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */
 #define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL          8       /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
@@ -454,16 +454,16 @@
 #define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
 #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA          10      /* Device Status */
-#define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
-#define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
-#define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
-#define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
+#define  PCI_EXP_DEVSTA_CED     0x0001  /* Correctable Error Detected */
+#define  PCI_EXP_DEVSTA_NFED    0x0002  /* Non-Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_FED     0x0004  /* Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_URD     0x0008  /* Unsupported Request Detected */
+#define  PCI_EXP_DEVSTA_AUXPD   0x0010  /* AUX Power Detected */
+#define  PCI_EXP_DEVSTA_TRPND   0x0020  /* Transactions Pending */
 #define PCI_EXP_LNKCAP          12      /* Link Capabilities */
 #define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
-#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x1   /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
-#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x2   /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
+#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
+#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 #define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
@@ -475,21 +475,21 @@
 #define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL          16      /* Link Control */
 #define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
-#define  PCI_EXP_LNKCTL_ASPM_L0S  0x01  /* L0s Enable */
-#define  PCI_EXP_LNKCTL_ASPM_L1   0x02  /* L1 Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L1  0x0002 /* L1 Enable */
 #define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
 #define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
 #define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
 #define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
-#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
+#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
 #define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
 #define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
 #define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
 #define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
-#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01  /* Current Link Speed 2.5GT/s */
-#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02  /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
 #define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
 #define  PCI_EXP_LNKSTA_NLW_SHIFT 4     /* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
@@ -534,44 +534,49 @@
 #define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
 #define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL           28      /* Root Control */
-#define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE    0x04    /* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE    0x08    /* PME Interrupt Enable */
-#define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
+#define  PCI_EXP_RTCTL_SECEE    0x0001  /* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE   0x0002  /* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE    0x0004  /* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE    0x0008  /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSSVE   0x0010  /* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP           30      /* Root Capabilities */
 #define PCI_EXP_RTSTA           32      /* Root Status */
-#define PCI_EXP_RTSTA_PME       0x10000 /* PME status */
-#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
+#define PCI_EXP_RTSTA_PME       0x00010000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING   0x00020000 /* PME pending */
 /*
- * Note that the following PCI Express 'Capability Structure' registers
- * were introduced with 'Capability Version' 0x2 (v2).  These registers
- * do not exist on devices with Capability Version 1.  Use pci_pcie_cap2()
- * to use these fields safely.
+ * The Device Capabilities 2, Device Status 2, Device Control 2,
+ * Link Capabilities 2, Link Status 2, Link Control 2,
+ * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
+ * are only present on devices with PCIe Capability version 2.
+ * Use pcie_capability_read_word() and similar interfaces to use them
+ * safely.
  */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
-#define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
-#define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
-#define  PCI_EXP_OBFF_MASK      0xc0000 /* OBFF support mechanism */
-#define  PCI_EXP_OBFF_MSG       0x40000 /* New message signaling */
-#define  PCI_EXP_OBFF_WAKE      0x80000 /* Re-use WAKE# for OBFF */
+#define  PCI_EXP_DEVCAP2_ARI            0x00000020 /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR            0x00000800 /* Latency tolerance reporting */
+#define  PCI_EXP_DEVCAP2_OBFF_MASK      0x000c0000 /* OBFF support mechanism */
+#define  PCI_EXP_DEVCAP2_OBFF_MSG       0x00040000 /* New message signaling */
+#define  PCI_EXP_DEVCAP2_OBFF_WAKE      0x00080000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
-#define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
-#define  PCI_EXP_IDO_REQ_EN     0x100   /* ID-based ordering request enable */
-#define  PCI_EXP_IDO_CMP_EN     0x200   /* ID-based ordering completion enable */
-#define  PCI_EXP_LTR_EN         0x400   /* Latency tolerance reporting */
-#define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
-#define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
-#define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
+#define  PCI_EXP_DEVCTL2_ARI            0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCTL2_IDO_REQ_EN     0x0100  /* Allow IDO for requests */
+#define  PCI_EXP_DEVCTL2_IDO_CMP_EN     0x0200  /* Allow IDO for completions */
+#define  PCI_EXP_DEVCTL2_LTR_EN         0x0400  /* Enable LTR mechanism */
+#define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN   0x2000  /* Enable OBFF Message type A */
+#define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN   0x4000  /* Enable OBFF Message type B */
+#define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
+#define PCI_EXP_DEVSTA2         42      /* Device Status 2 */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  44      /* v2 endpoints end here */
-#define PCI_EXP_LNKCAP2         44      /* Link Capability 2 */
-#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
-#define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
+#define PCI_EXP_LNKCAP2         44      /* Link Capabilities 2 */
+#define  PCI_EXP_LNKCAP2_SLS_2_5GB      0x00000002 /* Supported Speed 2.5GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_5_0GB      0x00000004 /* Supported Speed 5.0GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_8_0GB      0x00000008 /* Supported Speed 8.0GT/s */
+#define  PCI_EXP_LNKCAP2_CROSSLINK      0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 #define PCI_EXP_LNKSTA2         50      /* Link Status 2 */
+#define PCI_EXP_SLTCAP2         52      /* Slot Capabilities 2 */
 #define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
+#define PCI_EXP_SLTSTA2         58      /* Slot Status 2 */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 0b1df41691e8..ca1d90bcb74d 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -109,6 +109,7 @@ enum perf_sw_ids {
         PERF_COUNT_SW_PAGE_FAULTS_MAJ           = 6,
         PERF_COUNT_SW_ALIGNMENT_FAULTS          = 7,
         PERF_COUNT_SW_EMULATION_FAULTS          = 8,
+        PERF_COUNT_SW_DUMMY                     = 9,
 
         PERF_COUNT_SW_MAX,                      /* non-ABI */
 };
@@ -134,8 +135,9 @@ enum perf_event_sample_format {
         PERF_SAMPLE_STACK_USER                  = 1U << 13,
         PERF_SAMPLE_WEIGHT                      = 1U << 14,
         PERF_SAMPLE_DATA_SRC                    = 1U << 15,
+        PERF_SAMPLE_IDENTIFIER                  = 1U << 16,
 
-        PERF_SAMPLE_MAX = 1U << 16,             /* non-ABI */
+        PERF_SAMPLE_MAX = 1U << 17,             /* non-ABI */
 };
 
 /*
@@ -275,8 +277,9 @@ struct perf_event_attr {
 
                                 exclude_callchain_kernel : 1, /* exclude kernel callchains */
                                 exclude_callchain_user   : 1, /* exclude user callchains */
+                                mmap2          :  1, /* include mmap with inode data     */
 
-                                __reserved_1   : 41;
+                                __reserved_1   : 40;
 
         union {
                 __u32           wakeup_events;    /* wakeup every n events */
@@ -321,6 +324,7 @@ struct perf_event_attr {
 #define PERF_EVENT_IOC_PERIOD           _IOW('$', 4, __u64)
 #define PERF_EVENT_IOC_SET_OUTPUT       _IO ('$', 5)
 #define PERF_EVENT_IOC_SET_FILTER       _IOW('$', 6, char *)
+#define PERF_EVENT_IOC_ID               _IOR('$', 7, u64 *)
 
 enum perf_event_ioc_flags {
         PERF_IOC_FLAG_GROUP             = 1U << 0,
@@ -375,9 +379,12 @@ struct perf_event_mmap_page {
         __u64   time_running;           /* time event on cpu */
         union {
                 __u64   capabilities;
-                __u64   cap_usr_time  : 1,
-                        cap_usr_rdpmc : 1,
-                        cap_____res   : 62;
+                struct {
+                        __u64   cap_usr_time            : 1,
+                                cap_usr_rdpmc           : 1,
+                                cap_usr_time_zero       : 1,
+                                cap_____res             : 61;
+                };
         };
 
         /*
@@ -418,12 +425,29 @@ struct perf_event_mmap_page {
         __u16   time_shift;
         __u32   time_mult;
         __u64   time_offset;
+        /*
+         * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
+         * from sample timestamps.
+         *
+         *   time = timestamp - time_zero;
+         *   quot = time / time_mult;
+         *   rem  = time % time_mult;
+         *   cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
+         *
+         * And vice versa:
+         *
+         *   quot = cyc >> time_shift;
+         *   rem  = cyc & ((1 << time_shift) - 1);
+         *   timestamp = time_zero + quot * time_mult +
+         *               ((rem * time_mult) >> time_shift);
+         */
+        __u64   time_zero;
 
                 /*
                  * Hole for extension of the self monitor capabilities
                  */
 
-        __u64   __reserved[120];        /* align to 1k */
+        __u64   __reserved[119];        /* align to 1k */
 
         /*
          * Control data for the mmap() data buffer.
@@ -471,13 +495,28 @@ enum perf_event_type {
         /*
          * If perf_event_attr.sample_id_all is set then all event types will
          * have the sample_type selected fields related to where/when
-         * (identity) an event took place (TID, TIME, ID, CPU, STREAM_ID)
-         * described in PERF_RECORD_SAMPLE below, it will be stashed just after
-         * the perf_event_header and the fields already present for the existing
-         * fields, i.e. at the end of the payload. That way a newer perf.data
-         * file will be supported by older perf tools, with these new optional
-         * fields being ignored.
+         * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
+         * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
+         * just after the perf_event_header and the fields already present for
+         * the existing fields, i.e. at the end of the payload. That way a newer
+         * perf.data file will be supported by older perf tools, with these new
+         * optional fields being ignored.
+         *
+         * struct sample_id {
+         *      { u32                   pid, tid; } && PERF_SAMPLE_TID
+         *      { u64                   time;     } && PERF_SAMPLE_TIME
+         *      { u64                   id;       } && PERF_SAMPLE_ID
+         *      { u64                   stream_id;} && PERF_SAMPLE_STREAM_ID
+         *      { u32                   cpu, res; } && PERF_SAMPLE_CPU
+         *      { u64                   id;       } && PERF_SAMPLE_IDENTIFIER
+         * } && perf_event_attr::sample_id_all
          *
+         * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.  The
+         * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
+         * relative to header.size.
+         */
+
+        /*
          * The MMAP events record the PROT_EXEC mappings so that we can
          * correlate userspace IPs to code. They have the following structure:
          *
@@ -498,6 +537,7 @@ enum perf_event_type {
          *      struct perf_event_header        header;
          *      u64                             id;
          *      u64                             lost;
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_LOST                        = 2,
@@ -508,6 +548,7 @@ enum perf_event_type {
          *
          *      u32                             pid, tid;
          *      char                            comm[];
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_COMM                        = 3,
@@ -518,6 +559,7 @@ enum perf_event_type {
          *      u32                             pid, ppid;
          *      u32                             tid, ptid;
          *      u64                             time;
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_EXIT                        = 4,
@@ -528,6 +570,7 @@ enum perf_event_type {
          *      u64                             time;
          *      u64                             id;
          *      u64                             stream_id;
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_THROTTLE                    = 5,
@@ -539,6 +582,7 @@ enum perf_event_type {
          *      u32                             pid, ppid;
          *      u32                             tid, ptid;
          *      u64                             time;
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_FORK                        = 7,
@@ -549,6 +593,7 @@ enum perf_event_type {
          *      u32                             pid, tid;
          *
          *      struct read_format              values;
+         *      struct sample_id                sample_id;
          * };
          */
         PERF_RECORD_READ                        = 8,
@@ -557,6 +602,13 @@ enum perf_event_type {
          * struct {
          *      struct perf_event_header        header;
          *
+         *      #
+         *      # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
+         *      # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
+         *      # is fixed relative to header.
+         *      #
+         *
+         *      { u64                   id;       } && PERF_SAMPLE_IDENTIFIER
          *      { u64                   ip;       } && PERF_SAMPLE_IP
          *      { u32                   pid, tid; } && PERF_SAMPLE_TID
          *      { u64                   time;     } && PERF_SAMPLE_TIME
@@ -596,11 +648,32 @@ enum perf_event_type {
          *        u64                   dyn_size; } && PERF_SAMPLE_STACK_USER
          *
          *      { u64                   weight;   } && PERF_SAMPLE_WEIGHT
-         *      { u64                   data_src;     } && PERF_SAMPLE_DATA_SRC
+         *      { u64                   data_src; } && PERF_SAMPLE_DATA_SRC
          * };
          */
         PERF_RECORD_SAMPLE                      = 9,
 
+        /*
+         * The MMAP2 records are an augmented version of MMAP, they add
+         * maj, min, ino numbers to be used to uniquely identify each mapping
+         *
+         * struct {
+         *      struct perf_event_header        header;
+         *
+         *      u32                             pid, tid;
+         *      u64                             addr;
+         *      u64                             len;
+         *      u64                             pgoff;
+         *      u32                             maj;
+         *      u32                             min;
+         *      u64                             ino;
+         *      u64                             ino_generation;
+         *      char                            filename[];
+         *      struct sample_id                sample_id;
+         * };
+         */
+        PERF_RECORD_MMAP2                       = 10,
+
         PERF_RECORD_MAX,                        /* non-ABI */
 };
 
@@ -685,4 +758,28 @@ union perf_mem_data_src {
 #define PERF_MEM_S(a, s) \
         (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
 
+/*
+ * single taken branch record layout:
+ *
+ *      from: source instruction (may not always be a branch insn)
+ *        to: branch target
+ *   mispred: branch target was mispredicted
+ * predicted: branch target was predicted
+ *
+ * support for mispred, predicted is optional. In case it
+ * is not supported mispred = predicted = 0.
+ *
+ *     in_tx: running in a hardware transaction
+ *     abort: aborting a hardware transaction
+ */
+struct perf_branch_entry {
+        __u64   from;
+        __u64   to;
+        __u64   mispred:1,  /* target mispredicted */
+                predicted:1,/* target predicted */
+                in_tx:1,    /* in transaction */
+                abort:1,    /* transaction abort */
+                reserved:60;
+};
+
 #endif /* _UAPI_LINUX_PERF_EVENT_H */
diff --git a/include/uapi/linux/pkt_sched.h b/include/uapi/linux/pkt_sched.h
index dbd71b0c7d8c..09d62b9228ff 100644
--- a/include/uapi/linux/pkt_sched.h
+++ b/include/uapi/linux/pkt_sched.h
@@ -73,9 +73,17 @@ struct tc_estimator {
 #define TC_H_ROOT       (0xFFFFFFFFU)
 #define TC_H_INGRESS    (0xFFFFFFF1U)
 
+/* Need to corrospond to iproute2 tc/tc_core.h "enum link_layer" */
+enum tc_link_layer {
+        TC_LINKLAYER_UNAWARE, /* Indicate unaware old iproute2 util */
+        TC_LINKLAYER_ETHERNET,
+        TC_LINKLAYER_ATM,
+};
+#define TC_LINKLAYER_MASK 0x0F /* limit use to lower 4 bits */
+
 struct tc_ratespec {
         unsigned char   cell_log;
-        unsigned char   __reserved;
+        __u8            linklayer; /* lower 4 bits */
         unsigned short  overhead;
         short           cell_align;
         unsigned short  mpu;
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 9119cc0977bf..e40ebe124ced 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -232,4 +232,7 @@
 /* SH-SCI */
 #define PORT_HSCIF      104
 
+/* ST ASC type numbers */
+#define PORT_ASC       105
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
diff --git a/include/uapi/linux/snmp.h b/include/uapi/linux/snmp.h
index af0a674cc677..a1356d3b54df 100644
--- a/include/uapi/linux/snmp.h
+++ b/include/uapi/linux/snmp.h
@@ -253,7 +253,7 @@ enum
         LINUX_MIB_TCPFASTOPENLISTENOVERFLOW,    /* TCPFastOpenListenOverflow */
         LINUX_MIB_TCPFASTOPENCOOKIEREQD,        /* TCPFastOpenCookieReqd */
         LINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES, /* TCPSpuriousRtxHostQueues */
-        LINUX_MIB_LOWLATENCYRXPACKETS,          /* LowLatencyRxPackets */
+        LINUX_MIB_BUSYPOLLRXPACKETS,            /* BusyPollRxPackets */
         __LINUX_MIB_MAX
 };