diff options
| author | Alex Williamson <alex.williamson@redhat.com> | 2013-12-17 18:43:57 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-12-17 19:49:39 -0500 |
| commit | 274127a1fdbad3c0d64e813521f4a0ef96cfc70e (patch) | |
| tree | 72c5702de4cfcb7337550f355af46f568c448022 /include/uapi/linux | |
| parent | 425c1b223dac456d00a61fd6b451b6d1cf00d065 (diff) | |
PCI: Rename PCI_VC_PORT_REG1/2 to PCI_VC_PORT_CAP1/2
These are set of two capability registers, it's pretty much given that
they're registers, so reflect their purpose in the name.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 5eefacd93e18..d0160cc83fcf 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h | |||
| @@ -677,15 +677,15 @@ | |||
| 677 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ | 677 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
| 678 | 678 | ||
| 679 | /* Virtual Channel */ | 679 | /* Virtual Channel */ |
| 680 | #define PCI_VC_PORT_REG1 4 | 680 | #define PCI_VC_PORT_CAP1 4 |
| 681 | #define PCI_VC_REG1_EVCC 0x00000007 /* extended VC count */ | 681 | #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ |
| 682 | #define PCI_VC_REG1_LPEVCC 0x00000070 /* low prio extended VC count */ | 682 | #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ |
| 683 | #define PCI_VC_REG1_ARB_SIZE 0x00000c00 | 683 | #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 |
| 684 | #define PCI_VC_PORT_REG2 8 | 684 | #define PCI_VC_PORT_CAP2 8 |
| 685 | #define PCI_VC_REG2_32_PHASE 0x00000002 | 685 | #define PCI_VC_CAP2_32_PHASE 0x00000002 |
| 686 | #define PCI_VC_REG2_64_PHASE 0x00000004 | 686 | #define PCI_VC_CAP2_64_PHASE 0x00000004 |
| 687 | #define PCI_VC_REG2_128_PHASE 0x00000008 | 687 | #define PCI_VC_CAP2_128_PHASE 0x00000008 |
| 688 | #define PCI_VC_REG2_ARB_OFF 0xff000000 | 688 | #define PCI_VC_CAP2_ARB_OFF 0xff000000 |
| 689 | #define PCI_VC_PORT_CTRL 12 | 689 | #define PCI_VC_PORT_CTRL 12 |
| 690 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 | 690 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 |
| 691 | #define PCI_VC_PORT_STATUS 14 | 691 | #define PCI_VC_PORT_STATUS 14 |
