Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media into next

Pull media updates from Mauro Carvalho Chehab:
 "This contains:
   - a new frontend/tuner driver set for si2168 and sa2157
   - Videobuf 2 core now supports DVB too
   - A new gspca sub-driver (dtcs033)
   - saa7134 is now converted to use videobuf2
   - add support for 4K timings
   - several other driver fixes and improvements

  PS.  This pull request is shorter than usual, partly because I have
  some other patches on topic branches that I'll be sending you later
  this week"

* 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (286 commits)
  [media] au0828-dvb: restore its permission to 644
  [media] xc5000: delay tuner sleep to 5 seconds
  [media] xc5000: Don't use whitespace before tabs
  [media] xc5000: fix CamelCase
  [media] xc5000: Don't wrap msleep()
  [media] xc5000: get rid of positive error codes
  [media] au0828: reset streaming when a new frequency is set
  [media] au0828: Improve debug messages for urb_completion
  [media] au0828: Cancel stream-restart operation if frontend is disconnected
  [media] dib0700: fix RC support on Hauppauge Nova-TD
  [media] USB: as102_usb_drv.c: Remove useless return variables
  [media] v4l: Fix documentation of V4L2_PIX_FMT_H264_MVC and VP8 pixel formats
  [media] m5mols: Replace missing header
  [media] staging: lirc: Fix sparse warnings
  [media] fix mceusb endpoint type identification/handling
  [media] az6027: Added the PID for a new revision of the Elgato EyeTV Sat DVB-S Tuner
  [media] DocBook media: fix typo
  [media] adv7604: Add missing include to linux/types.h
  [media] v4l: Validate fields in the core code for subdev EDID ioctls
  [media] v4l: Add support for DV timings ioctls on subdev nodes
  ...

1 files changed, 70 insertions, 0 deletions

diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h
index b6a5fe00a470..6c8f159e416e 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -173,6 +173,76 @@
                 V4L2_DV_FL_CAN_REDUCE_FPS) \
 }
 
+#define V4L2_DV_BT_CEA_3840X2160P24 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_3840X2160P25 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_3840X2160P30 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_3840X2160P50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_3840X2160P60 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_4096X2160P24 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_4096X2160P25 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_4096X2160P30 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_4096X2160P50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_4096X2160P60 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+                594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
 
 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */