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authorIngo Molnar <mingo@kernel.org>2015-02-24 02:41:07 -0500
committerIngo Molnar <mingo@kernel.org>2015-02-24 02:41:07 -0500
commit2ae79026818e7d49fead82b79b1a543e3b9c8a23 (patch)
treec7ee7bd8b37b0880918d361839fd95988fac2dac /include/uapi/linux/serial_core.h
parent1a99367023f6ac664365a37fa508b059e31d0e88 (diff)
parentc517d838eb7d07bbe9507871fab3931deccff539 (diff)
Merge tag 'v4.0-rc1' into locking/core, to refresh the tree before merging new changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/uapi/linux/serial_core.h')
-rw-r--r--include/uapi/linux/serial_core.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index c17218094f18..b2122813f18a 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -55,7 +55,8 @@
55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ 55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ 56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
57#define PORT_RT2880 29 /* Ralink RT2880 internal UART */ 57#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
58#define PORT_MAX_8250 29 /* max port ID */ 58#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
59#define PORT_MAX_8250 30 /* max port ID */
59 60
60/* 61/*
61 * ARM specific type numbers. These are not currently guaranteed 62 * ARM specific type numbers. These are not currently guaranteed
@@ -248,4 +249,13 @@
248/* MESON */ 249/* MESON */
249#define PORT_MESON 109 250#define PORT_MESON 109
250 251
252/* Conexant Digicolor */
253#define PORT_DIGICOLOR 110
254
255/* SPRD SERIAL */
256#define PORT_SPRD 111
257
258/* Cris v10 / v32 SoC */
259#define PORT_CRIS 112
260
251#endif /* _UAPILINUX_SERIAL_CORE_H */ 261#endif /* _UAPILINUX_SERIAL_CORE_H */