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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2015-01-15 12:46:14 -0500
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2015-01-15 12:46:14 -0500
commit0c49cd295d42d0032af11d55e2140dbec11dc8d0 (patch)
tree1e7d0e50b6b6d6e4de1fb6bb0b6d856c3932da58 /include/uapi/linux/serial_core.h
parent0c3e99437a66e4c869c60c2398449e6d98f3a988 (diff)
parenteaa27f34e91a14cdceed26ed6c6793ec1d186115 (diff)
Merge tag 'v3.19-rc4' into next
Merge with mainline to bring in the latest thermal and other changes.
Diffstat (limited to 'include/uapi/linux/serial_core.h')
-rw-r--r--include/uapi/linux/serial_core.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 5820269aa132..c17218094f18 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -54,7 +54,8 @@
54#define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ 54#define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ 55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ 56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
57#define PORT_MAX_8250 28 /* max port ID */ 57#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
58#define PORT_MAX_8250 29 /* max port ID */
58 59
59/* 60/*
60 * ARM specific type numbers. These are not currently guaranteed 61 * ARM specific type numbers. These are not currently guaranteed
@@ -244,4 +245,7 @@
244/* SC16IS74xx */ 245/* SC16IS74xx */
245#define PORT_SC16IS7XX 108 246#define PORT_SC16IS7XX 108
246 247
248/* MESON */
249#define PORT_MESON 109
250
247#endif /* _UAPILINUX_SERIAL_CORE_H */ 251#endif /* _UAPILINUX_SERIAL_CORE_H */