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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 06:06:33 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 06:06:33 -0500
commite790245eb3b437bb1d322cf3d5fbb603a138c9f7 (patch)
tree54469e8ec666cb4a03b541c218482f172b80bb24 /include/sound
parentd289323286d6b4e738458c31533da51d294d28a0 (diff)
parentfd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (diff)
Merge remote-tracking branch 'asoc/topic/cs4271' into asoc-next
Diffstat (limited to 'include/sound')
-rw-r--r--include/sound/cs4271.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/sound/cs4271.h b/include/sound/cs4271.h
index dd8c48d14ed9..70f45355acaa 100644
--- a/include/sound/cs4271.h
+++ b/include/sound/cs4271.h
@@ -20,6 +20,21 @@
20struct cs4271_platform_data { 20struct cs4271_platform_data {
21 int gpio_nreset; /* GPIO driving Reset pin, if any */ 21 int gpio_nreset; /* GPIO driving Reset pin, if any */
22 bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ 22 bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
23
24 /*
25 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
26 * line is de-asserted. That also means that clocks cannot be changed
27 * without putting the chip back into hardware reset, which also requires
28 * a complete re-initialization of all registers.
29 *
30 * One (undocumented) workaround is to assert and de-assert the PDN bit
31 * in the MODE2 register. This workaround can be enabled with the
32 * following flag.
33 *
34 * Note that this is not needed in case the clocks are stable
35 * throughout the entire runtime of the codec.
36 */
37 bool enable_soft_reset;
23}; 38};
24 39
25#endif /* __CS4271_H */ 40#endif /* __CS4271_H */