Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:
 "This pull brings:
   - Andy's DW driver updates
   - Guennadi's sh driver updates
   - Pl08x driver fixes from Tomasz & Alban
   - Improvements to mmp_pdma by Daniel
   - TI EDMA fixes by Joel
   - New drivers:
     - Hisilicon k3dma driver
     - Renesas rcar dma driver
  - New API for publishing slave driver capablities
  - Various fixes across the subsystem by Andy, Jingoo, Sachin etc..."

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (94 commits)
  dma: edma: Remove limits on number of slots
  dma: edma: Leave linked to Null slot instead of DUMMY slot
  dma: edma: Find missed events and issue them
  ARM: edma: Add function to manually trigger an EDMA channel
  dma: edma: Write out and handle MAX_NR_SG at a given time
  dma: edma: Setup parameters to DMA MAX_NR_SG at a time
  dmaengine: pl330: use dma_set_max_seg_size to set the sg limit
  dmaengine: dma_slave_caps: remove sg entries
  dma: replace devm_request_and_ioremap by devm_ioremap_resource
  dma: ste_dma40: Fix potential null pointer dereference
  dma: ste_dma40: Remove duplicate const
  dma: imx-dma: Remove redundant NULL check
  dma: dmagengine: fix function names in comments
  dma: add driver for R-Car HPB-DMAC
  dma: k3dma: use devm_ioremap_resource() instead of devm_request_and_ioremap()
  dma: imx-sdma: Staticize sdma_driver_data structures
  pch_dma: Add MODULE_DEVICE_TABLE
  dmaengine: PL08x: Add cyclic transfer support
  dmaengine: PL08x: Fix reading the byte count in cctl
  dmaengine: PL08x: Add support for different maximum transfer size
  ...

8 files changed, 192 insertions, 44 deletions

diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 3e7b62fbefbd..91b84a7f0539 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -87,6 +87,7 @@
 #define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
 #define PL080_CONTROL_SB_SIZE_SHIFT             (12)
 #define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
+#define PL080S_CONTROL_TRANSFER_SIZE_MASK       (0x1ffffff << 0)
 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
 
 #define PL080_BSIZE_1                           (0x0)
diff --git a/include/linux/dma/mmp-pdma.h b/include/linux/dma/mmp-pdma.h
new file mode 100644
index 000000000000..2dc9b2bc18fc
--- /dev/null
+++ b/include/linux/dma/mmp-pdma.h
@@ -0,0 +1,15 @@
+#ifndef _MMP_PDMA_H_
+#define _MMP_PDMA_H_
+
+struct dma_chan;
+
+#ifdef CONFIG_MMP_PDMA
+bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param);
+#else
+static inline bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param)
+{
+        return false;
+}
+#endif
+
+#endif /* _MMP_PDMA_H_ */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 0c72b89a172c..0bc727534108 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -373,6 +373,25 @@ struct dma_slave_config {
         unsigned int slave_id;
 };
 
+/* struct dma_slave_caps - expose capabilities of a slave channel only
+ *
+ * @src_addr_widths: bit mask of src addr widths the channel supports
+ * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
+ * @directions: bit mask of slave direction the channel supported
+ *      since the enum dma_transfer_direction is not defined as bits for each
+ *      type of direction, the dma controller should fill (1 << <TYPE>) and same
+ *      should be checked by controller as well
+ * @cmd_pause: true, if pause and thereby resume is supported
+ * @cmd_terminate: true, if terminate cmd is supported
+ */
+struct dma_slave_caps {
+        u32 src_addr_widths;
+        u32 dstn_addr_widths;
+        u32 directions;
+        bool cmd_pause;
+        bool cmd_terminate;
+};
+
 static inline const char *dma_chan_name(struct dma_chan *chan)
 {
         return dev_name(&chan->dev->device);
@@ -535,6 +554,7 @@ struct dma_tx_state {
  *      struct with auxiliary transfer status information, otherwise the call
  *      will just return a simple status code
  * @device_issue_pending: push pending transactions to hardware
+ * @device_slave_caps: return the slave channel capabilities
  */
 struct dma_device {
 
@@ -600,6 +620,7 @@ struct dma_device {
                                             dma_cookie_t cookie,
                                             struct dma_tx_state *txstate);
         void (*device_issue_pending)(struct dma_chan *chan);
+        int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
 };
 
 static inline int dmaengine_device_control(struct dma_chan *chan,
@@ -673,6 +694,21 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
 }
 
+static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
+{
+        if (!chan || !caps)
+                return -EINVAL;
+
+        /* check if the channel supports slave transactions */
+        if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
+                return -ENXIO;
+
+        if (chan->device->device_slave_caps)
+                return chan->device->device_slave_caps(chan, caps);
+
+        return -ENXIO;
+}
+
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
         return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
@@ -1006,6 +1042,7 @@ static inline void dma_release_channel(struct dma_chan *chan)
 int dma_async_device_register(struct dma_device *device);
 void dma_async_device_unregister(struct dma_device *device);
 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
 struct dma_chan *net_dma_find_channel(void);
 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
diff --git a/include/linux/fsl/mxs-dma.h b/include/linux/fsl/mxs-dma.h
deleted file mode 100644
index 55d870238399..000000000000
--- a/include/linux/fsl/mxs-dma.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_DMA_H__
-#define __MACH_MXS_DMA_H__
-
-#include <linux/dmaengine.h>
-
-struct mxs_dma_data {
-        int chan_irq;
-};
-
-extern int mxs_dma_is_apbh(struct dma_chan *chan);
-extern int mxs_dma_is_apbx(struct dma_chan *chan);
-#endif /* __MACH_MXS_DMA_H__ */
diff --git a/include/linux/platform_data/dma-rcar-hpbdma.h b/include/linux/platform_data/dma-rcar-hpbdma.h
new file mode 100644
index 000000000000..648b8ea61a22
--- /dev/null
+++ b/include/linux/platform_data/dma-rcar-hpbdma.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011-2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __DMA_RCAR_HPBDMA_H
+#define __DMA_RCAR_HPBDMA_H
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+/* Transmit sizes and respective register values */
+enum {
+        XMIT_SZ_8BIT    = 0,
+        XMIT_SZ_16BIT   = 1,
+        XMIT_SZ_32BIT   = 2,
+        XMIT_SZ_MAX
+};
+
+/* DMA control register (DCR) bits */
+#define HPB_DMAE_DCR_DTAMD              (1u << 26)
+#define HPB_DMAE_DCR_DTAC               (1u << 25)
+#define HPB_DMAE_DCR_DTAU               (1u << 24)
+#define HPB_DMAE_DCR_DTAU1              (1u << 23)
+#define HPB_DMAE_DCR_SWMD               (1u << 22)
+#define HPB_DMAE_DCR_BTMD               (1u << 21)
+#define HPB_DMAE_DCR_PKMD               (1u << 20)
+#define HPB_DMAE_DCR_CT                 (1u << 18)
+#define HPB_DMAE_DCR_ACMD               (1u << 17)
+#define HPB_DMAE_DCR_DIP                (1u << 16)
+#define HPB_DMAE_DCR_SMDL               (1u << 13)
+#define HPB_DMAE_DCR_SPDAM              (1u << 12)
+#define HPB_DMAE_DCR_SDRMD_MASK         (3u << 10)
+#define HPB_DMAE_DCR_SDRMD_MOD          (0u << 10)
+#define HPB_DMAE_DCR_SDRMD_AUTO         (1u << 10)
+#define HPB_DMAE_DCR_SDRMD_TIMER        (2u << 10)
+#define HPB_DMAE_DCR_SPDS_MASK          (3u << 8)
+#define HPB_DMAE_DCR_SPDS_8BIT          (0u << 8)
+#define HPB_DMAE_DCR_SPDS_16BIT         (1u << 8)
+#define HPB_DMAE_DCR_SPDS_32BIT         (2u << 8)
+#define HPB_DMAE_DCR_DMDL               (1u << 5)
+#define HPB_DMAE_DCR_DPDAM              (1u << 4)
+#define HPB_DMAE_DCR_DDRMD_MASK         (3u << 2)
+#define HPB_DMAE_DCR_DDRMD_MOD          (0u << 2)
+#define HPB_DMAE_DCR_DDRMD_AUTO         (1u << 2)
+#define HPB_DMAE_DCR_DDRMD_TIMER        (2u << 2)
+#define HPB_DMAE_DCR_DPDS_MASK          (3u << 0)
+#define HPB_DMAE_DCR_DPDS_8BIT          (0u << 0)
+#define HPB_DMAE_DCR_DPDS_16BIT         (1u << 0)
+#define HPB_DMAE_DCR_DPDS_32BIT         (2u << 0)
+
+/* Asynchronous reset register (ASYNCRSTR) bits */
+#define HPB_DMAE_ASYNCRSTR_ASRST41      BIT(10)
+#define HPB_DMAE_ASYNCRSTR_ASRST40      BIT(9)
+#define HPB_DMAE_ASYNCRSTR_ASRST39      BIT(8)
+#define HPB_DMAE_ASYNCRSTR_ASRST27      BIT(7)
+#define HPB_DMAE_ASYNCRSTR_ASRST26      BIT(6)
+#define HPB_DMAE_ASYNCRSTR_ASRST25      BIT(5)
+#define HPB_DMAE_ASYNCRSTR_ASRST24      BIT(4)
+#define HPB_DMAE_ASYNCRSTR_ASRST23      BIT(3)
+#define HPB_DMAE_ASYNCRSTR_ASRST22      BIT(2)
+#define HPB_DMAE_ASYNCRSTR_ASRST21      BIT(1)
+#define HPB_DMAE_ASYNCRSTR_ASRST20      BIT(0)
+
+struct hpb_dmae_slave_config {
+        unsigned int    id;
+        dma_addr_t      addr;
+        u32             dcr;
+        u32             port;
+        u32             rstr;
+        u32             mdr;
+        u32             mdm;
+        u32             flags;
+#define HPB_DMAE_SET_ASYNC_RESET        BIT(0)
+#define HPB_DMAE_SET_ASYNC_MODE         BIT(1)
+        u32             dma_ch;
+};
+
+#define HPB_DMAE_CHANNEL(_irq, _s_id)   \
+{                                       \
+        .ch_irq         = _irq,         \
+        .s_id           = _s_id,        \
+}
+
+struct hpb_dmae_channel {
+        unsigned int    ch_irq;
+        unsigned int    s_id;
+};
+
+struct hpb_dmae_pdata {
+        const struct hpb_dmae_slave_config *slaves;
+        int num_slaves;
+        const struct hpb_dmae_channel *channels;
+        int num_channels;
+        const unsigned int ts_shift[XMIT_SZ_MAX];
+        int num_hw_channels;
+};
+
+#endif
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 57300fd7cc03..179fb91bb5f2 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -180,4 +180,6 @@ struct edma_soc_info {
         const s16       (*xbar_chans)[2];
 };
 
+int edma_trigger_channel(unsigned);
+
 #endif
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index 4e83f3e034f3..b7b43b82231e 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -33,13 +33,44 @@ struct sh_dmae_slave_config {
         char            mid_rid;
 };
 
+/**
+ * struct sh_dmae_channel - DMAC channel platform data
+ * @offset:             register offset within the main IOMEM resource
+ * @dmars:              channel DMARS register offset
+ * @chclr_offset:       channel CHCLR register offset
+ * @dmars_bit:          channel DMARS field offset within the register
+ * @chclr_bit:          bit position, to be set to reset the channel
+ */
 struct sh_dmae_channel {
         unsigned int    offset;
         unsigned int    dmars;
-        unsigned int    dmars_bit;
         unsigned int    chclr_offset;
+        unsigned char   dmars_bit;
+        unsigned char   chclr_bit;
 };
 
+/**
+ * struct sh_dmae_pdata - DMAC platform data
+ * @slave:              array of slaves
+ * @slave_num:          number of slaves in the above array
+ * @channel:            array of DMA channels
+ * @channel_num:        number of channels in the above array
+ * @ts_low_shift:       shift of the low part of the TS field
+ * @ts_low_mask:        low TS field mask
+ * @ts_high_shift:      additional shift of the high part of the TS field
+ * @ts_high_mask:       high TS field mask
+ * @ts_shift:           array of Transfer Size shifts, indexed by TS value
+ * @ts_shift_num:       number of shifts in the above array
+ * @dmaor_init:         DMAOR initialisation value
+ * @chcr_offset:        CHCR address offset
+ * @chcr_ie_bit:        CHCR Interrupt Enable bit
+ * @dmaor_is_32bit:     DMAOR is a 32-bit register
+ * @needs_tend_set:     the TEND register has to be set
+ * @no_dmars:           DMAC has no DMARS registers
+ * @chclr_present:      DMAC has one or several CHCLR registers
+ * @chclr_bitwise:      channel CHCLR registers are bitwise
+ * @slave_only:         DMAC cannot be used for MEMCPY
+ */
 struct sh_dmae_pdata {
         const struct sh_dmae_slave_config *slave;
         int slave_num;
@@ -59,42 +90,22 @@ struct sh_dmae_pdata {
         unsigned int needs_tend_set:1;
         unsigned int no_dmars:1;
         unsigned int chclr_present:1;
+        unsigned int chclr_bitwise:1;
         unsigned int slave_only:1;
 };
 
-/* DMA register */
-#define SAR     0x00
-#define DAR     0x04
-#define TCR     0x08
-#define CHCR    0x0C
-#define DMAOR   0x40
-
-#define TEND    0x18 /* USB-DMAC */
-
 /* DMAOR definitions */
 #define DMAOR_AE        0x00000004
 #define DMAOR_NMIF      0x00000002
 #define DMAOR_DME       0x00000001
 
 /* Definitions for the SuperH DMAC */
-#define REQ_L   0x00000000
-#define REQ_E   0x00080000
-#define RACK_H  0x00000000
-#define RACK_L  0x00040000
-#define ACK_R   0x00000000
-#define ACK_W   0x00020000
-#define ACK_H   0x00000000
-#define ACK_L   0x00010000
 #define DM_INC  0x00004000
 #define DM_DEC  0x00008000
 #define DM_FIX  0x0000c000
 #define SM_INC  0x00001000
 #define SM_DEC  0x00002000
 #define SM_FIX  0x00003000
-#define RS_IN   0x00000200
-#define RS_OUT  0x00000300
-#define TS_BLK  0x00000040
-#define TM_BUR  0x00000020
 #define CHCR_DE 0x00000001
 #define CHCR_TE 0x00000002
 #define CHCR_IE 0x00000004
diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h
index 5b1c9848124c..f92c0a43c54c 100644
--- a/include/linux/shdma-base.h
+++ b/include/linux/shdma-base.h
@@ -96,7 +96,7 @@ struct shdma_ops {
         dma_addr_t (*slave_addr)(struct shdma_chan *);
         int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
                           dma_addr_t, dma_addr_t, size_t *);
-        int (*set_slave)(struct shdma_chan *, int, bool);
+        int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
         void (*setup_xfer)(struct shdma_chan *, int);
         void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
         struct shdma_desc *(*embedded_desc)(void *, int);
@@ -116,7 +116,6 @@ struct shdma_dev {
 
 int shdma_request_irq(struct shdma_chan *, int,
                            unsigned long, const char *);
-void shdma_free_irq(struct shdma_chan *);
 bool shdma_reset(struct shdma_dev *sdev);
 void shdma_chan_probe(struct shdma_dev *sdev,
                            struct shdma_chan *schan, int id);