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authorJack Morgenstein <jackm@dev.mellanox.co.il>2008-01-28 03:40:59 -0500
committerRoland Dreier <rolandd@cisco.com>2008-02-08 16:30:02 -0500
commitea54b10c7773007e173da31fe7adcc049da33331 (patch)
treeb13b77fb3807071a5b93ece7b564f6748d962bbc /include/linux
parentb57aacfa7a95328f469d0360e49289b023c47e9e (diff)
IB/mlx4: Use multiple WQ blocks to post smaller send WQEs
ConnectX HCA supports shrinking WQEs, so that a single work request can be made of multiple units of wqe_shift. This way, WRs can differ in size, and do not have to be a power of 2 in size, saving memory and speeding up send WR posting. Unfortunately, if we do this then the wqe_index field in CQEs can't be used to look up the WR ID anymore, so our implementation does this only if selective signaling is off. Further, on 32-bit platforms, we can't use vmap() to make the QP buffer virtually contigious. Thus we have to use constant-sized WRs to make sure a WR is always fully within a single page-sized chunk. Finally, we use WRs with the NOP opcode to avoid wrapping around the queue buffer in the middle of posting a WR, and we set the NoErrorCompletion bit to avoid getting completions with error for NOP WRs. However, NEC is only supported starting with firmware 2.2.232, so we use constant-sized WRs for older firmware. And, since MLX QPs only support SEND, we use constant-sized WRs in this case. When stamping during NOP posting, do stamping following setting of the NOP WQE valid bit. Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx4/device.h5
-rw-r--r--include/linux/mlx4/qp.h4
2 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 4210ac4a8bcd..6cdf813cd478 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -133,6 +133,11 @@ enum {
133 MLX4_STAT_RATE_OFFSET = 5 133 MLX4_STAT_RATE_OFFSET = 5
134}; 134};
135 135
136static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
137{
138 return (major << 32) | (minor << 16) | subminor;
139}
140
136struct mlx4_caps { 141struct mlx4_caps {
137 u64 fw_ver; 142 u64 fw_ver;
138 int num_ports; 143 int num_ports;
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 3968b943259a..09a2230923f2 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -154,7 +154,11 @@ struct mlx4_qp_context {
154 u32 reserved5[10]; 154 u32 reserved5[10];
155}; 155};
156 156
157/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
159
157enum { 160enum {
161 MLX4_WQE_CTRL_NEC = 1 << 29,
158 MLX4_WQE_CTRL_FENCE = 1 << 6, 162 MLX4_WQE_CTRL_FENCE = 1 << 6,
159 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
160 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 164 MLX4_WQE_CTRL_SOLICITED = 1 << 1,