Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (48 commits)
  LIB82596: correct data types for hardware addresses
  via-velocity: don't oops on MTU change (resend)
  Stop phy code from returning success to unknown ioctls.
  SET_NETDEV_DEV() in fec_mpc52xx.c
  net: smc911x: only enable for mpr2 on sh.
  e1000: Fix NAPI state bug when Rx complete
  sky2: turn of dynamic Tx watermark workaround (FE+ only)
  sky2: don't use AER routines
  sky2: revert to access PCI config via device space
  cxgb - fix stats
  cxgb - fix NAPI
  cxgb - fix T2 GSO
  ucc_geth: handle passing of RX-only and TX-only internal delay PHY connection type parameters
  phylib: marvell: add support for TX-only and RX-only Internal Delay
  phylib: add PHY interface modes for internal delay for tx and rx only
  skge: MTU changing fix
  skge: serial mode register values
  skge version 1.13
  skge: increase TX threshold for Jumbo
  skge: fiber link up/down fix
  ...

2 files changed, 6 insertions, 0 deletions

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1ee009e8fec8..111aa10f1136 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1237,6 +1237,10 @@
 #define PCI_DEVICE_ID_NVIDIA_NVENET_33              0x0761
 #define PCI_DEVICE_ID_NVIDIA_NVENET_34              0x0762
 #define PCI_DEVICE_ID_NVIDIA_NVENET_35              0x0763
+#define PCI_DEVICE_ID_NVIDIA_NVENET_36              0x0AB0
+#define PCI_DEVICE_ID_NVIDIA_NVENET_37              0x0AB1
+#define PCI_DEVICE_ID_NVIDIA_NVENET_38              0x0AB2
+#define PCI_DEVICE_ID_NVIDIA_NVENET_39              0x0AB3
 
 #define PCI_VENDOR_ID_IMS               0x10e0
 #define PCI_DEVICE_ID_IMS_TT128         0x9128
diff --git a/include/linux/phy.h b/include/linux/phy.h
index f0742b6aaa64..e10763d79181 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -58,6 +58,8 @@ typedef enum {
         PHY_INTERFACE_MODE_RMII,
         PHY_INTERFACE_MODE_RGMII,
         PHY_INTERFACE_MODE_RGMII_ID,
+        PHY_INTERFACE_MODE_RGMII_RXID,
+        PHY_INTERFACE_MODE_RGMII_TXID,
         PHY_INTERFACE_MODE_RTBI
 } phy_interface_t;