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authorLennert Buytenhek <buytenh@wantstofly.org>2007-10-18 22:10:10 -0400
committerDale Farnsworth <dale@farnsworth.org>2007-10-23 11:23:00 -0400
commite2734d6c61e0fd2b0f3aeac01e8dcd36c99b1a13 (patch)
treebcd8fcc0667a1846d19756d90d1ce5618af5d4e7 /include/linux
parentc4a6a2ab5e99980b10d1eef761cd95f2a19ba46d (diff)
mv643xx_eth: Move ethernet register definitions into private header
Move the mv643xx's ethernet-related register definitions from include/linux/mv643xx.h into drivers/net/mv643xx_eth.h, since they aren't of any use outside the ethernet driver. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Tzachi Perelstein <tzachi@marvell.com> Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mv643xx.h302
1 files changed, 0 insertions, 302 deletions
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index e67d7eceb660..d2ae6185f03b 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -659,117 +659,6 @@
659/* Ethernet Unit Registers */ 659/* Ethernet Unit Registers */
660/****************************************/ 660/****************************************/
661 661
662#define MV643XX_ETH_PHY_ADDR_REG 0x2000
663#define MV643XX_ETH_SMI_REG 0x2004
664#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
665#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
666#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
667#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
668#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
669#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
670#define MV643XX_ETH_BAR_0 0x2200
671#define MV643XX_ETH_BAR_1 0x2208
672#define MV643XX_ETH_BAR_2 0x2210
673#define MV643XX_ETH_BAR_3 0x2218
674#define MV643XX_ETH_BAR_4 0x2220
675#define MV643XX_ETH_BAR_5 0x2228
676#define MV643XX_ETH_SIZE_REG_0 0x2204
677#define MV643XX_ETH_SIZE_REG_1 0x220c
678#define MV643XX_ETH_SIZE_REG_2 0x2214
679#define MV643XX_ETH_SIZE_REG_3 0x221c
680#define MV643XX_ETH_SIZE_REG_4 0x2224
681#define MV643XX_ETH_SIZE_REG_5 0x222c
682#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
683#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
684#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
685#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
686#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
687#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
688#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
689#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
690#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
691#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
692#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
693#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
694#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
695#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
696#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
697#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
698#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
699#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
700#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
701#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
702#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
703#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
704#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
705#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
706#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
707#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
708#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
709#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
710#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
711#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
712#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
713#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
714#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
715#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
716#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
717#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
718#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
719#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
720#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
721#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
722#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
723#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
724#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
725#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
726#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
727#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
728#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
729#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
730#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
731#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
732#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
733#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
734#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
735#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
736#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
737#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
738#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
739#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
740#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
741#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
742#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
743#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
744#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
745#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
746#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
747#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
748#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
749#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
750#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
751#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
752#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
753#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
754#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
755#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
756#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
757#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
758#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
759#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
760#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
761#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
762#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
763#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
764#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
765#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
766#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
767#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
768#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
769#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
770#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
771#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
772
773/*******************************************/ 662/*******************************************/
774/* CUNIT Registers */ 663/* CUNIT Registers */
775/*******************************************/ 664/*******************************************/
@@ -1087,197 +976,6 @@ struct mv64xxx_i2c_pdata {
1087 u32 retries; 976 u32 retries;
1088}; 977};
1089 978
1090/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
1091#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
1092#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
1093#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
1094#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
1095#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
1096#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
1097#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
1098#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
1099#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
1100#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
1101#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
1102#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
1103#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
1104#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
1105#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
1106#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
1107#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
1108#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
1109#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
1110#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
1111#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
1112#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
1113#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
1114#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
1115#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
1116#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
1117#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
1118#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
1119#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
1120#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
1121#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
1122#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
1123#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
1124#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
1125#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
1126#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
1127#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
1128#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
1129#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
1130#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
1131#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
1132#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
1133#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
1134#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
1135#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
1136#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
1137#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
1138#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
1139#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
1140#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
1141#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
1142#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
1143#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
1144
1145#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
1146 MV643XX_ETH_UNICAST_NORMAL_MODE | \
1147 MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
1148 MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
1149 MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
1150 MV643XX_ETH_RECEIVE_BC_IF_IP | \
1151 MV643XX_ETH_RECEIVE_BC_IF_ARP | \
1152 MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
1153 MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
1154 MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
1155 MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
1156 MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
1157
1158/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
1159#define MV643XX_ETH_CLASSIFY_EN (1<<0)
1160#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
1161#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
1162#define MV643XX_ETH_PARTITION_DISABLE 0
1163#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
1164
1165#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
1166 MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
1167 MV643XX_ETH_PARTITION_DISABLE
1168
1169/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
1170#define MV643XX_ETH_RIFB (1<<0)
1171#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
1172#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
1173#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
1174#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
1175#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
1176#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
1177#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
1178#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
1179#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
1180#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
1181#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
1182#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
1183#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
1184#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
1185#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
1186#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
1187
1188#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
1189
1190#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
1191 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
1192 MV643XX_ETH_IPG_INT_RX(0) | \
1193 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
1194
1195/* These macros describe Ethernet Port serial control reg (PSCR) bits */
1196#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
1197#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
1198#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
1199#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
1200#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
1201#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
1202#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
1203#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
1204#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
1205#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
1206#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
1207#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
1208#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
1209#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
1210#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
1211#define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
1212#define MV643XX_ETH_FORCE_LINK_FAIL 0
1213#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
1214#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
1215#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
1216#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
1217#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
1218#define MV643XX_ETH_DTE_ADV_0 0
1219#define MV643XX_ETH_DTE_ADV_1 (1<<14)
1220#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
1221#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
1222#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
1223#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
1224#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
1225#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
1226#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
1227#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
1228#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
1229#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
1230#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
1231#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
1232#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
1233#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
1234#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
1235#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
1236#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
1237#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
1238#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
1239#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
1240
1241#define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
1242
1243#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
1244 MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
1245 MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
1246 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
1247 MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
1248 MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
1249 MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
1250 (1<<9) /* reserved */ | \
1251 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
1252 MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
1253 MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
1254 MV643XX_ETH_DTE_ADV_0 | \
1255 MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
1256 MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
1257 MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
1258 MV643XX_ETH_CLR_EXT_LOOPBACK | \
1259 MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
1260 MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
1261
1262/* These macros describe Ethernet Serial Status reg (PSR) bits */
1263#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
1264#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
1265#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
1266#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
1267#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
1268#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
1269/* PSR bit 6 is undocumented */
1270#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
1271#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
1272#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
1273#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
1274/* PSR bits 11-31 are reserved */
1275
1276#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
1277#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
1278
1279#define MV643XX_ETH_DESC_SIZE 64
1280
1281/* Watchdog Platform Device, Driver Data */ 979/* Watchdog Platform Device, Driver Data */
1282#define MV64x60_WDT_NAME "mv64x60_wdt" 980#define MV64x60_WDT_NAME "mv64x60_wdt"
1283 981
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