Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem

Conflicts:
	drivers/net/wireless/iwlwifi/iwl-agn-tx.c
	net/mac80211/sta_info.h

8 files changed, 976 insertions, 4 deletions

diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
new file mode 100644
index 000000000000..08763e4e848f
--- /dev/null
+++ b/include/linux/bcma/bcma.h
@@ -0,0 +1,224 @@
+#ifndef LINUX_BCMA_H_
+#define LINUX_BCMA_H_
+
+#include <linux/pci.h>
+#include <linux/mod_devicetable.h>
+
+#include <linux/bcma/bcma_driver_chipcommon.h>
+#include <linux/bcma/bcma_driver_pci.h>
+
+#include "bcma_regs.h"
+
+struct bcma_device;
+struct bcma_bus;
+
+enum bcma_hosttype {
+        BCMA_HOSTTYPE_NONE,
+        BCMA_HOSTTYPE_PCI,
+        BCMA_HOSTTYPE_SDIO,
+};
+
+struct bcma_chipinfo {
+        u16 id;
+        u8 rev;
+        u8 pkg;
+};
+
+struct bcma_host_ops {
+        u8 (*read8)(struct bcma_device *core, u16 offset);
+        u16 (*read16)(struct bcma_device *core, u16 offset);
+        u32 (*read32)(struct bcma_device *core, u16 offset);
+        void (*write8)(struct bcma_device *core, u16 offset, u8 value);
+        void (*write16)(struct bcma_device *core, u16 offset, u16 value);
+        void (*write32)(struct bcma_device *core, u16 offset, u32 value);
+        /* Agent ops */
+        u32 (*aread32)(struct bcma_device *core, u16 offset);
+        void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
+};
+
+/* Core manufacturers */
+#define BCMA_MANUF_ARM                  0x43B
+#define BCMA_MANUF_MIPS                 0x4A7
+#define BCMA_MANUF_BCM                  0x4BF
+
+/* Core class values. */
+#define BCMA_CL_SIM                     0x0
+#define BCMA_CL_EROM                    0x1
+#define BCMA_CL_CORESIGHT               0x9
+#define BCMA_CL_VERIF                   0xB
+#define BCMA_CL_OPTIMO                  0xD
+#define BCMA_CL_GEN                     0xE
+#define BCMA_CL_PRIMECELL               0xF
+
+/* Core-ID values. */
+#define BCMA_CORE_OOB_ROUTER            0x367   /* Out of band */
+#define BCMA_CORE_INVALID               0x700
+#define BCMA_CORE_CHIPCOMMON            0x800
+#define BCMA_CORE_ILINE20               0x801
+#define BCMA_CORE_SRAM                  0x802
+#define BCMA_CORE_SDRAM                 0x803
+#define BCMA_CORE_PCI                   0x804
+#define BCMA_CORE_MIPS                  0x805
+#define BCMA_CORE_ETHERNET              0x806
+#define BCMA_CORE_V90                   0x807
+#define BCMA_CORE_USB11_HOSTDEV         0x808
+#define BCMA_CORE_ADSL                  0x809
+#define BCMA_CORE_ILINE100              0x80A
+#define BCMA_CORE_IPSEC                 0x80B
+#define BCMA_CORE_UTOPIA                0x80C
+#define BCMA_CORE_PCMCIA                0x80D
+#define BCMA_CORE_INTERNAL_MEM          0x80E
+#define BCMA_CORE_MEMC_SDRAM            0x80F
+#define BCMA_CORE_OFDM                  0x810
+#define BCMA_CORE_EXTIF                 0x811
+#define BCMA_CORE_80211                 0x812
+#define BCMA_CORE_PHY_A                 0x813
+#define BCMA_CORE_PHY_B                 0x814
+#define BCMA_CORE_PHY_G                 0x815
+#define BCMA_CORE_MIPS_3302             0x816
+#define BCMA_CORE_USB11_HOST            0x817
+#define BCMA_CORE_USB11_DEV             0x818
+#define BCMA_CORE_USB20_HOST            0x819
+#define BCMA_CORE_USB20_DEV             0x81A
+#define BCMA_CORE_SDIO_HOST             0x81B
+#define BCMA_CORE_ROBOSWITCH            0x81C
+#define BCMA_CORE_PARA_ATA              0x81D
+#define BCMA_CORE_SATA_XORDMA           0x81E
+#define BCMA_CORE_ETHERNET_GBIT         0x81F
+#define BCMA_CORE_PCIE                  0x820
+#define BCMA_CORE_PHY_N                 0x821
+#define BCMA_CORE_SRAM_CTL              0x822
+#define BCMA_CORE_MINI_MACPHY           0x823
+#define BCMA_CORE_ARM_1176              0x824
+#define BCMA_CORE_ARM_7TDMI             0x825
+#define BCMA_CORE_PHY_LP                0x826
+#define BCMA_CORE_PMU                   0x827
+#define BCMA_CORE_PHY_SSN               0x828
+#define BCMA_CORE_SDIO_DEV              0x829
+#define BCMA_CORE_ARM_CM3               0x82A
+#define BCMA_CORE_PHY_HT                0x82B
+#define BCMA_CORE_MIPS_74K              0x82C
+#define BCMA_CORE_MAC_GBIT              0x82D
+#define BCMA_CORE_DDR12_MEM_CTL         0x82E
+#define BCMA_CORE_PCIE_RC               0x82F   /* PCIe Root Complex */
+#define BCMA_CORE_OCP_OCP_BRIDGE        0x830
+#define BCMA_CORE_SHARED_COMMON         0x831
+#define BCMA_CORE_OCP_AHB_BRIDGE        0x832
+#define BCMA_CORE_SPI_HOST              0x833
+#define BCMA_CORE_I2S                   0x834
+#define BCMA_CORE_SDR_DDR1_MEM_CTL      0x835   /* SDR/DDR1 memory controller core */
+#define BCMA_CORE_SHIM                  0x837   /* SHIM component in ubus/6362 */
+#define BCMA_CORE_DEFAULT               0xFFF
+
+#define BCMA_MAX_NR_CORES               16
+
+struct bcma_device {
+        struct bcma_bus *bus;
+        struct bcma_device_id id;
+
+        struct device dev;
+        bool dev_registered;
+
+        u8 core_index;
+
+        u32 addr;
+        u32 wrap;
+
+        void *drvdata;
+        struct list_head list;
+};
+
+static inline void *bcma_get_drvdata(struct bcma_device *core)
+{
+        return core->drvdata;
+}
+static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
+{
+        core->drvdata = drvdata;
+}
+
+struct bcma_driver {
+        const char *name;
+        const struct bcma_device_id *id_table;
+
+        int (*probe)(struct bcma_device *dev);
+        void (*remove)(struct bcma_device *dev);
+        int (*suspend)(struct bcma_device *dev, pm_message_t state);
+        int (*resume)(struct bcma_device *dev);
+        void (*shutdown)(struct bcma_device *dev);
+
+        struct device_driver drv;
+};
+extern
+int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
+static inline int bcma_driver_register(struct bcma_driver *drv)
+{
+        return __bcma_driver_register(drv, THIS_MODULE);
+}
+extern void bcma_driver_unregister(struct bcma_driver *drv);
+
+struct bcma_bus {
+        /* The MMIO area. */
+        void __iomem *mmio;
+
+        const struct bcma_host_ops *ops;
+
+        enum bcma_hosttype hosttype;
+        union {
+                /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
+                struct pci_dev *host_pci;
+                /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
+                struct sdio_func *host_sdio;
+        };
+
+        struct bcma_chipinfo chipinfo;
+
+        struct bcma_device *mapped_core;
+        struct list_head cores;
+        u8 nr_cores;
+
+        struct bcma_drv_cc drv_cc;
+        struct bcma_drv_pci drv_pci;
+};
+
+extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
+{
+        return core->bus->ops->read8(core, offset);
+}
+extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
+{
+        return core->bus->ops->read16(core, offset);
+}
+extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
+{
+        return core->bus->ops->read32(core, offset);
+}
+extern inline
+void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
+{
+        core->bus->ops->write8(core, offset, value);
+}
+extern inline
+void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
+{
+        core->bus->ops->write16(core, offset, value);
+}
+extern inline
+void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
+{
+        core->bus->ops->write32(core, offset, value);
+}
+extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
+{
+        return core->bus->ops->aread32(core, offset);
+}
+extern inline
+void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
+{
+        core->bus->ops->awrite32(core, offset, value);
+}
+
+extern bool bcma_core_is_enabled(struct bcma_device *core);
+extern int bcma_core_enable(struct bcma_device *core, u32 flags);
+
+#endif /* LINUX_BCMA_H_ */
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
new file mode 100644
index 000000000000..083c3b6cd5ce
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -0,0 +1,302 @@
+#ifndef LINUX_BCMA_DRIVER_CC_H_
+#define LINUX_BCMA_DRIVER_CC_H_
+
+/** ChipCommon core registers. **/
+#define BCMA_CC_ID                      0x0000
+#define  BCMA_CC_ID_ID                  0x0000FFFF
+#define  BCMA_CC_ID_ID_SHIFT            0
+#define  BCMA_CC_ID_REV                 0x000F0000
+#define  BCMA_CC_ID_REV_SHIFT           16
+#define  BCMA_CC_ID_PKG                 0x00F00000
+#define  BCMA_CC_ID_PKG_SHIFT           20
+#define  BCMA_CC_ID_NRCORES             0x0F000000
+#define  BCMA_CC_ID_NRCORES_SHIFT       24
+#define  BCMA_CC_ID_TYPE                0xF0000000
+#define  BCMA_CC_ID_TYPE_SHIFT          28
+#define BCMA_CC_CAP                     0x0004          /* Capabilities */
+#define  BCMA_CC_CAP_NRUART             0x00000003      /* # of UARTs */
+#define  BCMA_CC_CAP_MIPSEB             0x00000004      /* MIPS in BigEndian Mode */
+#define  BCMA_CC_CAP_UARTCLK            0x00000018      /* UART clock select */
+#define   BCMA_CC_CAP_UARTCLK_INT       0x00000008      /* UARTs are driven by internal divided clock */
+#define  BCMA_CC_CAP_UARTGPIO           0x00000020      /* UARTs on GPIO 15-12 */
+#define  BCMA_CC_CAP_EXTBUS             0x000000C0      /* External buses present */
+#define  BCMA_CC_CAP_FLASHT             0x00000700      /* Flash Type */
+#define   BCMA_CC_FLASHT_NONE           0x00000000      /* No flash */
+#define   BCMA_CC_FLASHT_STSER          0x00000100      /* ST serial flash */
+#define   BCMA_CC_FLASHT_ATSER          0x00000200      /* Atmel serial flash */
+#define   BCMA_CC_FLASHT_PARA           0x00000700      /* Parallel flash */
+#define  BCMA_CC_CAP_PLLT               0x00038000      /* PLL Type */
+#define   BCMA_PLLTYPE_NONE             0x00000000
+#define   BCMA_PLLTYPE_1                0x00010000      /* 48Mhz base, 3 dividers */
+#define   BCMA_PLLTYPE_2                0x00020000      /* 48Mhz, 4 dividers */
+#define   BCMA_PLLTYPE_3                0x00030000      /* 25Mhz, 2 dividers */
+#define   BCMA_PLLTYPE_4                0x00008000      /* 48Mhz, 4 dividers */
+#define   BCMA_PLLTYPE_5                0x00018000      /* 25Mhz, 4 dividers */
+#define   BCMA_PLLTYPE_6                0x00028000      /* 100/200 or 120/240 only */
+#define   BCMA_PLLTYPE_7                0x00038000      /* 25Mhz, 4 dividers */
+#define  BCMA_CC_CAP_PCTL               0x00040000      /* Power Control */
+#define  BCMA_CC_CAP_OTPS               0x00380000      /* OTP size */
+#define  BCMA_CC_CAP_OTPS_SHIFT         19
+#define  BCMA_CC_CAP_OTPS_BASE          5
+#define  BCMA_CC_CAP_JTAGM              0x00400000      /* JTAG master present */
+#define  BCMA_CC_CAP_BROM               0x00800000      /* Internal boot ROM active */
+#define  BCMA_CC_CAP_64BIT              0x08000000      /* 64-bit Backplane */
+#define  BCMA_CC_CAP_PMU                0x10000000      /* PMU available (rev >= 20) */
+#define  BCMA_CC_CAP_ECI                0x20000000      /* ECI available (rev >= 20) */
+#define  BCMA_CC_CAP_SPROM              0x40000000      /* SPROM present */
+#define BCMA_CC_CORECTL                 0x0008
+#define  BCMA_CC_CORECTL_UARTCLK0       0x00000001      /* Drive UART with internal clock */
+#define  BCMA_CC_CORECTL_SE             0x00000002      /* sync clk out enable (corerev >= 3) */
+#define  BCMA_CC_CORECTL_UARTCLKEN      0x00000008      /* UART clock enable (rev >= 21) */
+#define BCMA_CC_BIST                    0x000C
+#define BCMA_CC_OTPS                    0x0010          /* OTP status */
+#define  BCMA_CC_OTPS_PROGFAIL          0x80000000
+#define  BCMA_CC_OTPS_PROTECT           0x00000007
+#define  BCMA_CC_OTPS_HW_PROTECT        0x00000001
+#define  BCMA_CC_OTPS_SW_PROTECT        0x00000002
+#define  BCMA_CC_OTPS_CID_PROTECT       0x00000004
+#define BCMA_CC_OTPC                    0x0014          /* OTP control */
+#define  BCMA_CC_OTPC_RECWAIT           0xFF000000
+#define  BCMA_CC_OTPC_PROGWAIT          0x00FFFF00
+#define  BCMA_CC_OTPC_PRW_SHIFT         8
+#define  BCMA_CC_OTPC_MAXFAIL           0x00000038
+#define  BCMA_CC_OTPC_VSEL              0x00000006
+#define  BCMA_CC_OTPC_SELVL             0x00000001
+#define BCMA_CC_OTPP                    0x0018          /* OTP prog */
+#define  BCMA_CC_OTPP_COL               0x000000FF
+#define  BCMA_CC_OTPP_ROW               0x0000FF00
+#define  BCMA_CC_OTPP_ROW_SHIFT         8
+#define  BCMA_CC_OTPP_READERR           0x10000000
+#define  BCMA_CC_OTPP_VALUE             0x20000000
+#define  BCMA_CC_OTPP_READ              0x40000000
+#define  BCMA_CC_OTPP_START             0x80000000
+#define  BCMA_CC_OTPP_BUSY              0x80000000
+#define BCMA_CC_IRQSTAT                 0x0020
+#define BCMA_CC_IRQMASK                 0x0024
+#define  BCMA_CC_IRQ_GPIO               0x00000001      /* gpio intr */
+#define  BCMA_CC_IRQ_EXT                0x00000002      /* ro: ext intr pin (corerev >= 3) */
+#define  BCMA_CC_IRQ_WDRESET            0x80000000      /* watchdog reset occurred */
+#define BCMA_CC_CHIPCTL                 0x0028          /* Rev >= 11 only */
+#define BCMA_CC_CHIPSTAT                0x002C          /* Rev >= 11 only */
+#define BCMA_CC_JCMD                    0x0030          /* Rev >= 10 only */
+#define  BCMA_CC_JCMD_START             0x80000000
+#define  BCMA_CC_JCMD_BUSY              0x80000000
+#define  BCMA_CC_JCMD_PAUSE             0x40000000
+#define  BCMA_CC_JCMD0_ACC_MASK         0x0000F000
+#define  BCMA_CC_JCMD0_ACC_IRDR         0x00000000
+#define  BCMA_CC_JCMD0_ACC_DR           0x00001000
+#define  BCMA_CC_JCMD0_ACC_IR           0x00002000
+#define  BCMA_CC_JCMD0_ACC_RESET        0x00003000
+#define  BCMA_CC_JCMD0_ACC_IRPDR        0x00004000
+#define  BCMA_CC_JCMD0_ACC_PDR          0x00005000
+#define  BCMA_CC_JCMD0_IRW_MASK         0x00000F00
+#define  BCMA_CC_JCMD_ACC_MASK          0x000F0000      /* Changes for corerev 11 */
+#define  BCMA_CC_JCMD_ACC_IRDR          0x00000000
+#define  BCMA_CC_JCMD_ACC_DR            0x00010000
+#define  BCMA_CC_JCMD_ACC_IR            0x00020000
+#define  BCMA_CC_JCMD_ACC_RESET         0x00030000
+#define  BCMA_CC_JCMD_ACC_IRPDR         0x00040000
+#define  BCMA_CC_JCMD_ACC_PDR           0x00050000
+#define  BCMA_CC_JCMD_IRW_MASK          0x00001F00
+#define  BCMA_CC_JCMD_IRW_SHIFT         8
+#define  BCMA_CC_JCMD_DRW_MASK          0x0000003F
+#define BCMA_CC_JIR                     0x0034          /* Rev >= 10 only */
+#define BCMA_CC_JDR                     0x0038          /* Rev >= 10 only */
+#define BCMA_CC_JCTL                    0x003C          /* Rev >= 10 only */
+#define  BCMA_CC_JCTL_FORCE_CLK         4               /* Force clock */
+#define  BCMA_CC_JCTL_EXT_EN            2               /* Enable external targets */
+#define  BCMA_CC_JCTL_EN                1               /* Enable Jtag master */
+#define BCMA_CC_FLASHCTL                0x0040
+#define  BCMA_CC_FLASHCTL_START         0x80000000
+#define  BCMA_CC_FLASHCTL_BUSY          BCMA_CC_FLASHCTL_START
+#define BCMA_CC_FLASHADDR               0x0044
+#define BCMA_CC_FLASHDATA               0x0048
+#define BCMA_CC_BCAST_ADDR              0x0050
+#define BCMA_CC_BCAST_DATA              0x0054
+#define BCMA_CC_GPIOPULLUP              0x0058          /* Rev >= 20 only */
+#define BCMA_CC_GPIOPULLDOWN            0x005C          /* Rev >= 20 only */
+#define BCMA_CC_GPIOIN                  0x0060
+#define BCMA_CC_GPIOOUT                 0x0064
+#define BCMA_CC_GPIOOUTEN               0x0068
+#define BCMA_CC_GPIOCTL                 0x006C
+#define BCMA_CC_GPIOPOL                 0x0070
+#define BCMA_CC_GPIOIRQ                 0x0074
+#define BCMA_CC_WATCHDOG                0x0080
+#define BCMA_CC_GPIOTIMER               0x0088          /* LED powersave (corerev >= 16) */
+#define  BCMA_CC_GPIOTIMER_OFFTIME      0x0000FFFF
+#define  BCMA_CC_GPIOTIMER_OFFTIME_SHIFT        0
+#define  BCMA_CC_GPIOTIMER_ONTIME       0xFFFF0000
+#define  BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
+#define BCMA_CC_GPIOTOUTM               0x008C          /* LED powersave (corerev >= 16) */
+#define BCMA_CC_CLOCK_N                 0x0090
+#define BCMA_CC_CLOCK_SB                0x0094
+#define BCMA_CC_CLOCK_PCI               0x0098
+#define BCMA_CC_CLOCK_M2                0x009C
+#define BCMA_CC_CLOCK_MIPS              0x00A0
+#define BCMA_CC_CLKDIV                  0x00A4          /* Rev >= 3 only */
+#define  BCMA_CC_CLKDIV_SFLASH          0x0F000000
+#define  BCMA_CC_CLKDIV_SFLASH_SHIFT    24
+#define  BCMA_CC_CLKDIV_OTP             0x000F0000
+#define  BCMA_CC_CLKDIV_OTP_SHIFT       16
+#define  BCMA_CC_CLKDIV_JTAG            0x00000F00
+#define  BCMA_CC_CLKDIV_JTAG_SHIFT      8
+#define  BCMA_CC_CLKDIV_UART            0x000000FF
+#define BCMA_CC_CAP_EXT                 0x00AC          /* Capabilities */
+#define BCMA_CC_PLLONDELAY              0x00B0          /* Rev >= 4 only */
+#define BCMA_CC_FREFSELDELAY            0x00B4          /* Rev >= 4 only */
+#define BCMA_CC_SLOWCLKCTL              0x00B8          /* 6 <= Rev <= 9 only */
+#define  BCMA_CC_SLOWCLKCTL_SRC         0x00000007      /* slow clock source mask */
+#define   BCMA_CC_SLOWCLKCTL_SRC_LPO    0x00000000      /* source of slow clock is LPO */
+#define   BCMA_CC_SLOWCLKCTL_SRC_XTAL   0x00000001      /* source of slow clock is crystal */
+#define   BCMA_CC_SLOECLKCTL_SRC_PCI    0x00000002      /* source of slow clock is PCI */
+#define  BCMA_CC_SLOWCLKCTL_LPOFREQ     0x00000200      /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
+#define  BCMA_CC_SLOWCLKCTL_LPOPD       0x00000400      /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
+#define  BCMA_CC_SLOWCLKCTL_FSLOW       0x00000800      /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
+#define  BCMA_CC_SLOWCLKCTL_IPLL        0x00001000      /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
+#define  BCMA_CC_SLOWCLKCTL_ENXTAL      0x00002000      /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
+#define  BCMA_CC_SLOWCLKCTL_XTALPU      0x00004000      /* XtalPU (RO), 1/0: crystal running/disabled */
+#define  BCMA_CC_SLOWCLKCTL_CLKDIV      0xFFFF0000      /* ClockDivider (SlowClk = 1/(4+divisor)) */
+#define  BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT        16
+#define BCMA_CC_SYSCLKCTL               0x00C0          /* Rev >= 3 only */
+#define  BCMA_CC_SYSCLKCTL_IDLPEN       0x00000001      /* ILPen: Enable Idle Low Power */
+#define  BCMA_CC_SYSCLKCTL_ALPEN        0x00000002      /* ALPen: Enable Active Low Power */
+#define  BCMA_CC_SYSCLKCTL_PLLEN        0x00000004      /* ForcePLLOn */
+#define  BCMA_CC_SYSCLKCTL_FORCEALP     0x00000008      /* Force ALP (or HT if ALPen is not set */
+#define  BCMA_CC_SYSCLKCTL_FORCEHT      0x00000010      /* Force HT */
+#define  BCMA_CC_SYSCLKCTL_CLKDIV       0xFFFF0000      /* ClkDiv  (ILP = 1/(4+divisor)) */
+#define  BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
+#define BCMA_CC_CLKSTSTR                0x00C4          /* Rev >= 3 only */
+#define BCMA_CC_EROM                    0x00FC
+#define BCMA_CC_PCMCIA_CFG              0x0100
+#define BCMA_CC_PCMCIA_MEMWAIT          0x0104
+#define BCMA_CC_PCMCIA_ATTRWAIT         0x0108
+#define BCMA_CC_PCMCIA_IOWAIT           0x010C
+#define BCMA_CC_IDE_CFG                 0x0110
+#define BCMA_CC_IDE_MEMWAIT             0x0114
+#define BCMA_CC_IDE_ATTRWAIT            0x0118
+#define BCMA_CC_IDE_IOWAIT              0x011C
+#define BCMA_CC_PROG_CFG                0x0120
+#define BCMA_CC_PROG_WAITCNT            0x0124
+#define BCMA_CC_FLASH_CFG               0x0128
+#define BCMA_CC_FLASH_WAITCNT           0x012C
+#define BCMA_CC_CLKCTLST                0x01E0 /* Clock control and status (rev >= 20) */
+#define  BCMA_CC_CLKCTLST_FORCEALP      0x00000001 /* Force ALP request */
+#define  BCMA_CC_CLKCTLST_FORCEHT       0x00000002 /* Force HT request */
+#define  BCMA_CC_CLKCTLST_FORCEILP      0x00000004 /* Force ILP request */
+#define  BCMA_CC_CLKCTLST_HAVEALPREQ    0x00000008 /* ALP available request */
+#define  BCMA_CC_CLKCTLST_HAVEHTREQ     0x00000010 /* HT available request */
+#define  BCMA_CC_CLKCTLST_HWCROFF       0x00000020 /* Force HW clock request off */
+#define  BCMA_CC_CLKCTLST_HAVEHT        0x00010000 /* HT available */
+#define  BCMA_CC_CLKCTLST_HAVEALP       0x00020000 /* APL available */
+#define BCMA_CC_HW_WORKAROUND           0x01E4 /* Hardware workaround (rev >= 20) */
+#define BCMA_CC_UART0_DATA              0x0300
+#define BCMA_CC_UART0_IMR               0x0304
+#define BCMA_CC_UART0_FCR               0x0308
+#define BCMA_CC_UART0_LCR               0x030C
+#define BCMA_CC_UART0_MCR               0x0310
+#define BCMA_CC_UART0_LSR               0x0314
+#define BCMA_CC_UART0_MSR               0x0318
+#define BCMA_CC_UART0_SCRATCH           0x031C
+#define BCMA_CC_UART1_DATA              0x0400
+#define BCMA_CC_UART1_IMR               0x0404
+#define BCMA_CC_UART1_FCR               0x0408
+#define BCMA_CC_UART1_LCR               0x040C
+#define BCMA_CC_UART1_MCR               0x0410
+#define BCMA_CC_UART1_LSR               0x0414
+#define BCMA_CC_UART1_MSR               0x0418
+#define BCMA_CC_UART1_SCRATCH           0x041C
+/* PMU registers (rev >= 20) */
+#define BCMA_CC_PMU_CTL                 0x0600 /* PMU control */
+#define  BCMA_CC_PMU_CTL_ILP_DIV        0xFFFF0000 /* ILP div mask */
+#define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT  16
+#define  BCMA_CC_PMU_CTL_NOILPONW       0x00000200 /* No ILP on wait */
+#define  BCMA_CC_PMU_CTL_HTREQEN        0x00000100 /* HT req enable */
+#define  BCMA_CC_PMU_CTL_ALPREQEN       0x00000080 /* ALP req enable */
+#define  BCMA_CC_PMU_CTL_XTALFREQ       0x0000007C /* Crystal freq */
+#define  BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
+#define  BCMA_CC_PMU_CTL_ILPDIVEN       0x00000002 /* ILP div enable */
+#define  BCMA_CC_PMU_CTL_LPOSEL         0x00000001 /* LPO sel */
+#define BCMA_CC_PMU_CAP                 0x0604 /* PMU capabilities */
+#define  BCMA_CC_PMU_CAP_REVISION       0x000000FF /* Revision mask */
+#define BCMA_CC_PMU_STAT                0x0608 /* PMU status */
+#define  BCMA_CC_PMU_STAT_INTPEND       0x00000040 /* Interrupt pending */
+#define  BCMA_CC_PMU_STAT_SBCLKST       0x00000030 /* Backplane clock status? */
+#define  BCMA_CC_PMU_STAT_HAVEALP       0x00000008 /* ALP available */
+#define  BCMA_CC_PMU_STAT_HAVEHT        0x00000004 /* HT available */
+#define  BCMA_CC_PMU_STAT_RESINIT       0x00000003 /* Res init */
+#define BCMA_CC_PMU_RES_STAT            0x060C /* PMU res status */
+#define BCMA_CC_PMU_RES_PEND            0x0610 /* PMU res pending */
+#define BCMA_CC_PMU_TIMER               0x0614 /* PMU timer */
+#define BCMA_CC_PMU_MINRES_MSK          0x0618 /* PMU min res mask */
+#define BCMA_CC_PMU_MAXRES_MSK          0x061C /* PMU max res mask */
+#define BCMA_CC_PMU_RES_TABSEL          0x0620 /* PMU res table sel */
+#define BCMA_CC_PMU_RES_DEPMSK          0x0624 /* PMU res dep mask */
+#define BCMA_CC_PMU_RES_UPDNTM          0x0628 /* PMU res updown timer */
+#define BCMA_CC_PMU_RES_TIMER           0x062C /* PMU res timer */
+#define BCMA_CC_PMU_CLKSTRETCH          0x0630 /* PMU clockstretch */
+#define BCMA_CC_PMU_WATCHDOG            0x0634 /* PMU watchdog */
+#define BCMA_CC_PMU_RES_REQTS           0x0640 /* PMU res req timer sel */
+#define BCMA_CC_PMU_RES_REQT            0x0644 /* PMU res req timer */
+#define BCMA_CC_PMU_RES_REQM            0x0648 /* PMU res req mask */
+#define BCMA_CC_CHIPCTL_ADDR            0x0650
+#define BCMA_CC_CHIPCTL_DATA            0x0654
+#define BCMA_CC_REGCTL_ADDR             0x0658
+#define BCMA_CC_REGCTL_DATA             0x065C
+#define BCMA_CC_PLLCTL_ADDR             0x0660
+#define BCMA_CC_PLLCTL_DATA             0x0664
+
+/* Data for the PMU, if available.
+ * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
+ */
+struct bcma_chipcommon_pmu {
+        u8 rev;                 /* PMU revision */
+        u32 crystalfreq;        /* The active crystal frequency (in kHz) */
+};
+
+struct bcma_drv_cc {
+        struct bcma_device *core;
+        u32 status;
+        u32 capabilities;
+        u32 capabilities_ext;
+        /* Fast Powerup Delay constant */
+        u16 fast_pwrup_delay;
+        struct bcma_chipcommon_pmu pmu;
+};
+
+/* Register access */
+#define bcma_cc_read32(cc, offset) \
+        bcma_read32((cc)->core, offset)
+#define bcma_cc_write32(cc, offset, val) \
+        bcma_write32((cc)->core, offset, val)
+
+#define bcma_cc_mask32(cc, offset, mask) \
+        bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
+#define bcma_cc_set32(cc, offset, set) \
+        bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
+#define bcma_cc_maskset32(cc, offset, mask, set) \
+        bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
+
+extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
+
+extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
+extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
+
+extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
+                                          u32 ticks);
+
+void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+
+u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
+
+/* Chipcommon GPIO pin access. */
+u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
+u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
+u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
+u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
+u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
+
+/* PMU support */
+extern void bcma_pmu_init(struct bcma_drv_cc *cc);
+
+#endif /* LINUX_BCMA_DRIVER_CC_H_ */
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
new file mode 100644
index 000000000000..b7e191cf00ec
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -0,0 +1,89 @@
+#ifndef LINUX_BCMA_DRIVER_PCI_H_
+#define LINUX_BCMA_DRIVER_PCI_H_
+
+#include <linux/types.h>
+
+struct pci_dev;
+
+/** PCI core registers. **/
+#define BCMA_CORE_PCI_CTL                       0x0000  /* PCI Control */
+#define  BCMA_CORE_PCI_CTL_RST_OE               0x00000001 /* PCI_RESET Output Enable */
+#define  BCMA_CORE_PCI_CTL_RST                  0x00000002 /* PCI_RESET driven out to pin */
+#define  BCMA_CORE_PCI_CTL_CLK_OE               0x00000004 /* Clock gate Output Enable */
+#define  BCMA_CORE_PCI_CTL_CLK                  0x00000008 /* Gate for clock driven out to pin */
+#define BCMA_CORE_PCI_ARBCTL                    0x0010  /* PCI Arbiter Control */
+#define  BCMA_CORE_PCI_ARBCTL_INTERN            0x00000001 /* Use internal arbiter */
+#define  BCMA_CORE_PCI_ARBCTL_EXTERN            0x00000002 /* Use external arbiter */
+#define  BCMA_CORE_PCI_ARBCTL_PARKID            0x00000006 /* Mask, selects which agent is parked on an idle bus */
+#define   BCMA_CORE_PCI_ARBCTL_PARKID_LAST      0x00000000 /* Last requestor */
+#define   BCMA_CORE_PCI_ARBCTL_PARKID_4710      0x00000002 /* 4710 */
+#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT0      0x00000004 /* External requestor 0 */
+#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT1      0x00000006 /* External requestor 1 */
+#define BCMA_CORE_PCI_ISTAT                     0x0020  /* Interrupt status */
+#define  BCMA_CORE_PCI_ISTAT_INTA               0x00000001 /* PCI INTA# */
+#define  BCMA_CORE_PCI_ISTAT_INTB               0x00000002 /* PCI INTB# */
+#define  BCMA_CORE_PCI_ISTAT_SERR               0x00000004 /* PCI SERR# (write to clear) */
+#define  BCMA_CORE_PCI_ISTAT_PERR               0x00000008 /* PCI PERR# (write to clear) */
+#define  BCMA_CORE_PCI_ISTAT_PME                0x00000010 /* PCI PME# */
+#define BCMA_CORE_PCI_IMASK                     0x0024  /* Interrupt mask */
+#define  BCMA_CORE_PCI_IMASK_INTA               0x00000001 /* PCI INTA# */
+#define  BCMA_CORE_PCI_IMASK_INTB               0x00000002 /* PCI INTB# */
+#define  BCMA_CORE_PCI_IMASK_SERR               0x00000004 /* PCI SERR# */
+#define  BCMA_CORE_PCI_IMASK_PERR               0x00000008 /* PCI PERR# */
+#define  BCMA_CORE_PCI_IMASK_PME                0x00000010 /* PCI PME# */
+#define BCMA_CORE_PCI_MBOX                      0x0028  /* Backplane to PCI Mailbox */
+#define  BCMA_CORE_PCI_MBOX_F0_0                0x00000100 /* PCI function 0, INT 0 */
+#define  BCMA_CORE_PCI_MBOX_F0_1                0x00000200 /* PCI function 0, INT 1 */
+#define  BCMA_CORE_PCI_MBOX_F1_0                0x00000400 /* PCI function 1, INT 0 */
+#define  BCMA_CORE_PCI_MBOX_F1_1                0x00000800 /* PCI function 1, INT 1 */
+#define  BCMA_CORE_PCI_MBOX_F2_0                0x00001000 /* PCI function 2, INT 0 */
+#define  BCMA_CORE_PCI_MBOX_F2_1                0x00002000 /* PCI function 2, INT 1 */
+#define  BCMA_CORE_PCI_MBOX_F3_0                0x00004000 /* PCI function 3, INT 0 */
+#define  BCMA_CORE_PCI_MBOX_F3_1                0x00008000 /* PCI function 3, INT 1 */
+#define BCMA_CORE_PCI_BCAST_ADDR                0x0050  /* Backplane Broadcast Address */
+#define  BCMA_CORE_PCI_BCAST_ADDR_MASK          0x000000FF
+#define BCMA_CORE_PCI_BCAST_DATA                0x0054  /* Backplane Broadcast Data */
+#define BCMA_CORE_PCI_GPIO_IN                   0x0060  /* rev >= 2 only */
+#define BCMA_CORE_PCI_GPIO_OUT                  0x0064  /* rev >= 2 only */
+#define BCMA_CORE_PCI_GPIO_ENABLE               0x0068  /* rev >= 2 only */
+#define BCMA_CORE_PCI_GPIO_CTL                  0x006C  /* rev >= 2 only */
+#define BCMA_CORE_PCI_SBTOPCI0                  0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
+#define  BCMA_CORE_PCI_SBTOPCI0_MASK            0xFC000000
+#define BCMA_CORE_PCI_SBTOPCI1                  0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
+#define  BCMA_CORE_PCI_SBTOPCI1_MASK            0xFC000000
+#define BCMA_CORE_PCI_SBTOPCI2                  0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
+#define  BCMA_CORE_PCI_SBTOPCI2_MASK            0xC0000000
+#define BCMA_CORE_PCI_PCICFG0                   0x0400  /* PCI config space 0 (rev >= 8) */
+#define BCMA_CORE_PCI_PCICFG1                   0x0500  /* PCI config space 1 (rev >= 8) */
+#define BCMA_CORE_PCI_PCICFG2                   0x0600  /* PCI config space 2 (rev >= 8) */
+#define BCMA_CORE_PCI_PCICFG3                   0x0700  /* PCI config space 3 (rev >= 8) */
+#define BCMA_CORE_PCI_SPROM(wordoffset)         (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
+
+/* SBtoPCIx */
+#define BCMA_CORE_PCI_SBTOPCI_MEM               0x00000000
+#define BCMA_CORE_PCI_SBTOPCI_IO                0x00000001
+#define BCMA_CORE_PCI_SBTOPCI_CFG0              0x00000002
+#define BCMA_CORE_PCI_SBTOPCI_CFG1              0x00000003
+#define BCMA_CORE_PCI_SBTOPCI_PREF              0x00000004 /* Prefetch enable */
+#define BCMA_CORE_PCI_SBTOPCI_BURST             0x00000008 /* Burst enable */
+#define BCMA_CORE_PCI_SBTOPCI_MRM               0x00000020 /* Memory Read Multiple */
+#define BCMA_CORE_PCI_SBTOPCI_RC                0x00000030 /* Read Command mask (rev >= 11) */
+#define  BCMA_CORE_PCI_SBTOPCI_RC_READ          0x00000000 /* Memory read */
+#define  BCMA_CORE_PCI_SBTOPCI_RC_READL         0x00000010 /* Memory read line */
+#define  BCMA_CORE_PCI_SBTOPCI_RC_READM         0x00000020 /* Memory read multiple */
+
+/* PCIcore specific boardflags */
+#define BCMA_CORE_PCI_BFL_NOPCI                 0x00000400 /* Board leaves PCI floating */
+
+struct bcma_drv_pci {
+        struct bcma_device *core;
+        u8 setup_done:1;
+};
+
+/* Register access */
+#define pcicore_read32(pc, offset)              bcma_read32((pc)->core, offset)
+#define pcicore_write32(pc, offset, val)        bcma_write32((pc)->core, offset, val)
+
+extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
+
+#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
new file mode 100644
index 000000000000..f82d88a960ce
--- /dev/null
+++ b/include/linux/bcma/bcma_regs.h
@@ -0,0 +1,34 @@
+#ifndef LINUX_BCMA_REGS_H_
+#define LINUX_BCMA_REGS_H_
+
+/* Agent registers (common for every core) */
+#define BCMA_IOCTL                      0x0408
+#define  BCMA_IOCTL_CLK                 0x0001
+#define  BCMA_IOCTL_FGC                 0x0002
+#define  BCMA_IOCTL_CORE_BITS           0x3FFC
+#define  BCMA_IOCTL_PME_EN              0x4000
+#define  BCMA_IOCTL_BIST_EN             0x8000
+#define BCMA_RESET_CTL                  0x0800
+#define  BCMA_RESET_CTL_RESET           0x0001
+
+/* BCMA PCI config space registers. */
+#define BCMA_PCI_PMCSR                  0x44
+#define  BCMA_PCI_PE                    0x100
+#define BCMA_PCI_BAR0_WIN               0x80    /* Backplane address space 0 */
+#define BCMA_PCI_BAR1_WIN               0x84    /* Backplane address space 1 */
+#define BCMA_PCI_SPROMCTL               0x88    /* SPROM control */
+#define  BCMA_PCI_SPROMCTL_WE           0x10    /* SPROM write enable */
+#define BCMA_PCI_BAR1_CONTROL           0x8c    /* Address space 1 burst control */
+#define BCMA_PCI_IRQS                   0x90    /* PCI interrupts */
+#define BCMA_PCI_IRQMASK                0x94    /* PCI IRQ control and mask (pcirev >= 6 only) */
+#define BCMA_PCI_BACKPLANE_IRQS         0x98    /* Backplane Interrupts */
+#define BCMA_PCI_BAR0_WIN2              0xAC
+#define BCMA_PCI_GPIO_IN                0xB0    /* GPIO Input (pcirev >= 3 only) */
+#define BCMA_PCI_GPIO_OUT               0xB4    /* GPIO Output (pcirev >= 3 only) */
+#define BCMA_PCI_GPIO_OUT_ENABLE        0xB8    /* GPIO Output Enable/Disable (pcirev >= 3 only) */
+#define  BCMA_PCI_GPIO_SCS              0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
+#define  BCMA_PCI_GPIO_HWRAD            0x20    /* PCI config space GPIO 13 for hw radio disable */
+#define  BCMA_PCI_GPIO_XTAL             0x40    /* PCI config space GPIO 14 for Xtal powerup */
+#define  BCMA_PCI_GPIO_PLL              0x80    /* PCI config space GPIO 15 for PLL powerdown */
+
+#endif /* LINUX_BCMA_REGS_H_ */
diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 79690b710665..b2eee5879883 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -1002,6 +1002,11 @@ struct ieee80211_ht_info {
 
 #define WLAN_CAPABILITY_ESS             (1<<0)
 #define WLAN_CAPABILITY_IBSS            (1<<1)
+
+/* A mesh STA sets the ESS and IBSS capability bits to zero */
+#define WLAN_CAPABILITY_IS_MBSS(cap)    \
+        (!((cap) & (WLAN_CAPABILITY_ESS | WLAN_CAPABILITY_IBSS)))
+
 #define WLAN_CAPABILITY_CF_POLLABLE     (1<<2)
 #define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
 #define WLAN_CAPABILITY_PRIVACY         (1<<4)
@@ -1261,9 +1266,8 @@ enum ieee80211_category {
         WLAN_CATEGORY_MULTIHOP_ACTION = 14,
         WLAN_CATEGORY_SELF_PROTECTED = 15,
         WLAN_CATEGORY_WMM = 17,
-        /* TODO: remove MESH_PLINK and MESH_PATH_SEL after */
-        /*       mesh is updated to current 802.11s draft  */
-        WLAN_CATEGORY_MESH_PLINK = 30,
+        /* TODO: remove MESH_PATH_SEL after mesh is updated
+         * to current 802.11s draft  */
         WLAN_CATEGORY_MESH_PATH_SEL = 32,
         WLAN_CATEGORY_VENDOR_SPECIFIC_PROTECTED = 126,
         WLAN_CATEGORY_VENDOR_SPECIFIC = 127,
@@ -1516,6 +1520,7 @@ static inline bool ieee80211_is_robust_mgmt_frame(struct ieee80211_hdr *hdr)
                 category = ((u8 *) hdr) + 24;
                 return *category != WLAN_CATEGORY_PUBLIC &&
                         *category != WLAN_CATEGORY_HT &&
+                        *category != WLAN_CATEGORY_SELF_PROTECTED &&
                         *category != WLAN_CATEGORY_VENDOR_SPECIFIC;
         }
 
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 48c007dae476..ae28e93fd072 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -382,6 +382,23 @@ struct ssb_device_id {
 #define SSB_ANY_ID              0xFFFF
 #define SSB_ANY_REV             0xFF
 
+/* Broadcom's specific AMBA core, see drivers/bcma/ */
+struct bcma_device_id {
+        __u16   manuf;
+        __u16   id;
+        __u8    rev;
+        __u8    class;
+};
+#define BCMA_CORE(_manuf, _id, _rev, _class)  \
+        { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
+#define BCMA_CORETABLE_END  \
+        { 0, },
+
+#define BCMA_ANY_MANUF          0xFFFF
+#define BCMA_ANY_ID             0xFFFF
+#define BCMA_ANY_REV            0xFF
+#define BCMA_ANY_CLASS          0xFF
+
 struct virtio_device_id {
         __u32 device;
         __u32 vendor;
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 216b1d8a862f..c7ccaae15af6 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -77,6 +77,39 @@
  */
 
 /**
+ * DOC: Virtual interface / concurrency capabilities
+ *
+ * Some devices are able to operate with virtual MACs, they can have
+ * more than one virtual interface. The capability handling for this
+ * is a bit complex though, as there may be a number of restrictions
+ * on the types of concurrency that are supported.
+ *
+ * To start with, each device supports the interface types listed in
+ * the %NL80211_ATTR_SUPPORTED_IFTYPES attribute, but by listing the
+ * types there no concurrency is implied.
+ *
+ * Once concurrency is desired, more attributes must be observed:
+ * To start with, since some interface types are purely managed in
+ * software, like the AP-VLAN type in mac80211 for example, there's
+ * an additional list of these, they can be added at any time and
+ * are only restricted by some semantic restrictions (e.g. AP-VLAN
+ * cannot be added without a corresponding AP interface). This list
+ * is exported in the %NL80211_ATTR_SOFTWARE_IFTYPES attribute.
+ *
+ * Further, the list of supported combinations is exported. This is
+ * in the %NL80211_ATTR_INTERFACE_COMBINATIONS attribute. Basically,
+ * it exports a list of "groups", and at any point in time the
+ * interfaces that are currently active must fall into any one of
+ * the advertised groups. Within each group, there are restrictions
+ * on the number of interfaces of different types that are supported
+ * and also the number of different channels, along with potentially
+ * some other restrictions. See &enum nl80211_if_combination_attrs.
+ *
+ * All together, these attributes define the concurrency of virtual
+ * interfaces that a given device supports.
+ */
+
+/**
  * enum nl80211_commands - supported nl80211 commands
  *
  * @NL80211_CMD_UNSPEC: unspecified command to catch errors
@@ -203,6 +236,28 @@
  * @NL80211_CMD_SCAN_ABORTED: scan was aborted, for unspecified reasons,
  *      partial scan results may be available
  *
+ * @NL80211_CMD_START_SCHED_SCAN: start a scheduled scan at certain
+ *      intervals, as specified by %NL80211_ATTR_SCHED_SCAN_INTERVAL.
+ *      Like with normal scans, if SSIDs (%NL80211_ATTR_SCAN_SSIDS)
+ *      are passed, they are used in the probe requests.  For
+ *      broadcast, a broadcast SSID must be passed (ie. an empty
+ *      string).  If no SSID is passed, no probe requests are sent and
+ *      a passive scan is performed.  %NL80211_ATTR_SCAN_FREQUENCIES,
+ *      if passed, define which channels should be scanned; if not
+ *      passed, all channels allowed for the current regulatory domain
+ *      are used.  Extra IEs can also be passed from the userspace by
+ *      using the %NL80211_ATTR_IE attribute.
+ * @NL80211_CMD_STOP_SCHED_SCAN: stop a scheduled scan
+ * @NL80211_CMD_SCHED_SCAN_RESULTS: indicates that there are scheduled scan
+ *      results available.
+ * @NL80211_CMD_SCHED_SCAN_STOPPED: indicates that the scheduled scan has
+ *      stopped.  The driver may issue this event at any time during a
+ *      scheduled scan.  One reason for stopping the scan is if the hardware
+ *      does not support starting an association or a normal scan while running
+ *      a scheduled scan.  This event is also sent when the
+ *      %NL80211_CMD_STOP_SCHED_SCAN command is received or when the interface
+ *      is brought down while a scheduled scan was running.
+ *
  * @NL80211_CMD_GET_SURVEY: get survey resuls, e.g. channel occupation
  *      or noise level
  * @NL80211_CMD_NEW_SURVEY_RESULTS: survey data notification (as a reply to
@@ -420,6 +475,14 @@
  *      new station with the AUTHENTICATED flag unset and maybe change it later
  *      depending on the authentication result.
  *
+ * @NL80211_CMD_GET_WOWLAN: get Wake-on-Wireless-LAN (WoWLAN) settings.
+ * @NL80211_CMD_SET_WOWLAN: set Wake-on-Wireless-LAN (WoWLAN) settings.
+ *      Since wireless is more complex than wired ethernet, it supports
+ *      various triggers. These triggers can be configured through this
+ *      command with the %NL80211_ATTR_WOWLAN_TRIGGERS attribute. For
+ *      more background information, see
+ *      http://wireless.kernel.org/en/users/Documentation/WoWLAN.
+ *
  * @NL80211_CMD_MAX: highest used command number
  * @__NL80211_CMD_AFTER_LAST: internal use
  */
@@ -534,6 +597,14 @@ enum nl80211_commands {
 
         NL80211_CMD_NEW_PEER_CANDIDATE,
 
+        NL80211_CMD_GET_WOWLAN,
+        NL80211_CMD_SET_WOWLAN,
+
+        NL80211_CMD_START_SCHED_SCAN,
+        NL80211_CMD_STOP_SCHED_SCAN,
+        NL80211_CMD_SCHED_SCAN_RESULTS,
+        NL80211_CMD_SCHED_SCAN_STOPPED,
+
         /* add new commands above here */
 
         /* used to define NL80211_CMD_MAX below */
@@ -902,6 +973,28 @@ enum nl80211_commands {
  * @NL80211_ATTR_SUPPORT_MESH_AUTH: Currently, this means the underlying driver
  *      allows auth frames in a mesh to be passed to userspace for processing via
  *      the @NL80211_MESH_SETUP_USERSPACE_AUTH flag.
+ * @NL80211_ATTR_STA_PLINK_STATE: The state of a mesh peer link as
+ *      defined in &enum nl80211_plink_state. Used when userspace is
+ *      driving the peer link management state machine.
+ *      @NL80211_MESH_SETUP_USERSPACE_AMPE must be enabled.
+ *
+ * @NL80211_ATTR_WOWLAN_SUPPORTED: indicates, as part of the wiphy capabilities,
+ *      the supported WoWLAN triggers
+ * @NL80211_ATTR_WOWLAN_TRIGGERS: used by %NL80211_CMD_SET_WOWLAN to
+ *      indicate which WoW triggers should be enabled. This is also
+ *      used by %NL80211_CMD_GET_WOWLAN to get the currently enabled WoWLAN
+ *      triggers.
+
+ * @NL80211_ATTR_SCHED_SCAN_INTERVAL: Interval between scheduled scan
+ *      cycles, in msecs.
+ *
+ * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported
+ *      interface combinations. In each nested item, it contains attributes
+ *      defined in &enum nl80211_if_combination_attrs.
+ * @NL80211_ATTR_SOFTWARE_IFTYPES: Nested attribute (just like
+ *      %NL80211_ATTR_SUPPORTED_IFTYPES) containing the interface types that
+ *      are managed in software: interfaces of these types aren't subject to
+ *      any restrictions in their number or combinations.
  *
  * @NL80211_ATTR_MAX: highest attribute number currently defined
  * @__NL80211_ATTR_AFTER_LAST: internal use
@@ -1091,6 +1184,15 @@ enum nl80211_attrs {
         NL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX,
 
         NL80211_ATTR_SUPPORT_MESH_AUTH,
+        NL80211_ATTR_STA_PLINK_STATE,
+
+        NL80211_ATTR_WOWLAN_TRIGGERS,
+        NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED,
+
+        NL80211_ATTR_SCHED_SCAN_INTERVAL,
+
+        NL80211_ATTR_INTERFACE_COMBINATIONS,
+        NL80211_ATTR_SOFTWARE_IFTYPES,
 
         /* add attributes here, update the policy in nl80211.c */
 
@@ -1144,7 +1246,9 @@ enum nl80211_attrs {
  * @NL80211_IFTYPE_ADHOC: independent BSS member
  * @NL80211_IFTYPE_STATION: managed BSS member
  * @NL80211_IFTYPE_AP: access point
- * @NL80211_IFTYPE_AP_VLAN: VLAN interface for access points
+ * @NL80211_IFTYPE_AP_VLAN: VLAN interface for access points; VLAN interfaces
+ *      are a bit special in that they must always be tied to a pre-existing
+ *      AP type interface.
  * @NL80211_IFTYPE_WDS: wireless distribution interface
  * @NL80211_IFTYPE_MONITOR: monitor interface receiving all frames
  * @NL80211_IFTYPE_MESH_POINT: mesh point
@@ -1293,6 +1397,7 @@ enum nl80211_sta_bss_param {
  * @NL80211_STA_INFO_LLID: the station's mesh LLID
  * @NL80211_STA_INFO_PLID: the station's mesh PLID
  * @NL80211_STA_INFO_PLINK_STATE: peer link state for the station
+ *      (see %enum nl80211_plink_state)
  * @NL80211_STA_INFO_RX_BITRATE: last unicast data frame rx rate, nested
  *      attribute, like NL80211_STA_INFO_TX_BITRATE.
  * @NL80211_STA_INFO_BSS_PARAM: current station's view of BSS, nested attribute
@@ -1748,6 +1853,15 @@ enum nl80211_meshconf_params {
  * @NL80211_MESH_SETUP_USERSPACE_AUTH: Enable this option if an authentication
  * daemon will be authenticating mesh candidates.
  *
+ * @NL80211_MESH_SETUP_USERSPACE_AMPE: Enable this option if an authentication
+ * daemon will be securing peer link frames.  AMPE is a secured version of Mesh
+ * Peering Management (MPM) and is implemented with the assistance of a
+ * userspace daemon.  When this flag is set, the kernel will send peer
+ * management frames to a userspace daemon that will implement AMPE
+ * functionality (security capabilities selection, key confirmation, and key
+ * management).  When the flag is unset (default), the kernel can autonomously
+ * complete (unsecured) mesh peering without the need of a userspace daemon.
+ *
  * @NL80211_MESH_SETUP_ATTR_MAX: highest possible mesh setup attribute number
  * @__NL80211_MESH_SETUP_ATTR_AFTER_LAST: Internal use
  */
@@ -1757,6 +1871,7 @@ enum nl80211_mesh_setup_params {
         NL80211_MESH_SETUP_ENABLE_VENDOR_METRIC,
         NL80211_MESH_SETUP_IE,
         NL80211_MESH_SETUP_USERSPACE_AUTH,
+        NL80211_MESH_SETUP_USERSPACE_AMPE,
 
         /* keep last */
         __NL80211_MESH_SETUP_ATTR_AFTER_LAST,
@@ -2061,4 +2176,189 @@ enum nl80211_tx_power_setting {
         NL80211_TX_POWER_FIXED,
 };
 
+/**
+ * enum nl80211_wowlan_packet_pattern_attr - WoWLAN packet pattern attribute
+ * @__NL80211_WOWLAN_PKTPAT_INVALID: invalid number for nested attribute
+ * @NL80211_WOWLAN_PKTPAT_PATTERN: the pattern, values where the mask has
+ *      a zero bit are ignored
+ * @NL80211_WOWLAN_PKTPAT_MASK: pattern mask, must be long enough to have
+ *      a bit for each byte in the pattern. The lowest-order bit corresponds
+ *      to the first byte of the pattern, but the bytes of the pattern are
+ *      in a little-endian-like format, i.e. the 9th byte of the pattern
+ *      corresponds to the lowest-order bit in the second byte of the mask.
+ *      For example: The match 00:xx:00:00:xx:00:00:00:00:xx:xx:xx (where
+ *      xx indicates "don't care") would be represented by a pattern of
+ *      twelve zero bytes, and a mask of "0xed,0x07".
+ *      Note that the pattern matching is done as though frames were not
+ *      802.11 frames but 802.3 frames, i.e. the frame is fully unpacked
+ *      first (including SNAP header unpacking) and then matched.
+ * @NUM_NL80211_WOWLAN_PKTPAT: number of attributes
+ * @MAX_NL80211_WOWLAN_PKTPAT: max attribute number
+ */
+enum nl80211_wowlan_packet_pattern_attr {
+        __NL80211_WOWLAN_PKTPAT_INVALID,
+        NL80211_WOWLAN_PKTPAT_MASK,
+        NL80211_WOWLAN_PKTPAT_PATTERN,
+
+        NUM_NL80211_WOWLAN_PKTPAT,
+        MAX_NL80211_WOWLAN_PKTPAT = NUM_NL80211_WOWLAN_PKTPAT - 1,
+};
+
+/**
+ * struct nl80211_wowlan_pattern_support - pattern support information
+ * @max_patterns: maximum number of patterns supported
+ * @min_pattern_len: minimum length of each pattern
+ * @max_pattern_len: maximum length of each pattern
+ *
+ * This struct is carried in %NL80211_WOWLAN_TRIG_PKT_PATTERN when
+ * that is part of %NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED in the
+ * capability information given by the kernel to userspace.
+ */
+struct nl80211_wowlan_pattern_support {
+        __u32 max_patterns;
+        __u32 min_pattern_len;
+        __u32 max_pattern_len;
+} __attribute__((packed));
+
+/**
+ * enum nl80211_wowlan_triggers - WoWLAN trigger definitions
+ * @__NL80211_WOWLAN_TRIG_INVALID: invalid number for nested attributes
+ * @NL80211_WOWLAN_TRIG_ANY: wake up on any activity, do not really put
+ *      the chip into a special state -- works best with chips that have
+ *      support for low-power operation already (flag)
+ * @NL80211_WOWLAN_TRIG_DISCONNECT: wake up on disconnect, the way disconnect
+ *      is detected is implementation-specific (flag)
+ * @NL80211_WOWLAN_TRIG_MAGIC_PKT: wake up on magic packet (6x 0xff, followed
+ *      by 16 repetitions of MAC addr, anywhere in payload) (flag)
+ * @NL80211_WOWLAN_TRIG_PKT_PATTERN: wake up on the specified packet patterns
+ *      which are passed in an array of nested attributes, each nested attribute
+ *      defining a with attributes from &struct nl80211_wowlan_trig_pkt_pattern.
+ *      Each pattern defines a wakeup packet. The matching is done on the MSDU,
+ *      i.e. as though the packet was an 802.3 packet, so the pattern matching
+ *      is done after the packet is converted to the MSDU.
+ *
+ *      In %NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED, it is a binary attribute
+ *      carrying a &struct nl80211_wowlan_pattern_support.
+ * @NUM_NL80211_WOWLAN_TRIG: number of wake on wireless triggers
+ * @MAX_NL80211_WOWLAN_TRIG: highest wowlan trigger attribute number
+ */
+enum nl80211_wowlan_triggers {
+        __NL80211_WOWLAN_TRIG_INVALID,
+        NL80211_WOWLAN_TRIG_ANY,
+        NL80211_WOWLAN_TRIG_DISCONNECT,
+        NL80211_WOWLAN_TRIG_MAGIC_PKT,
+        NL80211_WOWLAN_TRIG_PKT_PATTERN,
+
+        /* keep last */
+        NUM_NL80211_WOWLAN_TRIG,
+        MAX_NL80211_WOWLAN_TRIG = NUM_NL80211_WOWLAN_TRIG - 1
+};
+
+/**
+ * enum nl80211_iface_limit_attrs - limit attributes
+ * @NL80211_IFACE_LIMIT_UNSPEC: (reserved)
+ * @NL80211_IFACE_LIMIT_MAX: maximum number of interfaces that
+ *      can be chosen from this set of interface types (u32)
+ * @NL80211_IFACE_LIMIT_TYPES: nested attribute containing a
+ *      flag attribute for each interface type in this set
+ * @NUM_NL80211_IFACE_LIMIT: number of attributes
+ * @MAX_NL80211_IFACE_LIMIT: highest attribute number
+ */
+enum nl80211_iface_limit_attrs {
+        NL80211_IFACE_LIMIT_UNSPEC,
+        NL80211_IFACE_LIMIT_MAX,
+        NL80211_IFACE_LIMIT_TYPES,
+
+        /* keep last */
+        NUM_NL80211_IFACE_LIMIT,
+        MAX_NL80211_IFACE_LIMIT = NUM_NL80211_IFACE_LIMIT - 1
+};
+
+/**
+ * enum nl80211_if_combination_attrs -- interface combination attributes
+ *
+ * @NL80211_IFACE_COMB_UNSPEC: (reserved)
+ * @NL80211_IFACE_COMB_LIMITS: Nested attributes containing the limits
+ *      for given interface types, see &enum nl80211_iface_limit_attrs.
+ * @NL80211_IFACE_COMB_MAXNUM: u32 attribute giving the total number of
+ *      interfaces that can be created in this group. This number doesn't
+ *      apply to interfaces purely managed in software, which are listed
+ *      in a separate attribute %NL80211_ATTR_INTERFACES_SOFTWARE.
+ * @NL80211_IFACE_COMB_STA_AP_BI_MATCH: flag attribute specifying that
+ *      beacon intervals within this group must be all the same even for
+ *      infrastructure and AP/GO combinations, i.e. the GO(s) must adopt
+ *      the infrastructure network's beacon interval.
+ * @NL80211_IFACE_COMB_NUM_CHANNELS: u32 attribute specifying how many
+ *      different channels may be used within this group.
+ * @NUM_NL80211_IFACE_COMB: number of attributes
+ * @MAX_NL80211_IFACE_COMB: highest attribute number
+ *
+ * Examples:
+ *      limits = [ #{STA} <= 1, #{AP} <= 1 ], matching BI, channels = 1, max = 2
+ *      => allows an AP and a STA that must match BIs
+ *
+ *      numbers = [ #{AP, P2P-GO} <= 8 ], channels = 1, max = 8
+ *      => allows 8 of AP/GO
+ *
+ *      numbers = [ #{STA} <= 2 ], channels = 2, max = 2
+ *      => allows two STAs on different channels
+ *
+ *      numbers = [ #{STA} <= 1, #{P2P-client,P2P-GO} <= 3 ], max = 4
+ *      => allows a STA plus three P2P interfaces
+ *
+ * The list of these four possiblities could completely be contained
+ * within the %NL80211_ATTR_INTERFACE_COMBINATIONS attribute to indicate
+ * that any of these groups must match.
+ *
+ * "Combinations" of just a single interface will not be listed here,
+ * a single interface of any valid interface type is assumed to always
+ * be possible by itself. This means that implicitly, for each valid
+ * interface type, the following group always exists:
+ *      numbers = [ #{<type>} <= 1 ], channels = 1, max = 1
+ */
+enum nl80211_if_combination_attrs {
+        NL80211_IFACE_COMB_UNSPEC,
+        NL80211_IFACE_COMB_LIMITS,
+        NL80211_IFACE_COMB_MAXNUM,
+        NL80211_IFACE_COMB_STA_AP_BI_MATCH,
+        NL80211_IFACE_COMB_NUM_CHANNELS,
+
+        /* keep last */
+        NUM_NL80211_IFACE_COMB,
+        MAX_NL80211_IFACE_COMB = NUM_NL80211_IFACE_COMB - 1
+};
+
+
+/**
+ * enum nl80211_plink_state - state of a mesh peer link finite state machine
+ *
+ * @NL80211_PLINK_LISTEN: initial state, considered the implicit
+ *      state of non existant mesh peer links
+ * @NL80211_PLINK_OPN_SNT: mesh plink open frame has been sent to
+ *      this mesh peer
+ * @NL80211_PLINK_OPN_RCVD: mesh plink open frame has been received
+ *      from this mesh peer
+ * @NL80211_PLINK_CNF_RCVD: mesh plink confirm frame has been
+ *      received from this mesh peer
+ * @NL80211_PLINK_ESTAB: mesh peer link is established
+ * @NL80211_PLINK_HOLDING: mesh peer link is being closed or cancelled
+ * @NL80211_PLINK_BLOCKED: all frames transmitted from this mesh
+ *      plink are discarded
+ * @NUM_NL80211_PLINK_STATES: number of peer link states
+ * @MAX_NL80211_PLINK_STATES: highest numerical value of plink states
+ */
+enum nl80211_plink_state {
+        NL80211_PLINK_LISTEN,
+        NL80211_PLINK_OPN_SNT,
+        NL80211_PLINK_OPN_RCVD,
+        NL80211_PLINK_CNF_RCVD,
+        NL80211_PLINK_ESTAB,
+        NL80211_PLINK_HOLDING,
+        NL80211_PLINK_BLOCKED,
+
+        /* keep last */
+        NUM_NL80211_PLINK_STATES,
+        MAX_NL80211_PLINK_STATES = NUM_NL80211_PLINK_STATES - 1
+};
+
 #endif /* __LINUX_NL80211_H */
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index 7e99b348834c..f017b8900f78 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
  * Otherwise static always-on powercontrol will be used. */
 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
 
+extern void ssb_commit_settings(struct ssb_bus *bus);
 
 /* Various helper functions */
 extern u32 ssb_admatch_base(u32 adm);