diff options
| author | Jason Cooper <jason@lakedaemon.net> | 2014-09-14 03:53:39 -0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-09-14 03:53:39 -0400 |
| commit | ce92bfe88ba38e76371feb93307125fac3f800f0 (patch) | |
| tree | a10bca9849e16830a846dcabe6bcefcc4a8fbe36 /include/linux | |
| parent | cec9694af7ada37611eb41733065427c0e72cd6c (diff) | |
| parent | 3228950621d92f0f212378f95a6998ef3a1be0bb (diff) | |
Merge branch 'irqchip/gic' into irqchip/core
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/irqchip/arm-gic.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 45e2d8c15bd2..13eed92c7d24 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h | |||
| @@ -21,7 +21,11 @@ | |||
| 21 | #define GIC_CPU_ACTIVEPRIO 0xd0 | 21 | #define GIC_CPU_ACTIVEPRIO 0xd0 |
| 22 | #define GIC_CPU_IDENT 0xfc | 22 | #define GIC_CPU_IDENT 0xfc |
| 23 | 23 | ||
| 24 | #define GICC_ENABLE 0x1 | ||
| 25 | #define GICC_INT_PRI_THRESHOLD 0xf0 | ||
| 24 | #define GICC_IAR_INT_ID_MASK 0x3ff | 26 | #define GICC_IAR_INT_ID_MASK 0x3ff |
| 27 | #define GICC_INT_SPURIOUS 1023 | ||
| 28 | #define GICC_DIS_BYPASS_MASK 0x1e0 | ||
| 25 | 29 | ||
| 26 | #define GIC_DIST_CTRL 0x000 | 30 | #define GIC_DIST_CTRL 0x000 |
| 27 | #define GIC_DIST_CTR 0x004 | 31 | #define GIC_DIST_CTR 0x004 |
| @@ -39,6 +43,18 @@ | |||
| 39 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 | 43 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 |
| 40 | #define GIC_DIST_SGI_PENDING_SET 0xf20 | 44 | #define GIC_DIST_SGI_PENDING_SET 0xf20 |
| 41 | 45 | ||
| 46 | #define GICD_ENABLE 0x1 | ||
| 47 | #define GICD_DISABLE 0x0 | ||
| 48 | #define GICD_INT_ACTLOW_LVLTRIG 0x0 | ||
| 49 | #define GICD_INT_EN_CLR_X32 0xffffffff | ||
| 50 | #define GICD_INT_EN_SET_SGI 0x0000ffff | ||
| 51 | #define GICD_INT_EN_CLR_PPI 0xffff0000 | ||
| 52 | #define GICD_INT_DEF_PRI 0xa0 | ||
| 53 | #define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ | ||
| 54 | (GICD_INT_DEF_PRI << 16) |\ | ||
| 55 | (GICD_INT_DEF_PRI << 8) |\ | ||
| 56 | GICD_INT_DEF_PRI) | ||
| 57 | |||
| 42 | #define GICH_HCR 0x0 | 58 | #define GICH_HCR 0x0 |
| 43 | #define GICH_VTR 0x4 | 59 | #define GICH_VTR 0x4 |
| 44 | #define GICH_VMCR 0x8 | 60 | #define GICH_VMCR 0x8 |
