aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-24 13:21:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-24 13:21:51 -0400
commitab11ca34eea8fda7a1a9302d86f6ef6108ffd68f (patch)
tree987ec6c263f3dfa4a7a6f9ce4d5ece47cbc12e29 /include/linux
parentf9369910a6225b8d4892c3f20ae740a711cd5ace (diff)
parent71006fb22b0f5a2045605b3887ee99a0e9adafe4 (diff)
Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - some V4L2 API updates needed by embedded devices - DVB API extensions for ATSC-MH delivery system, used in US for mobile TV - new tuners for fc0011/0012/0013 and tua9001 - a new dvb driver for af9033/9035 - a new ATSC-MH frontend (lg2160) - new remote controller keymaps - Removal of a few legacy webcam driver that got replaced by gspca on several kernel versions ago - a new driver for Exynos 4/5 webcams(s5pp fimc-lite) - a new webcam sensor driver (smiapp) - a new video input driver for embedded (sta2x1xx) - several improvements, fixes, cleanups, etc inside the drivers. Manually fix up conflicts due to err() -> dev_err() conversion in drivers/staging/media/easycap/easycap_main.c * 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (484 commits) [media] saa7134-cards: Remove a PCI entry added by mistake [media] radio-sf16fmi: add support for SF16-FMD [media] rc-loopback: remove duplicate line [media] patch for Asus My Cinema PS3-100 (1043:48cd) [media] au0828: Move the Kconfig knob under V4L_USB_DRIVERS [media] em28xx: simple comment fix [media] [resend] radio-sf16fmr2: add PnP support for SF16-FMD2 [media] smiapp: Use v4l2_ctrl_new_int_menu() instead of v4l2_ctrl_new_custom() [media] smiapp: Add support for 8-bit uncompressed formats [media] smiapp: Allow generic quirk registers [media] smiapp: Use non-binning limits if the binning limit is zero [media] smiapp: Initialise rval in smiapp_read_nvm() [media] smiapp: Round minimum pre_pll up rather than down in ip_clk_freq check [media] smiapp: Use 8-bit reads only before identifying the sensor [media] smiapp: Quirk for sensors that only do 8-bit reads [media] smiapp: Pass struct sensor to register writing commands instead of i2c_client [media] smiapp: Allow using external clock from the clock framework [media] zl10353: change .read_snr() to report SNR as a 0.1 dB [media] media: add support to gspca/pac7302.c for 093a:2627 (Genius FaceCam 300) [media] m88rs2000 - only flip bit 2 on reg 0x70 on 16th try ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/dvb/frontend.h51
-rw-r--r--include/linux/dvb/version.h2
-rw-r--r--include/linux/fixp-arith.h87
-rw-r--r--include/linux/v4l2-dv-timings.h816
-rw-r--r--include/linux/v4l2-subdev.h41
-rw-r--r--include/linux/videodev2.h372
7 files changed, 1300 insertions, 70 deletions
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 39737839ce29..74af192ef7ae 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -383,6 +383,7 @@ header-y += utime.h
383header-y += utsname.h 383header-y += utsname.h
384header-y += uuid.h 384header-y += uuid.h
385header-y += uvcvideo.h 385header-y += uvcvideo.h
386header-y += v4l2-dv-timings.h
386header-y += v4l2-mediabus.h 387header-y += v4l2-mediabus.h
387header-y += v4l2-subdev.h 388header-y += v4l2-subdev.h
388header-y += veth.h 389header-y += veth.h
diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h
index cb4428ab81ed..f50d4058c5fb 100644
--- a/include/linux/dvb/frontend.h
+++ b/include/linux/dvb/frontend.h
@@ -320,7 +320,24 @@ struct dvb_frontend_event {
320 320
321#define DTV_ENUM_DELSYS 44 321#define DTV_ENUM_DELSYS 44
322 322
323#define DTV_MAX_COMMAND DTV_ENUM_DELSYS 323/* ATSC-MH */
324#define DTV_ATSCMH_FIC_VER 45
325#define DTV_ATSCMH_PARADE_ID 46
326#define DTV_ATSCMH_NOG 47
327#define DTV_ATSCMH_TNOG 48
328#define DTV_ATSCMH_SGN 49
329#define DTV_ATSCMH_PRC 50
330#define DTV_ATSCMH_RS_FRAME_MODE 51
331#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52
332#define DTV_ATSCMH_RS_CODE_MODE_PRI 53
333#define DTV_ATSCMH_RS_CODE_MODE_SEC 54
334#define DTV_ATSCMH_SCCC_BLOCK_MODE 55
335#define DTV_ATSCMH_SCCC_CODE_MODE_A 56
336#define DTV_ATSCMH_SCCC_CODE_MODE_B 57
337#define DTV_ATSCMH_SCCC_CODE_MODE_C 58
338#define DTV_ATSCMH_SCCC_CODE_MODE_D 59
339
340#define DTV_MAX_COMMAND DTV_ATSCMH_SCCC_CODE_MODE_D
324 341
325typedef enum fe_pilot { 342typedef enum fe_pilot {
326 PILOT_ON, 343 PILOT_ON,
@@ -360,6 +377,38 @@ typedef enum fe_delivery_system {
360 377
361#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A 378#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A
362 379
380/* ATSC-MH */
381
382enum atscmh_sccc_block_mode {
383 ATSCMH_SCCC_BLK_SEP = 0,
384 ATSCMH_SCCC_BLK_COMB = 1,
385 ATSCMH_SCCC_BLK_RES = 2,
386};
387
388enum atscmh_sccc_code_mode {
389 ATSCMH_SCCC_CODE_HLF = 0,
390 ATSCMH_SCCC_CODE_QTR = 1,
391 ATSCMH_SCCC_CODE_RES = 2,
392};
393
394enum atscmh_rs_frame_ensemble {
395 ATSCMH_RSFRAME_ENS_PRI = 0,
396 ATSCMH_RSFRAME_ENS_SEC = 1,
397};
398
399enum atscmh_rs_frame_mode {
400 ATSCMH_RSFRAME_PRI_ONLY = 0,
401 ATSCMH_RSFRAME_PRI_SEC = 1,
402 ATSCMH_RSFRAME_RES = 2,
403};
404
405enum atscmh_rs_code_mode {
406 ATSCMH_RSCODE_211_187 = 0,
407 ATSCMH_RSCODE_223_187 = 1,
408 ATSCMH_RSCODE_235_187 = 2,
409 ATSCMH_RSCODE_RES = 3,
410};
411
363 412
364struct dtv_cmds_h { 413struct dtv_cmds_h {
365 char *name; /* A display name for debugging purposes */ 414 char *name; /* A display name for debugging purposes */
diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h
index 0559e2bd38f9..43d9e8d462d4 100644
--- a/include/linux/dvb/version.h
+++ b/include/linux/dvb/version.h
@@ -24,6 +24,6 @@
24#define _DVBVERSION_H_ 24#define _DVBVERSION_H_
25 25
26#define DVB_API_VERSION 5 26#define DVB_API_VERSION 5
27#define DVB_API_VERSION_MINOR 5 27#define DVB_API_VERSION_MINOR 6
28 28
29#endif /*_DVBVERSION_H_*/ 29#endif /*_DVBVERSION_H_*/
diff --git a/include/linux/fixp-arith.h b/include/linux/fixp-arith.h
new file mode 100644
index 000000000000..3089d7382325
--- /dev/null
+++ b/include/linux/fixp-arith.h
@@ -0,0 +1,87 @@
1#ifndef _FIXP_ARITH_H
2#define _FIXP_ARITH_H
3
4/*
5 * Simplistic fixed-point arithmetics.
6 * Hmm, I'm probably duplicating some code :(
7 *
8 * Copyright (c) 2002 Johann Deneux
9 */
10
11/*
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * Should you need to contact me, the author, you can do so by
27 * e-mail - mail your message to <johann.deneux@gmail.com>
28 */
29
30#include <linux/types.h>
31
32/* The type representing fixed-point values */
33typedef s16 fixp_t;
34
35#define FRAC_N 8
36#define FRAC_MASK ((1<<FRAC_N)-1)
37
38/* Not to be used directly. Use fixp_{cos,sin} */
39static const fixp_t cos_table[46] = {
40 0x0100, 0x00FF, 0x00FF, 0x00FE, 0x00FD, 0x00FC, 0x00FA, 0x00F8,
41 0x00F6, 0x00F3, 0x00F0, 0x00ED, 0x00E9, 0x00E6, 0x00E2, 0x00DD,
42 0x00D9, 0x00D4, 0x00CF, 0x00C9, 0x00C4, 0x00BE, 0x00B8, 0x00B1,
43 0x00AB, 0x00A4, 0x009D, 0x0096, 0x008F, 0x0087, 0x0080, 0x0078,
44 0x0070, 0x0068, 0x005F, 0x0057, 0x004F, 0x0046, 0x003D, 0x0035,
45 0x002C, 0x0023, 0x001A, 0x0011, 0x0008, 0x0000
46};
47
48
49/* a: 123 -> 123.0 */
50static inline fixp_t fixp_new(s16 a)
51{
52 return a<<FRAC_N;
53}
54
55/* a: 0xFFFF -> -1.0
56 0x8000 -> 1.0
57 0x0000 -> 0.0
58*/
59static inline fixp_t fixp_new16(s16 a)
60{
61 return ((s32)a)>>(16-FRAC_N);
62}
63
64static inline fixp_t fixp_cos(unsigned int degrees)
65{
66 int quadrant = (degrees / 90) & 3;
67 unsigned int i = degrees % 90;
68
69 if (quadrant == 1 || quadrant == 3)
70 i = 90 - i;
71
72 i >>= 1;
73
74 return (quadrant == 1 || quadrant == 2)? -cos_table[i] : cos_table[i];
75}
76
77static inline fixp_t fixp_sin(unsigned int degrees)
78{
79 return -fixp_cos(degrees + 90);
80}
81
82static inline fixp_t fixp_mult(fixp_t a, fixp_t b)
83{
84 return ((s32)(a*b))>>FRAC_N;
85}
86
87#endif
diff --git a/include/linux/v4l2-dv-timings.h b/include/linux/v4l2-dv-timings.h
new file mode 100644
index 000000000000..9ef8172e5ed0
--- /dev/null
+++ b/include/linux/v4l2-dv-timings.h
@@ -0,0 +1,816 @@
1/*
2 * V4L2 DV timings header.
3 *
4 * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 */
20
21#ifndef _V4L2_DV_TIMINGS_H
22#define _V4L2_DV_TIMINGS_H
23
24#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
25/* Sadly gcc versions older than 4.6 have a bug in how they initialize
26 anonymous unions where they require additional curly brackets.
27 This violates the C1x standard. This workaround adds the curly brackets
28 if needed. */
29#define V4L2_INIT_BT_TIMINGS(_width, args...) \
30 { .bt = { _width , ## args } }
31#else
32#define V4L2_INIT_BT_TIMINGS(_width, args...) \
33 .bt = { _width , ## args }
34#endif
35
36/* CEA-861-E timings (i.e. standard HDTV timings) */
37
38#define V4L2_DV_BT_CEA_640X480P59_94 { \
39 .type = V4L2_DV_BT_656_1120, \
40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
41 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
42 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
43}
44
45#define V4L2_DV_BT_CEA_720X480P59_94 { \
46 .type = V4L2_DV_BT_656_1120, \
47 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
48 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
49 V4L2_DV_BT_STD_CEA861, 0) \
50}
51
52#define V4L2_DV_BT_CEA_720X576P50 { \
53 .type = V4L2_DV_BT_656_1120, \
54 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
55 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
56 V4L2_DV_BT_STD_CEA861, 0) \
57}
58
59#define V4L2_DV_BT_CEA_1280X720P24 { \
60 .type = V4L2_DV_BT_656_1120, \
61 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
62 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
63 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
64 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
65 V4L2_DV_FL_CAN_REDUCE_FPS) \
66}
67
68#define V4L2_DV_BT_CEA_1280X720P25 { \
69 .type = V4L2_DV_BT_656_1120, \
70 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
71 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
72 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
73 V4L2_DV_BT_STD_CEA861, 0) \
74}
75
76#define V4L2_DV_BT_CEA_1280X720P30 { \
77 .type = V4L2_DV_BT_656_1120, \
78 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
79 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
80 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
81 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
82}
83
84#define V4L2_DV_BT_CEA_1280X720P50 { \
85 .type = V4L2_DV_BT_656_1120, \
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
88 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
89 V4L2_DV_BT_STD_CEA861, 0) \
90}
91
92#define V4L2_DV_BT_CEA_1280X720P60 { \
93 .type = V4L2_DV_BT_656_1120, \
94 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
97 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
98}
99
100#define V4L2_DV_BT_CEA_1920X1080P24 { \
101 .type = V4L2_DV_BT_656_1120, \
102 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
103 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
104 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
105 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
106}
107
108#define V4L2_DV_BT_CEA_1920X1080P25 { \
109 .type = V4L2_DV_BT_656_1120, \
110 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
111 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
112 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
113 V4L2_DV_BT_STD_CEA861, 0) \
114}
115
116#define V4L2_DV_BT_CEA_1920X1080P30 { \
117 .type = V4L2_DV_BT_656_1120, \
118 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
119 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
120 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
121 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
122}
123
124#define V4L2_DV_BT_CEA_1920X1080I50 { \
125 .type = V4L2_DV_BT_656_1120, \
126 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
127 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
128 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
129 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
130}
131
132#define V4L2_DV_BT_CEA_1920X1080P50 { \
133 .type = V4L2_DV_BT_656_1120, \
134 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
135 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
136 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
137 V4L2_DV_BT_STD_CEA861, 0) \
138}
139
140#define V4L2_DV_BT_CEA_1920X1080I60 { \
141 .type = V4L2_DV_BT_656_1120, \
142 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
143 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
145 V4L2_DV_BT_STD_CEA861, \
146 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
147}
148
149#define V4L2_DV_BT_CEA_1920X1080P60 { \
150 .type = V4L2_DV_BT_656_1120, \
151 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
152 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
154 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
155 V4L2_DV_FL_CAN_REDUCE_FPS) \
156}
157
158
159/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
160
161#define V4L2_DV_BT_DMT_640X350P85 { \
162 .type = V4L2_DV_BT_656_1120, \
163 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
164 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
165 V4L2_DV_BT_STD_DMT, 0) \
166}
167
168#define V4L2_DV_BT_DMT_640X400P85 { \
169 .type = V4L2_DV_BT_656_1120, \
170 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
171 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
172 V4L2_DV_BT_STD_DMT, 0) \
173}
174
175#define V4L2_DV_BT_DMT_720X400P85 { \
176 .type = V4L2_DV_BT_656_1120, \
177 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
178 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
179 V4L2_DV_BT_STD_DMT, 0) \
180}
181
182/* VGA resolutions */
183#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
184
185#define V4L2_DV_BT_DMT_640X480P72 { \
186 .type = V4L2_DV_BT_656_1120, \
187 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
188 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
189 V4L2_DV_BT_STD_DMT, 0) \
190}
191
192#define V4L2_DV_BT_DMT_640X480P75 { \
193 .type = V4L2_DV_BT_656_1120, \
194 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
195 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
196 V4L2_DV_BT_STD_DMT, 0) \
197}
198
199#define V4L2_DV_BT_DMT_640X480P85 { \
200 .type = V4L2_DV_BT_656_1120, \
201 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
202 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
203 V4L2_DV_BT_STD_DMT, 0) \
204}
205
206/* SVGA resolutions */
207#define V4L2_DV_BT_DMT_800X600P56 { \
208 .type = V4L2_DV_BT_656_1120, \
209 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
210 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
211 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
212 V4L2_DV_BT_STD_DMT, 0) \
213}
214
215#define V4L2_DV_BT_DMT_800X600P60 { \
216 .type = V4L2_DV_BT_656_1120, \
217 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
218 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
219 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
220 V4L2_DV_BT_STD_DMT, 0) \
221}
222
223#define V4L2_DV_BT_DMT_800X600P72 { \
224 .type = V4L2_DV_BT_656_1120, \
225 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
226 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
227 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
228 V4L2_DV_BT_STD_DMT, 0) \
229}
230
231#define V4L2_DV_BT_DMT_800X600P75 { \
232 .type = V4L2_DV_BT_656_1120, \
233 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
234 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
235 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
236 V4L2_DV_BT_STD_DMT, 0) \
237}
238
239#define V4L2_DV_BT_DMT_800X600P85 { \
240 .type = V4L2_DV_BT_656_1120, \
241 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
242 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
243 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
244 V4L2_DV_BT_STD_DMT, 0) \
245}
246
247#define V4L2_DV_BT_DMT_800X600P120_RB { \
248 .type = V4L2_DV_BT_656_1120, \
249 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
250 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
251 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
252 V4L2_DV_FL_REDUCED_BLANKING) \
253}
254
255#define V4L2_DV_BT_DMT_848X480P60 { \
256 .type = V4L2_DV_BT_656_1120, \
257 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
258 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
259 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
260 V4L2_DV_BT_STD_DMT, 0) \
261}
262
263#define V4L2_DV_BT_DMT_1024X768I43 { \
264 .type = V4L2_DV_BT_656_1120, \
265 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
266 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
267 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
268 V4L2_DV_BT_STD_DMT, 0) \
269}
270
271/* XGA resolutions */
272#define V4L2_DV_BT_DMT_1024X768P60 { \
273 .type = V4L2_DV_BT_656_1120, \
274 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
275 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
276 V4L2_DV_BT_STD_DMT, 0) \
277}
278
279#define V4L2_DV_BT_DMT_1024X768P70 { \
280 .type = V4L2_DV_BT_656_1120, \
281 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
282 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
283 V4L2_DV_BT_STD_DMT, 0) \
284}
285
286#define V4L2_DV_BT_DMT_1024X768P75 { \
287 .type = V4L2_DV_BT_656_1120, \
288 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
289 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
290 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
291 V4L2_DV_BT_STD_DMT, 0) \
292}
293
294#define V4L2_DV_BT_DMT_1024X768P85 { \
295 .type = V4L2_DV_BT_656_1120, \
296 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
297 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
298 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
299 V4L2_DV_BT_STD_DMT, 0) \
300}
301
302#define V4L2_DV_BT_DMT_1024X768P120_RB { \
303 .type = V4L2_DV_BT_656_1120, \
304 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
305 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
306 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
307 V4L2_DV_FL_REDUCED_BLANKING) \
308}
309
310/* XGA+ resolution */
311#define V4L2_DV_BT_DMT_1152X864P75 { \
312 .type = V4L2_DV_BT_656_1120, \
313 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
314 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
315 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
316 V4L2_DV_BT_STD_DMT, 0) \
317}
318
319#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
320
321/* WXGA resolutions */
322#define V4L2_DV_BT_DMT_1280X768P60_RB { \
323 .type = V4L2_DV_BT_656_1120, \
324 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
325 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
326 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
327 V4L2_DV_FL_REDUCED_BLANKING) \
328}
329
330#define V4L2_DV_BT_DMT_1280X768P60 { \
331 .type = V4L2_DV_BT_656_1120, \
332 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
333 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
334 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
335}
336
337#define V4L2_DV_BT_DMT_1280X768P75 { \
338 .type = V4L2_DV_BT_656_1120, \
339 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
340 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
341 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
342}
343
344#define V4L2_DV_BT_DMT_1280X768P85 { \
345 .type = V4L2_DV_BT_656_1120, \
346 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
347 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
348 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
349}
350
351#define V4L2_DV_BT_DMT_1280X768P120_RB { \
352 .type = V4L2_DV_BT_656_1120, \
353 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
354 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
355 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
356 V4L2_DV_FL_REDUCED_BLANKING) \
357}
358
359#define V4L2_DV_BT_DMT_1280X800P60_RB { \
360 .type = V4L2_DV_BT_656_1120, \
361 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
362 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
363 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
364 V4L2_DV_FL_REDUCED_BLANKING) \
365}
366
367#define V4L2_DV_BT_DMT_1280X800P60 { \
368 .type = V4L2_DV_BT_656_1120, \
369 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
370 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
371 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
372}
373
374#define V4L2_DV_BT_DMT_1280X800P75 { \
375 .type = V4L2_DV_BT_656_1120, \
376 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
377 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
378 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
379}
380
381#define V4L2_DV_BT_DMT_1280X800P85 { \
382 .type = V4L2_DV_BT_656_1120, \
383 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
384 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
385 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
386}
387
388#define V4L2_DV_BT_DMT_1280X800P120_RB { \
389 .type = V4L2_DV_BT_656_1120, \
390 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
391 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
392 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
393 V4L2_DV_FL_REDUCED_BLANKING) \
394}
395
396#define V4L2_DV_BT_DMT_1280X960P60 { \
397 .type = V4L2_DV_BT_656_1120, \
398 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
399 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
400 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
401 V4L2_DV_BT_STD_DMT, 0) \
402}
403
404#define V4L2_DV_BT_DMT_1280X960P85 { \
405 .type = V4L2_DV_BT_656_1120, \
406 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
407 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
408 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
409 V4L2_DV_BT_STD_DMT, 0) \
410}
411
412#define V4L2_DV_BT_DMT_1280X960P120_RB { \
413 .type = V4L2_DV_BT_656_1120, \
414 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
415 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
416 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
417 V4L2_DV_FL_REDUCED_BLANKING) \
418}
419
420/* SXGA resolutions */
421#define V4L2_DV_BT_DMT_1280X1024P60 { \
422 .type = V4L2_DV_BT_656_1120, \
423 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
424 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
425 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
426 V4L2_DV_BT_STD_DMT, 0) \
427}
428
429#define V4L2_DV_BT_DMT_1280X1024P75 { \
430 .type = V4L2_DV_BT_656_1120, \
431 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
432 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
433 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
434 V4L2_DV_BT_STD_DMT, 0) \
435}
436
437#define V4L2_DV_BT_DMT_1280X1024P85 { \
438 .type = V4L2_DV_BT_656_1120, \
439 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
440 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
441 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
442 V4L2_DV_BT_STD_DMT, 0) \
443}
444
445#define V4L2_DV_BT_DMT_1280X1024P120_RB { \
446 .type = V4L2_DV_BT_656_1120, \
447 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
448 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
449 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
450 V4L2_DV_FL_REDUCED_BLANKING) \
451}
452
453#define V4L2_DV_BT_DMT_1360X768P60 { \
454 .type = V4L2_DV_BT_656_1120, \
455 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
456 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
457 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
458 V4L2_DV_BT_STD_DMT, 0) \
459}
460
461#define V4L2_DV_BT_DMT_1360X768P120_RB { \
462 .type = V4L2_DV_BT_656_1120, \
463 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
464 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
465 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
466 V4L2_DV_FL_REDUCED_BLANKING) \
467}
468
469#define V4L2_DV_BT_DMT_1366X768P60 { \
470 .type = V4L2_DV_BT_656_1120, \
471 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
472 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
473 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
474 V4L2_DV_BT_STD_DMT, 0) \
475}
476
477#define V4L2_DV_BT_DMT_1366X768P60_RB { \
478 .type = V4L2_DV_BT_656_1120, \
479 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
480 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
481 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
482 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
483}
484
485/* SXGA+ resolutions */
486#define V4L2_DV_BT_DMT_1400X1050P60_RB { \
487 .type = V4L2_DV_BT_656_1120, \
488 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
489 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
490 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
491 V4L2_DV_FL_REDUCED_BLANKING) \
492}
493
494#define V4L2_DV_BT_DMT_1400X1050P60 { \
495 .type = V4L2_DV_BT_656_1120, \
496 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
497 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
498 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
499}
500
501#define V4L2_DV_BT_DMT_1400X1050P75 { \
502 .type = V4L2_DV_BT_656_1120, \
503 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
504 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
505 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
506}
507
508#define V4L2_DV_BT_DMT_1400X1050P85 { \
509 .type = V4L2_DV_BT_656_1120, \
510 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
511 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
512 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
513}
514
515#define V4L2_DV_BT_DMT_1400X1050P120_RB { \
516 .type = V4L2_DV_BT_656_1120, \
517 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
518 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
519 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
520 V4L2_DV_FL_REDUCED_BLANKING) \
521}
522
523/* WXGA+ resolutions */
524#define V4L2_DV_BT_DMT_1440X900P60_RB { \
525 .type = V4L2_DV_BT_656_1120, \
526 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
527 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
528 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
529 V4L2_DV_FL_REDUCED_BLANKING) \
530}
531
532#define V4L2_DV_BT_DMT_1440X900P60 { \
533 .type = V4L2_DV_BT_656_1120, \
534 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
535 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
536 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
537}
538
539#define V4L2_DV_BT_DMT_1440X900P75 { \
540 .type = V4L2_DV_BT_656_1120, \
541 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
542 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
543 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
544}
545
546#define V4L2_DV_BT_DMT_1440X900P85 { \
547 .type = V4L2_DV_BT_656_1120, \
548 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
549 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
550 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
551}
552
553#define V4L2_DV_BT_DMT_1440X900P120_RB { \
554 .type = V4L2_DV_BT_656_1120, \
555 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
556 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
557 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
558 V4L2_DV_FL_REDUCED_BLANKING) \
559}
560
561#define V4L2_DV_BT_DMT_1600X900P60_RB { \
562 .type = V4L2_DV_BT_656_1120, \
563 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
564 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
565 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
566 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
567}
568
569/* UXGA resolutions */
570#define V4L2_DV_BT_DMT_1600X1200P60 { \
571 .type = V4L2_DV_BT_656_1120, \
572 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
573 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
574 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
575 V4L2_DV_BT_STD_DMT, 0) \
576}
577
578#define V4L2_DV_BT_DMT_1600X1200P65 { \
579 .type = V4L2_DV_BT_656_1120, \
580 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
581 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
582 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
583 V4L2_DV_BT_STD_DMT, 0) \
584}
585
586#define V4L2_DV_BT_DMT_1600X1200P70 { \
587 .type = V4L2_DV_BT_656_1120, \
588 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
589 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
590 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
591 V4L2_DV_BT_STD_DMT, 0) \
592}
593
594#define V4L2_DV_BT_DMT_1600X1200P75 { \
595 .type = V4L2_DV_BT_656_1120, \
596 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
597 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
598 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
599 V4L2_DV_BT_STD_DMT, 0) \
600}
601
602#define V4L2_DV_BT_DMT_1600X1200P85 { \
603 .type = V4L2_DV_BT_656_1120, \
604 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
605 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
606 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
607 V4L2_DV_BT_STD_DMT, 0) \
608}
609
610#define V4L2_DV_BT_DMT_1600X1200P120_RB { \
611 .type = V4L2_DV_BT_656_1120, \
612 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
613 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
614 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
615 V4L2_DV_FL_REDUCED_BLANKING) \
616}
617
618/* WSXGA+ resolutions */
619#define V4L2_DV_BT_DMT_1680X1050P60_RB { \
620 .type = V4L2_DV_BT_656_1120, \
621 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
622 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
623 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
624 V4L2_DV_FL_REDUCED_BLANKING) \
625}
626
627#define V4L2_DV_BT_DMT_1680X1050P60 { \
628 .type = V4L2_DV_BT_656_1120, \
629 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
630 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
631 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
632}
633
634#define V4L2_DV_BT_DMT_1680X1050P75 { \
635 .type = V4L2_DV_BT_656_1120, \
636 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
637 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
638 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
639}
640
641#define V4L2_DV_BT_DMT_1680X1050P85 { \
642 .type = V4L2_DV_BT_656_1120, \
643 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
644 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
645 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
646}
647
648#define V4L2_DV_BT_DMT_1680X1050P120_RB { \
649 .type = V4L2_DV_BT_656_1120, \
650 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
651 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
652 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
653 V4L2_DV_FL_REDUCED_BLANKING) \
654}
655
656#define V4L2_DV_BT_DMT_1792X1344P60 { \
657 .type = V4L2_DV_BT_656_1120, \
658 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
659 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
660 V4L2_DV_BT_STD_DMT, 0) \
661}
662
663#define V4L2_DV_BT_DMT_1792X1344P75 { \
664 .type = V4L2_DV_BT_656_1120, \
665 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
666 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
667 V4L2_DV_BT_STD_DMT, 0) \
668}
669
670#define V4L2_DV_BT_DMT_1792X1344P120_RB { \
671 .type = V4L2_DV_BT_656_1120, \
672 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
673 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
674 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
675 V4L2_DV_FL_REDUCED_BLANKING) \
676}
677
678#define V4L2_DV_BT_DMT_1856X1392P60 { \
679 .type = V4L2_DV_BT_656_1120, \
680 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
681 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
682 V4L2_DV_BT_STD_DMT, 0) \
683}
684
685#define V4L2_DV_BT_DMT_1856X1392P75 { \
686 .type = V4L2_DV_BT_656_1120, \
687 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
688 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
689 V4L2_DV_BT_STD_DMT, 0) \
690}
691
692#define V4L2_DV_BT_DMT_1856X1392P120_RB { \
693 .type = V4L2_DV_BT_656_1120, \
694 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
695 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
696 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
697 V4L2_DV_FL_REDUCED_BLANKING) \
698}
699
700#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
701
702/* WUXGA resolutions */
703#define V4L2_DV_BT_DMT_1920X1200P60_RB { \
704 .type = V4L2_DV_BT_656_1120, \
705 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
706 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
707 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
708 V4L2_DV_FL_REDUCED_BLANKING) \
709}
710
711#define V4L2_DV_BT_DMT_1920X1200P60 { \
712 .type = V4L2_DV_BT_656_1120, \
713 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
714 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
715 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
716}
717
718#define V4L2_DV_BT_DMT_1920X1200P75 { \
719 .type = V4L2_DV_BT_656_1120, \
720 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
721 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
722 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
723}
724
725#define V4L2_DV_BT_DMT_1920X1200P85 { \
726 .type = V4L2_DV_BT_656_1120, \
727 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
728 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
729 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
730}
731
732#define V4L2_DV_BT_DMT_1920X1200P120_RB { \
733 .type = V4L2_DV_BT_656_1120, \
734 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
735 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
736 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
737 V4L2_DV_FL_REDUCED_BLANKING) \
738}
739
740#define V4L2_DV_BT_DMT_1920X1440P60 { \
741 .type = V4L2_DV_BT_656_1120, \
742 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
743 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
744 V4L2_DV_BT_STD_DMT, 0) \
745}
746
747#define V4L2_DV_BT_DMT_1920X1440P75 { \
748 .type = V4L2_DV_BT_656_1120, \
749 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
750 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
751 V4L2_DV_BT_STD_DMT, 0) \
752}
753
754#define V4L2_DV_BT_DMT_1920X1440P120_RB { \
755 .type = V4L2_DV_BT_656_1120, \
756 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
757 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
758 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
759 V4L2_DV_FL_REDUCED_BLANKING) \
760}
761
762#define V4L2_DV_BT_DMT_2048X1152P60_RB { \
763 .type = V4L2_DV_BT_656_1120, \
764 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
765 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
766 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
767 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
768}
769
770/* WQXGA resolutions */
771#define V4L2_DV_BT_DMT_2560X1600P60_RB { \
772 .type = V4L2_DV_BT_656_1120, \
773 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
774 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
775 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
776 V4L2_DV_FL_REDUCED_BLANKING) \
777}
778
779#define V4L2_DV_BT_DMT_2560X1600P60 { \
780 .type = V4L2_DV_BT_656_1120, \
781 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
782 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
783 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
784}
785
786#define V4L2_DV_BT_DMT_2560X1600P75 { \
787 .type = V4L2_DV_BT_656_1120, \
788 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
789 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
790 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
791}
792
793#define V4L2_DV_BT_DMT_2560X1600P85 { \
794 .type = V4L2_DV_BT_656_1120, \
795 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
796 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
797 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
798}
799
800#define V4L2_DV_BT_DMT_2560X1600P120_RB { \
801 .type = V4L2_DV_BT_656_1120, \
802 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
803 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
804 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
805 V4L2_DV_FL_REDUCED_BLANKING) \
806}
807
808#define V4L2_DV_BT_DMT_1366X768P60 { \
809 .type = V4L2_DV_BT_656_1120, \
810 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
811 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
812 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
813 V4L2_DV_BT_STD_DMT, 0) \
814}
815
816#endif
diff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h
index ed29cbbebfef..812019ee1e06 100644
--- a/include/linux/v4l2-subdev.h
+++ b/include/linux/v4l2-subdev.h
@@ -123,6 +123,43 @@ struct v4l2_subdev_frame_interval_enum {
123 __u32 reserved[9]; 123 __u32 reserved[9];
124}; 124};
125 125
126#define V4L2_SUBDEV_SEL_FLAG_SIZE_GE (1 << 0)
127#define V4L2_SUBDEV_SEL_FLAG_SIZE_LE (1 << 1)
128#define V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG (1 << 2)
129
130/* active cropping area */
131#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL 0x0000
132/* cropping bounds */
133#define V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS 0x0002
134/* current composing area */
135#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL 0x0100
136/* composing bounds */
137#define V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS 0x0102
138
139
140/**
141 * struct v4l2_subdev_selection - selection info
142 *
143 * @which: either V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY
144 * @pad: pad number, as reported by the media API
145 * @target: selection target, used to choose one of possible rectangles
146 * @flags: constraint flags
147 * @r: coordinates of the selection window
148 * @reserved: for future use, set to zero for now
149 *
150 * Hardware may use multiple helper windows to process a video stream.
151 * The structure is used to exchange this selection areas between
152 * an application and a driver.
153 */
154struct v4l2_subdev_selection {
155 __u32 which;
156 __u32 pad;
157 __u32 target;
158 __u32 flags;
159 struct v4l2_rect r;
160 __u32 reserved[8];
161};
162
126#define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format) 163#define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format)
127#define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format) 164#define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format)
128#define VIDIOC_SUBDEV_G_FRAME_INTERVAL \ 165#define VIDIOC_SUBDEV_G_FRAME_INTERVAL \
@@ -137,5 +174,9 @@ struct v4l2_subdev_frame_interval_enum {
137 _IOWR('V', 75, struct v4l2_subdev_frame_interval_enum) 174 _IOWR('V', 75, struct v4l2_subdev_frame_interval_enum)
138#define VIDIOC_SUBDEV_G_CROP _IOWR('V', 59, struct v4l2_subdev_crop) 175#define VIDIOC_SUBDEV_G_CROP _IOWR('V', 59, struct v4l2_subdev_crop)
139#define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop) 176#define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop)
177#define VIDIOC_SUBDEV_G_SELECTION \
178 _IOWR('V', 61, struct v4l2_subdev_selection)
179#define VIDIOC_SUBDEV_S_SELECTION \
180 _IOWR('V', 62, struct v4l2_subdev_selection)
140 181
141#endif 182#endif
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index c9c9a4680cc5..370d11106c11 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -292,10 +292,10 @@ struct v4l2_pix_format {
292 __u32 width; 292 __u32 width;
293 __u32 height; 293 __u32 height;
294 __u32 pixelformat; 294 __u32 pixelformat;
295 enum v4l2_field field; 295 __u32 field; /* enum v4l2_field */
296 __u32 bytesperline; /* for padding, zero if unused */ 296 __u32 bytesperline; /* for padding, zero if unused */
297 __u32 sizeimage; 297 __u32 sizeimage;
298 enum v4l2_colorspace colorspace; 298 __u32 colorspace; /* enum v4l2_colorspace */
299 __u32 priv; /* private data, depends on pixelformat */ 299 __u32 priv; /* private data, depends on pixelformat */
300}; 300};
301 301
@@ -378,7 +378,10 @@ struct v4l2_pix_format {
378#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ 378#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */
379#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ 379#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */
380 /* 10bit raw bayer DPCM compressed to 8 bits */ 380 /* 10bit raw bayer DPCM compressed to 8 bits */
381#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8')
382#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8')
381#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') 383#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
384#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8')
382 /* 385 /*
383 * 10bit raw bayer, expanded to 16 bits 386 * 10bit raw bayer, expanded to 16 bits
384 * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb... 387 * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb...
@@ -432,7 +435,7 @@ struct v4l2_pix_format {
432 */ 435 */
433struct v4l2_fmtdesc { 436struct v4l2_fmtdesc {
434 __u32 index; /* Format number */ 437 __u32 index; /* Format number */
435 enum v4l2_buf_type type; /* buffer type */ 438 __u32 type; /* enum v4l2_buf_type */
436 __u32 flags; 439 __u32 flags;
437 __u8 description[32]; /* Description string */ 440 __u8 description[32]; /* Description string */
438 __u32 pixelformat; /* Format fourcc */ 441 __u32 pixelformat; /* Format fourcc */
@@ -573,8 +576,8 @@ struct v4l2_jpegcompression {
573 */ 576 */
574struct v4l2_requestbuffers { 577struct v4l2_requestbuffers {
575 __u32 count; 578 __u32 count;
576 enum v4l2_buf_type type; 579 __u32 type; /* enum v4l2_buf_type */
577 enum v4l2_memory memory; 580 __u32 memory; /* enum v4l2_memory */
578 __u32 reserved[2]; 581 __u32 reserved[2];
579}; 582};
580 583
@@ -610,15 +613,17 @@ struct v4l2_plane {
610/** 613/**
611 * struct v4l2_buffer - video buffer info 614 * struct v4l2_buffer - video buffer info
612 * @index: id number of the buffer 615 * @index: id number of the buffer
613 * @type: buffer type (type == *_MPLANE for multiplanar buffers) 616 * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for
617 * multiplanar buffers);
614 * @bytesused: number of bytes occupied by data in the buffer (payload); 618 * @bytesused: number of bytes occupied by data in the buffer (payload);
615 * unused (set to 0) for multiplanar buffers 619 * unused (set to 0) for multiplanar buffers
616 * @flags: buffer informational flags 620 * @flags: buffer informational flags
617 * @field: field order of the image in the buffer 621 * @field: enum v4l2_field; field order of the image in the buffer
618 * @timestamp: frame timestamp 622 * @timestamp: frame timestamp
619 * @timecode: frame timecode 623 * @timecode: frame timecode
620 * @sequence: sequence count of this frame 624 * @sequence: sequence count of this frame
621 * @memory: the method, in which the actual video data is passed 625 * @memory: enum v4l2_memory; the method, in which the actual video data is
626 * passed
622 * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP; 627 * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP;
623 * offset from the start of the device memory for this plane, 628 * offset from the start of the device memory for this plane,
624 * (or a "cookie" that should be passed to mmap() as offset) 629 * (or a "cookie" that should be passed to mmap() as offset)
@@ -636,16 +641,16 @@ struct v4l2_plane {
636 */ 641 */
637struct v4l2_buffer { 642struct v4l2_buffer {
638 __u32 index; 643 __u32 index;
639 enum v4l2_buf_type type; 644 __u32 type;
640 __u32 bytesused; 645 __u32 bytesused;
641 __u32 flags; 646 __u32 flags;
642 enum v4l2_field field; 647 __u32 field;
643 struct timeval timestamp; 648 struct timeval timestamp;
644 struct v4l2_timecode timecode; 649 struct v4l2_timecode timecode;
645 __u32 sequence; 650 __u32 sequence;
646 651
647 /* memory location */ 652 /* memory location */
648 enum v4l2_memory memory; 653 __u32 memory;
649 union { 654 union {
650 __u32 offset; 655 __u32 offset;
651 unsigned long userptr; 656 unsigned long userptr;
@@ -708,7 +713,7 @@ struct v4l2_clip {
708 713
709struct v4l2_window { 714struct v4l2_window {
710 struct v4l2_rect w; 715 struct v4l2_rect w;
711 enum v4l2_field field; 716 __u32 field; /* enum v4l2_field */
712 __u32 chromakey; 717 __u32 chromakey;
713 struct v4l2_clip __user *clips; 718 struct v4l2_clip __user *clips;
714 __u32 clipcount; 719 __u32 clipcount;
@@ -745,14 +750,14 @@ struct v4l2_outputparm {
745 * I N P U T I M A G E C R O P P I N G 750 * I N P U T I M A G E C R O P P I N G
746 */ 751 */
747struct v4l2_cropcap { 752struct v4l2_cropcap {
748 enum v4l2_buf_type type; 753 __u32 type; /* enum v4l2_buf_type */
749 struct v4l2_rect bounds; 754 struct v4l2_rect bounds;
750 struct v4l2_rect defrect; 755 struct v4l2_rect defrect;
751 struct v4l2_fract pixelaspect; 756 struct v4l2_fract pixelaspect;
752}; 757};
753 758
754struct v4l2_crop { 759struct v4l2_crop {
755 enum v4l2_buf_type type; 760 __u32 type; /* enum v4l2_buf_type */
756 struct v4l2_rect c; 761 struct v4l2_rect c;
757}; 762};
758 763
@@ -939,6 +944,9 @@ struct v4l2_standard {
939 __u32 reserved[4]; 944 __u32 reserved[4];
940}; 945};
941 946
947/* The DV Preset API is deprecated in favor of the DV Timings API.
948 New drivers shouldn't use this anymore! */
949
942/* 950/*
943 * V I D E O T I M I N G S D V P R E S E T 951 * V I D E O T I M I N G S D V P R E S E T
944 */ 952 */
@@ -986,29 +994,56 @@ struct v4l2_dv_enum_preset {
986 * D V B T T I M I N G S 994 * D V B T T I M I N G S
987 */ 995 */
988 996
989/* BT.656/BT.1120 timing data */ 997/** struct v4l2_bt_timings - BT.656/BT.1120 timing data
998 * @width: total width of the active video in pixels
999 * @height: total height of the active video in lines
1000 * @interlaced: Interlaced or progressive
1001 * @polarities: Positive or negative polarities
1002 * @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
1003 * @hfrontporch:Horizontal front porch in pixels
1004 * @hsync: Horizontal Sync length in pixels
1005 * @hbackporch: Horizontal back porch in pixels
1006 * @vfrontporch:Vertical front porch in lines
1007 * @vsync: Vertical Sync length in lines
1008 * @vbackporch: Vertical back porch in lines
1009 * @il_vfrontporch:Vertical front porch for the even field
1010 * (aka field 2) of interlaced field formats
1011 * @il_vsync: Vertical Sync length for the even field
1012 * (aka field 2) of interlaced field formats
1013 * @il_vbackporch:Vertical back porch for the even field
1014 * (aka field 2) of interlaced field formats
1015 * @standards: Standards the timing belongs to
1016 * @flags: Flags
1017 * @reserved: Reserved fields, must be zeroed.
1018 *
1019 * A note regarding vertical interlaced timings: height refers to the total
1020 * height of the active video frame (= two fields). The blanking timings refer
1021 * to the blanking of each field. So the height of the total frame is
1022 * calculated as follows:
1023 *
1024 * tot_height = height + vfrontporch + vsync + vbackporch +
1025 * il_vfrontporch + il_vsync + il_vbackporch
1026 *
1027 * The active height of each field is height / 2.
1028 */
990struct v4l2_bt_timings { 1029struct v4l2_bt_timings {
991 __u32 width; /* width in pixels */ 1030 __u32 width;
992 __u32 height; /* height in lines */ 1031 __u32 height;
993 __u32 interlaced; /* Interlaced or progressive */ 1032 __u32 interlaced;
994 __u32 polarities; /* Positive or negative polarity */ 1033 __u32 polarities;
995 __u64 pixelclock; /* Pixel clock in HZ. Ex. 74.25MHz->74250000 */ 1034 __u64 pixelclock;
996 __u32 hfrontporch; /* Horizpontal front porch in pixels */ 1035 __u32 hfrontporch;
997 __u32 hsync; /* Horizontal Sync length in pixels */ 1036 __u32 hsync;
998 __u32 hbackporch; /* Horizontal back porch in pixels */ 1037 __u32 hbackporch;
999 __u32 vfrontporch; /* Vertical front porch in pixels */ 1038 __u32 vfrontporch;
1000 __u32 vsync; /* Vertical Sync length in lines */ 1039 __u32 vsync;
1001 __u32 vbackporch; /* Vertical back porch in lines */ 1040 __u32 vbackporch;
1002 __u32 il_vfrontporch; /* Vertical front porch for bottom field of 1041 __u32 il_vfrontporch;
1003 * interlaced field formats 1042 __u32 il_vsync;
1004 */ 1043 __u32 il_vbackporch;
1005 __u32 il_vsync; /* Vertical sync length for bottom field of 1044 __u32 standards;
1006 * interlaced field formats 1045 __u32 flags;
1007 */ 1046 __u32 reserved[14];
1008 __u32 il_vbackporch; /* Vertical back porch for bottom field of
1009 * interlaced field formats
1010 */
1011 __u32 reserved[16];
1012} __attribute__ ((packed)); 1047} __attribute__ ((packed));
1013 1048
1014/* Interlaced or progressive format */ 1049/* Interlaced or progressive format */
@@ -1019,8 +1054,42 @@ struct v4l2_bt_timings {
1019#define V4L2_DV_VSYNC_POS_POL 0x00000001 1054#define V4L2_DV_VSYNC_POS_POL 0x00000001
1020#define V4L2_DV_HSYNC_POS_POL 0x00000002 1055#define V4L2_DV_HSYNC_POS_POL 0x00000002
1021 1056
1022 1057/* Timings standards */
1023/* DV timings */ 1058#define V4L2_DV_BT_STD_CEA861 (1 << 0) /* CEA-861 Digital TV Profile */
1059#define V4L2_DV_BT_STD_DMT (1 << 1) /* VESA Discrete Monitor Timings */
1060#define V4L2_DV_BT_STD_CVT (1 << 2) /* VESA Coordinated Video Timings */
1061#define V4L2_DV_BT_STD_GTF (1 << 3) /* VESA Generalized Timings Formula */
1062
1063/* Flags */
1064
1065/* CVT/GTF specific: timing uses reduced blanking (CVT) or the 'Secondary
1066 GTF' curve (GTF). In both cases the horizontal and/or vertical blanking
1067 intervals are reduced, allowing a higher resolution over the same
1068 bandwidth. This is a read-only flag. */
1069#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0)
1070/* CEA-861 specific: set for CEA-861 formats with a framerate of a multiple
1071 of six. These formats can be optionally played at 1 / 1.001 speed.
1072 This is a read-only flag. */
1073#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1)
1074/* CEA-861 specific: only valid for video transmitters, the flag is cleared
1075 by receivers.
1076 If the framerate of the format is a multiple of six, then the pixelclock
1077 used to set up the transmitter is divided by 1.001 to make it compatible
1078 with 60 Hz based standards such as NTSC and PAL-M that use a framerate of
1079 29.97 Hz. Otherwise this flag is cleared. If the transmitter can't generate
1080 such frequencies, then the flag will also be cleared. */
1081#define V4L2_DV_FL_REDUCED_FPS (1 << 2)
1082/* Specific to interlaced formats: if set, then field 1 is really one half-line
1083 longer and field 2 is really one half-line shorter, so each field has
1084 exactly the same number of half-lines. Whether half-lines can be detected
1085 or used depends on the hardware. */
1086#define V4L2_DV_FL_HALF_LINE (1 << 0)
1087
1088
1089/** struct v4l2_dv_timings - DV timings
1090 * @type: the type of the timings
1091 * @bt: BT656/1120 timings
1092 */
1024struct v4l2_dv_timings { 1093struct v4l2_dv_timings {
1025 __u32 type; 1094 __u32 type;
1026 union { 1095 union {
@@ -1032,6 +1101,64 @@ struct v4l2_dv_timings {
1032/* Values for the type field */ 1101/* Values for the type field */
1033#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ 1102#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */
1034 1103
1104
1105/** struct v4l2_enum_dv_timings - DV timings enumeration
1106 * @index: enumeration index
1107 * @reserved: must be zeroed
1108 * @timings: the timings for the given index
1109 */
1110struct v4l2_enum_dv_timings {
1111 __u32 index;
1112 __u32 reserved[3];
1113 struct v4l2_dv_timings timings;
1114};
1115
1116/** struct v4l2_bt_timings_cap - BT.656/BT.1120 timing capabilities
1117 * @min_width: width in pixels
1118 * @max_width: width in pixels
1119 * @min_height: height in lines
1120 * @max_height: height in lines
1121 * @min_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
1122 * @max_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
1123 * @standards: Supported standards
1124 * @capabilities: Supported capabilities
1125 * @reserved: Must be zeroed
1126 */
1127struct v4l2_bt_timings_cap {
1128 __u32 min_width;
1129 __u32 max_width;
1130 __u32 min_height;
1131 __u32 max_height;
1132 __u64 min_pixelclock;
1133 __u64 max_pixelclock;
1134 __u32 standards;
1135 __u32 capabilities;
1136 __u32 reserved[16];
1137} __attribute__ ((packed));
1138
1139/* Supports interlaced formats */
1140#define V4L2_DV_BT_CAP_INTERLACED (1 << 0)
1141/* Supports progressive formats */
1142#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1)
1143/* Supports CVT/GTF reduced blanking */
1144#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2)
1145/* Supports custom formats */
1146#define V4L2_DV_BT_CAP_CUSTOM (1 << 3)
1147
1148/** struct v4l2_dv_timings_cap - DV timings capabilities
1149 * @type: the type of the timings (same as in struct v4l2_dv_timings)
1150 * @bt: the BT656/1120 timings capabilities
1151 */
1152struct v4l2_dv_timings_cap {
1153 __u32 type;
1154 __u32 reserved[3];
1155 union {
1156 struct v4l2_bt_timings_cap bt;
1157 __u32 raw_data[32];
1158 };
1159};
1160
1161
1035/* 1162/*
1036 * V I D E O I N P U T S 1163 * V I D E O I N P U T S
1037 */ 1164 */
@@ -1040,7 +1167,7 @@ struct v4l2_input {
1040 __u8 name[32]; /* Label */ 1167 __u8 name[32]; /* Label */
1041 __u32 type; /* Type of input */ 1168 __u32 type; /* Type of input */
1042 __u32 audioset; /* Associated audios (bitfield) */ 1169 __u32 audioset; /* Associated audios (bitfield) */
1043 __u32 tuner; /* Associated tuner */ 1170 __u32 tuner; /* enum v4l2_tuner_type */
1044 v4l2_std_id std; 1171 v4l2_std_id std;
1045 __u32 status; 1172 __u32 status;
1046 __u32 capabilities; 1173 __u32 capabilities;
@@ -1137,6 +1264,8 @@ struct v4l2_ext_controls {
1137#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ 1264#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */
1138#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ 1265#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
1139#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ 1266#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */
1267#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */
1268#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */
1140 1269
1141#define V4L2_CTRL_ID_MASK (0x0fffffff) 1270#define V4L2_CTRL_ID_MASK (0x0fffffff)
1142#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) 1271#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)
@@ -1151,12 +1280,13 @@ enum v4l2_ctrl_type {
1151 V4L2_CTRL_TYPE_CTRL_CLASS = 6, 1280 V4L2_CTRL_TYPE_CTRL_CLASS = 6,
1152 V4L2_CTRL_TYPE_STRING = 7, 1281 V4L2_CTRL_TYPE_STRING = 7,
1153 V4L2_CTRL_TYPE_BITMASK = 8, 1282 V4L2_CTRL_TYPE_BITMASK = 8,
1283 V4L2_CTRL_TYPE_INTEGER_MENU = 9,
1154}; 1284};
1155 1285
1156/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ 1286/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
1157struct v4l2_queryctrl { 1287struct v4l2_queryctrl {
1158 __u32 id; 1288 __u32 id;
1159 enum v4l2_ctrl_type type; 1289 __u32 type; /* enum v4l2_ctrl_type */
1160 __u8 name[32]; /* Whatever */ 1290 __u8 name[32]; /* Whatever */
1161 __s32 minimum; /* Note signedness */ 1291 __s32 minimum; /* Note signedness */
1162 __s32 maximum; 1292 __s32 maximum;
@@ -1170,9 +1300,12 @@ struct v4l2_queryctrl {
1170struct v4l2_querymenu { 1300struct v4l2_querymenu {
1171 __u32 id; 1301 __u32 id;
1172 __u32 index; 1302 __u32 index;
1173 __u8 name[32]; /* Whatever */ 1303 union {
1304 __u8 name[32]; /* Whatever */
1305 __s64 value;
1306 };
1174 __u32 reserved; 1307 __u32 reserved;
1175}; 1308} __attribute__ ((packed));
1176 1309
1177/* Control flags */ 1310/* Control flags */
1178#define V4L2_CTRL_FLAG_DISABLED 0x0001 1311#define V4L2_CTRL_FLAG_DISABLED 0x0001
@@ -1237,16 +1370,22 @@ enum v4l2_power_line_frequency {
1237#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) 1370#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30)
1238#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) 1371#define V4L2_CID_COLORFX (V4L2_CID_BASE+31)
1239enum v4l2_colorfx { 1372enum v4l2_colorfx {
1240 V4L2_COLORFX_NONE = 0, 1373 V4L2_COLORFX_NONE = 0,
1241 V4L2_COLORFX_BW = 1, 1374 V4L2_COLORFX_BW = 1,
1242 V4L2_COLORFX_SEPIA = 2, 1375 V4L2_COLORFX_SEPIA = 2,
1243 V4L2_COLORFX_NEGATIVE = 3, 1376 V4L2_COLORFX_NEGATIVE = 3,
1244 V4L2_COLORFX_EMBOSS = 4, 1377 V4L2_COLORFX_EMBOSS = 4,
1245 V4L2_COLORFX_SKETCH = 5, 1378 V4L2_COLORFX_SKETCH = 5,
1246 V4L2_COLORFX_SKY_BLUE = 6, 1379 V4L2_COLORFX_SKY_BLUE = 6,
1247 V4L2_COLORFX_GRASS_GREEN = 7, 1380 V4L2_COLORFX_GRASS_GREEN = 7,
1248 V4L2_COLORFX_SKIN_WHITEN = 8, 1381 V4L2_COLORFX_SKIN_WHITEN = 8,
1249 V4L2_COLORFX_VIVID = 9, 1382 V4L2_COLORFX_VIVID = 9,
1383 V4L2_COLORFX_AQUA = 10,
1384 V4L2_COLORFX_ART_FREEZE = 11,
1385 V4L2_COLORFX_SILHOUETTE = 12,
1386 V4L2_COLORFX_SOLARIZATION = 13,
1387 V4L2_COLORFX_ANTIQUE = 14,
1388 V4L2_COLORFX_SET_CBCR = 15,
1250}; 1389};
1251#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) 1390#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32)
1252#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) 1391#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33)
@@ -1263,9 +1402,10 @@ enum v4l2_colorfx {
1263#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) 1402#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40)
1264 1403
1265#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) 1404#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41)
1405#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42)
1266 1406
1267/* last CID + 1 */ 1407/* last CID + 1 */
1268#define V4L2_CID_LASTP1 (V4L2_CID_BASE+42) 1408#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43)
1269 1409
1270/* MPEG-class control IDs defined by V4L2 */ 1410/* MPEG-class control IDs defined by V4L2 */
1271#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) 1411#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
@@ -1689,6 +1829,78 @@ enum v4l2_exposure_auto_type {
1689#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) 1829#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17)
1690#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) 1830#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18)
1691 1831
1832#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19)
1833
1834#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20)
1835enum v4l2_auto_n_preset_white_balance {
1836 V4L2_WHITE_BALANCE_MANUAL = 0,
1837 V4L2_WHITE_BALANCE_AUTO = 1,
1838 V4L2_WHITE_BALANCE_INCANDESCENT = 2,
1839 V4L2_WHITE_BALANCE_FLUORESCENT = 3,
1840 V4L2_WHITE_BALANCE_FLUORESCENT_H = 4,
1841 V4L2_WHITE_BALANCE_HORIZON = 5,
1842 V4L2_WHITE_BALANCE_DAYLIGHT = 6,
1843 V4L2_WHITE_BALANCE_FLASH = 7,
1844 V4L2_WHITE_BALANCE_CLOUDY = 8,
1845 V4L2_WHITE_BALANCE_SHADE = 9,
1846};
1847
1848#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21)
1849#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22)
1850
1851#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23)
1852#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24)
1853enum v4l2_iso_sensitivity_auto_type {
1854 V4L2_ISO_SENSITIVITY_MANUAL = 0,
1855 V4L2_ISO_SENSITIVITY_AUTO = 1,
1856};
1857
1858#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25)
1859enum v4l2_exposure_metering {
1860 V4L2_EXPOSURE_METERING_AVERAGE = 0,
1861 V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1,
1862 V4L2_EXPOSURE_METERING_SPOT = 2,
1863};
1864
1865#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26)
1866enum v4l2_scene_mode {
1867 V4L2_SCENE_MODE_NONE = 0,
1868 V4L2_SCENE_MODE_BACKLIGHT = 1,
1869 V4L2_SCENE_MODE_BEACH_SNOW = 2,
1870 V4L2_SCENE_MODE_CANDLE_LIGHT = 3,
1871 V4L2_SCENE_MODE_DAWN_DUSK = 4,
1872 V4L2_SCENE_MODE_FALL_COLORS = 5,
1873 V4L2_SCENE_MODE_FIREWORKS = 6,
1874 V4L2_SCENE_MODE_LANDSCAPE = 7,
1875 V4L2_SCENE_MODE_NIGHT = 8,
1876 V4L2_SCENE_MODE_PARTY_INDOOR = 9,
1877 V4L2_SCENE_MODE_PORTRAIT = 10,
1878 V4L2_SCENE_MODE_SPORTS = 11,
1879 V4L2_SCENE_MODE_SUNSET = 12,
1880 V4L2_SCENE_MODE_TEXT = 13,
1881};
1882
1883#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27)
1884#define V4L2_LOCK_EXPOSURE (1 << 0)
1885#define V4L2_LOCK_WHITE_BALANCE (1 << 1)
1886#define V4L2_LOCK_FOCUS (1 << 2)
1887
1888#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28)
1889#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29)
1890#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30)
1891#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0)
1892#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0)
1893#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1)
1894#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2)
1895
1896#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31)
1897enum v4l2_auto_focus_range {
1898 V4L2_AUTO_FOCUS_RANGE_AUTO = 0,
1899 V4L2_AUTO_FOCUS_RANGE_NORMAL = 1,
1900 V4L2_AUTO_FOCUS_RANGE_MACRO = 2,
1901 V4L2_AUTO_FOCUS_RANGE_INFINITY = 3,
1902};
1903
1692/* FM Modulator class control IDs */ 1904/* FM Modulator class control IDs */
1693#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) 1905#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900)
1694#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) 1906#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1)
@@ -1782,13 +1994,28 @@ enum v4l2_jpeg_chroma_subsampling {
1782#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) 1994#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
1783#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) 1995#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
1784 1996
1997/* Image source controls */
1998#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
1999#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1)
2000
2001#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1)
2002#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2)
2003#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3)
2004
2005/* Image processing controls */
2006#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900)
2007#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1)
2008
2009#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1)
2010#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2)
2011
1785/* 2012/*
1786 * T U N I N G 2013 * T U N I N G
1787 */ 2014 */
1788struct v4l2_tuner { 2015struct v4l2_tuner {
1789 __u32 index; 2016 __u32 index;
1790 __u8 name[32]; 2017 __u8 name[32];
1791 enum v4l2_tuner_type type; 2018 __u32 type; /* enum v4l2_tuner_type */
1792 __u32 capability; 2019 __u32 capability;
1793 __u32 rangelow; 2020 __u32 rangelow;
1794 __u32 rangehigh; 2021 __u32 rangehigh;
@@ -1838,14 +2065,14 @@ struct v4l2_modulator {
1838 2065
1839struct v4l2_frequency { 2066struct v4l2_frequency {
1840 __u32 tuner; 2067 __u32 tuner;
1841 enum v4l2_tuner_type type; 2068 __u32 type; /* enum v4l2_tuner_type */
1842 __u32 frequency; 2069 __u32 frequency;
1843 __u32 reserved[8]; 2070 __u32 reserved[8];
1844}; 2071};
1845 2072
1846struct v4l2_hw_freq_seek { 2073struct v4l2_hw_freq_seek {
1847 __u32 tuner; 2074 __u32 tuner;
1848 enum v4l2_tuner_type type; 2075 __u32 type; /* enum v4l2_tuner_type */
1849 __u32 seek_upward; 2076 __u32 seek_upward;
1850 __u32 wrap_around; 2077 __u32 wrap_around;
1851 __u32 spacing; 2078 __u32 spacing;
@@ -2056,7 +2283,7 @@ struct v4l2_sliced_vbi_cap {
2056 (equals frame lines 313-336 for 625 line video 2283 (equals frame lines 313-336 for 625 line video
2057 standards, 263-286 for 525 line standards) */ 2284 standards, 263-286 for 525 line standards) */
2058 __u16 service_lines[2][24]; 2285 __u16 service_lines[2][24];
2059 enum v4l2_buf_type type; 2286 __u32 type; /* enum v4l2_buf_type */
2060 __u32 reserved[3]; /* must be 0 */ 2287 __u32 reserved[3]; /* must be 0 */
2061}; 2288};
2062 2289
@@ -2137,8 +2364,8 @@ struct v4l2_plane_pix_format {
2137 * @width: image width in pixels 2364 * @width: image width in pixels
2138 * @height: image height in pixels 2365 * @height: image height in pixels
2139 * @pixelformat: little endian four character code (fourcc) 2366 * @pixelformat: little endian four character code (fourcc)
2140 * @field: field order (for interlaced video) 2367 * @field: enum v4l2_field; field order (for interlaced video)
2141 * @colorspace: supplemental to pixelformat 2368 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
2142 * @plane_fmt: per-plane information 2369 * @plane_fmt: per-plane information
2143 * @num_planes: number of planes for this format 2370 * @num_planes: number of planes for this format
2144 */ 2371 */
@@ -2146,8 +2373,8 @@ struct v4l2_pix_format_mplane {
2146 __u32 width; 2373 __u32 width;
2147 __u32 height; 2374 __u32 height;
2148 __u32 pixelformat; 2375 __u32 pixelformat;
2149 enum v4l2_field field; 2376 __u32 field;
2150 enum v4l2_colorspace colorspace; 2377 __u32 colorspace;
2151 2378
2152 struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; 2379 struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES];
2153 __u8 num_planes; 2380 __u8 num_planes;
@@ -2156,7 +2383,7 @@ struct v4l2_pix_format_mplane {
2156 2383
2157/** 2384/**
2158 * struct v4l2_format - stream data format 2385 * struct v4l2_format - stream data format
2159 * @type: type of the data stream 2386 * @type: enum v4l2_buf_type; type of the data stream
2160 * @pix: definition of an image format 2387 * @pix: definition of an image format
2161 * @pix_mp: definition of a multiplanar image format 2388 * @pix_mp: definition of a multiplanar image format
2162 * @win: definition of an overlaid image 2389 * @win: definition of an overlaid image
@@ -2165,7 +2392,7 @@ struct v4l2_pix_format_mplane {
2165 * @raw_data: placeholder for future extensions and custom formats 2392 * @raw_data: placeholder for future extensions and custom formats
2166 */ 2393 */
2167struct v4l2_format { 2394struct v4l2_format {
2168 enum v4l2_buf_type type; 2395 __u32 type;
2169 union { 2396 union {
2170 struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ 2397 struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */
2171 struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */ 2398 struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */
@@ -2179,7 +2406,7 @@ struct v4l2_format {
2179/* Stream type-dependent parameters 2406/* Stream type-dependent parameters
2180 */ 2407 */
2181struct v4l2_streamparm { 2408struct v4l2_streamparm {
2182 enum v4l2_buf_type type; 2409 __u32 type; /* enum v4l2_buf_type */
2183 union { 2410 union {
2184 struct v4l2_captureparm capture; 2411 struct v4l2_captureparm capture;
2185 struct v4l2_outputparm output; 2412 struct v4l2_outputparm output;
@@ -2292,14 +2519,14 @@ struct v4l2_dbg_chip_ident {
2292 * @index: on return, index of the first created buffer 2519 * @index: on return, index of the first created buffer
2293 * @count: entry: number of requested buffers, 2520 * @count: entry: number of requested buffers,
2294 * return: number of created buffers 2521 * return: number of created buffers
2295 * @memory: buffer memory type 2522 * @memory: enum v4l2_memory; buffer memory type
2296 * @format: frame format, for which buffers are requested 2523 * @format: frame format, for which buffers are requested
2297 * @reserved: future extensions 2524 * @reserved: future extensions
2298 */ 2525 */
2299struct v4l2_create_buffers { 2526struct v4l2_create_buffers {
2300 __u32 index; 2527 __u32 index;
2301 __u32 count; 2528 __u32 count;
2302 enum v4l2_memory memory; 2529 __u32 memory;
2303 struct v4l2_format format; 2530 struct v4l2_format format;
2304 __u32 reserved[8]; 2531 __u32 reserved[8];
2305}; 2532};
@@ -2356,8 +2583,8 @@ struct v4l2_create_buffers {
2356#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) 2583#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format)
2357#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) 2584#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio)
2358#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) 2585#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout)
2359#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority) 2586#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) /* enum v4l2_priority */
2360#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority) 2587#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) /* enum v4l2_priority */
2361#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) 2588#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap)
2362#define VIDIOC_LOG_STATUS _IO('V', 70) 2589#define VIDIOC_LOG_STATUS _IO('V', 70)
2363#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) 2590#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls)
@@ -2384,6 +2611,9 @@ struct v4l2_create_buffers {
2384#endif 2611#endif
2385 2612
2386#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) 2613#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
2614
2615/* These four DV Preset ioctls are deprecated in favor of the DV Timings
2616 ioctls. */
2387#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset) 2617#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset)
2388#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset) 2618#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset)
2389#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset) 2619#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset)
@@ -2408,6 +2638,12 @@ struct v4l2_create_buffers {
2408#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) 2638#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd)
2409#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) 2639#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd)
2410 2640
2641/* Experimental, these three ioctls may change over the next couple of kernel
2642 versions. */
2643#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 96, struct v4l2_enum_dv_timings)
2644#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 97, struct v4l2_dv_timings)
2645#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 98, struct v4l2_dv_timings_cap)
2646
2411/* Reminder: when adding new ioctls please add support for them to 2647/* Reminder: when adding new ioctls please add support for them to
2412 drivers/media/video/v4l2-compat-ioctl32.c as well! */ 2648 drivers/media/video/v4l2-compat-ioctl32.c as well! */
2413 2649
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-21 18:26:05 -0500