i7core_edac: Add an EDAC memory controller driver for Nehalem chipsets

This driver is meant to support i7 core/i7core extreme desktop
processors and Xeon 35xx/55xx series with integrated memory controller.
It is likely that it can be expanded in the future to work with other
processor series based at the same Memory Controller design.

For now, it has just a few MCH status reads.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 9f688d243b86..c5dd0994bd7c 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2532,6 +2532,22 @@
 #define PCI_DEVICE_ID_INTEL_ICH9_6      0x2930
 #define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
 #define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
+#define PCI_DEVICE_ID_INTEL_I7_MCR      0x2c18
+#define PCI_DEVICE_ID_INTEL_I7_MC_TAD   0x2c19
+#define PCI_DEVICE_ID_INTEL_I7_MC_RAS   0x2c1a
+#define PCI_DEVICE_ID_INTEL_I7_MC_TEST  0x2c1c
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL  0x2c20
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR  0x2c21
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK  0x2c22
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC    0x2c23
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL  0x2c28
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR  0x2c29
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK  0x2c2a
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC    0x2c2b
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL  0x2c30
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR  0x2c31
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33
 #define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG4   0x3429
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG5   0x342a