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authorKeshavamurthy, Anil S <anil.s.keshavamurthy@intel.com>2007-10-21 19:41:46 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-22 11:13:18 -0400
commit994a65e25df85abc465cfee495557200e8205f9e (patch)
tree2b6676898cccc03a356a67a3173fdb50bb25abb6 /include/linux
parent10e5247f40f3bf7508a0ed2848c9cae37bddf4bc (diff)
Intel IOMMU: PCI generic helper function
When devices are under a p2p bridge, upstream transactions get replaced by the device id of the bridge as it owns the PCIE transaction. Hence its necessary to setup translations on behalf of the bridge as well. Due to this limitation all devices under a p2p share the same domain in a DMAR. We just cache the type of device, if its a native PCIe device or not for later use. [akpm@linux-foundation.org: BUG_ON -> WARN_ON+recover] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/pci.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 768b93359f90..5d2281f661f7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -141,6 +141,7 @@ struct pci_dev {
141 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 141 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
142 u8 revision; /* PCI revision, low byte of class word */ 142 u8 revision; /* PCI revision, low byte of class word */
143 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 143 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
144 u8 pcie_type; /* PCI-E device/port type */
144 u8 rom_base_reg; /* which config register controls the ROM */ 145 u8 rom_base_reg; /* which config register controls the ROM */
145 u8 pin; /* which interrupt pin this device uses */ 146 u8 pin; /* which interrupt pin this device uses */
146 147
@@ -183,6 +184,7 @@ struct pci_dev {
183 unsigned int msi_enabled:1; 184 unsigned int msi_enabled:1;
184 unsigned int msix_enabled:1; 185 unsigned int msix_enabled:1;
185 unsigned int is_managed:1; 186 unsigned int is_managed:1;
187 unsigned int is_pcie:1;
186 atomic_t enable_cnt; /* pci_enable_device has been called */ 188 atomic_t enable_cnt; /* pci_enable_device has been called */
187 189
188 u32 saved_config_space[16]; /* config space saved at suspend time */ 190 u32 saved_config_space[16]; /* config space saved at suspend time */