diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-24 20:18:32 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-24 20:18:32 -0500 |
| commit | 8e585a6c4abdef8562308f3f307aeea6cf168e8b (patch) | |
| tree | 70236b30b362123b009f2b723056072f7028d75e /include/linux | |
| parent | 1b59bab55e36082b1db3dc81bb32475616487a98 (diff) | |
| parent | fb1b5034e4987b158179a62732fb6dfb8f7ec88e (diff) | |
Merge tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
Pull infiniband updates from Roland Dreier:
"Main batch of InfiniBand/RDMA changes for 3.14:
- Flow steering for InfiniBand UD traffic
- IP-based addressing for IBoE aka RoCE
- Pass SRP submaintainership from Dave to Bart
- SRP transport fixes from Bart
- Add the new Cisco usNIC low-level device driver
- Various other fixes"
* tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: (75 commits)
IB/mlx5: Verify reserved fields are cleared
IB/mlx5: Remove old field for create mkey mailbox
IB/mlx5: Abort driver cleanup if teardown hca fails
IB/mlx5: Allow creation of QPs with zero-length work queues
mlx5_core: Fix PowerPC support
mlx5_core: Improve debugfs readability
IB/mlx5: Add support for resize CQ
IB/mlx5: Implement modify CQ
IB/mlx5: Make sure doorbell record is visible before doorbell
mlx5_core: Use mlx5 core style warning
IB/mlx5: Clear out struct before create QP command
mlx5_core: Fix out arg size in access_register command
RDMA/nes: Slight optimization of Ethernet address compare
IB/qib: Fix QP check when looping back to/from QP1
RDMA/cxgb4: Fix gcc warning on 32-bit arch
IB/usnic: Remove unused includes of <linux/version.h>
RDMA/amso1100: Add check if cache memory was allocated before freeing it
IPoIB: Report operstate consistently when brought up without a link
IB/core: Fix unused variable warning
RDMA/cma: Handle global/non-linklocal IPv6 addresses in cma_check_linklocal()
...
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mlx4/cmd.h | 1 | ||||
| -rw-r--r-- | include/linux/mlx4/cq.h | 15 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 7 | ||||
| -rw-r--r-- | include/linux/mlx5/cq.h | 18 | ||||
| -rw-r--r-- | include/linux/mlx5/device.h | 31 | ||||
| -rw-r--r-- | include/linux/mlx5/qp.h | 45 |
6 files changed, 101 insertions, 16 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index 8df61bc5da00..ff36620f88a7 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h | |||
| @@ -157,6 +157,7 @@ enum { | |||
| 157 | /* register/delete flow steering network rules */ | 157 | /* register/delete flow steering network rules */ |
| 158 | MLX4_QP_FLOW_STEERING_ATTACH = 0x65, | 158 | MLX4_QP_FLOW_STEERING_ATTACH = 0x65, |
| 159 | MLX4_QP_FLOW_STEERING_DETACH = 0x66, | 159 | MLX4_QP_FLOW_STEERING_DETACH = 0x66, |
| 160 | MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64, | ||
| 160 | }; | 161 | }; |
| 161 | 162 | ||
| 162 | enum { | 163 | enum { |
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h index 98fa492cf406..e1862997f933 100644 --- a/include/linux/mlx4/cq.h +++ b/include/linux/mlx4/cq.h | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #define MLX4_CQ_H | 34 | #define MLX4_CQ_H |
| 35 | 35 | ||
| 36 | #include <linux/types.h> | 36 | #include <linux/types.h> |
| 37 | #include <uapi/linux/if_ether.h> | ||
| 37 | 38 | ||
| 38 | #include <linux/mlx4/device.h> | 39 | #include <linux/mlx4/device.h> |
| 39 | #include <linux/mlx4/doorbell.h> | 40 | #include <linux/mlx4/doorbell.h> |
| @@ -43,10 +44,15 @@ struct mlx4_cqe { | |||
| 43 | __be32 immed_rss_invalid; | 44 | __be32 immed_rss_invalid; |
| 44 | __be32 g_mlpath_rqpn; | 45 | __be32 g_mlpath_rqpn; |
| 45 | __be16 sl_vid; | 46 | __be16 sl_vid; |
| 46 | __be16 rlid; | 47 | union { |
| 47 | __be16 status; | 48 | struct { |
| 48 | u8 ipv6_ext_mask; | 49 | __be16 rlid; |
| 49 | u8 badfcs_enc; | 50 | __be16 status; |
| 51 | u8 ipv6_ext_mask; | ||
| 52 | u8 badfcs_enc; | ||
| 53 | }; | ||
| 54 | u8 smac[ETH_ALEN]; | ||
| 55 | }; | ||
| 50 | __be32 byte_cnt; | 56 | __be32 byte_cnt; |
| 51 | __be16 wqe_index; | 57 | __be16 wqe_index; |
| 52 | __be16 checksum; | 58 | __be16 checksum; |
| @@ -83,6 +89,7 @@ struct mlx4_ts_cqe { | |||
| 83 | enum { | 89 | enum { |
| 84 | MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, | 90 | MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, |
| 85 | MLX4_CQE_QPN_MASK = 0xffffff, | 91 | MLX4_CQE_QPN_MASK = 0xffffff, |
| 92 | MLX4_CQE_VID_MASK = 0xfff, | ||
| 86 | }; | 93 | }; |
| 87 | 94 | ||
| 88 | enum { | 95 | enum { |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 7d3a523160ba..ac5cb1d92487 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -160,7 +160,8 @@ enum { | |||
| 160 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, | 160 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
| 161 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, | 161 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
| 162 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, | 162 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
| 163 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8 | 163 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
| 164 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9 | ||
| 164 | }; | 165 | }; |
| 165 | 166 | ||
| 166 | enum { | 167 | enum { |
| @@ -1095,6 +1096,7 @@ int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |||
| 1095 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); | 1096 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
| 1096 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | 1097 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, |
| 1097 | u8 *pg, u16 *ratelimit); | 1098 | u8 *pg, u16 *ratelimit); |
| 1099 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); | ||
| 1098 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); | 1100 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
| 1099 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); | 1101 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
| 1100 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); | 1102 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
| @@ -1144,6 +1146,9 @@ int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int | |||
| 1144 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); | 1146 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
| 1145 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | 1147 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); |
| 1146 | 1148 | ||
| 1149 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, | ||
| 1150 | u32 max_range_qpn); | ||
| 1151 | |||
| 1147 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); | 1152 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
| 1148 | 1153 | ||
| 1149 | #endif /* MLX4_DEVICE_H */ | 1154 | #endif /* MLX4_DEVICE_H */ |
diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 3db67f73d96d..2202c7f72b75 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h | |||
| @@ -79,15 +79,23 @@ enum { | |||
| 79 | MLX5_CQE_RESP_SEND = 2, | 79 | MLX5_CQE_RESP_SEND = 2, |
| 80 | MLX5_CQE_RESP_SEND_IMM = 3, | 80 | MLX5_CQE_RESP_SEND_IMM = 3, |
| 81 | MLX5_CQE_RESP_SEND_INV = 4, | 81 | MLX5_CQE_RESP_SEND_INV = 4, |
| 82 | MLX5_CQE_RESIZE_CQ = 0xff, /* TBD */ | 82 | MLX5_CQE_RESIZE_CQ = 5, |
| 83 | MLX5_CQE_REQ_ERR = 13, | 83 | MLX5_CQE_REQ_ERR = 13, |
| 84 | MLX5_CQE_RESP_ERR = 14, | 84 | MLX5_CQE_RESP_ERR = 14, |
| 85 | MLX5_CQE_INVALID = 15, | ||
| 85 | }; | 86 | }; |
| 86 | 87 | ||
| 87 | enum { | 88 | enum { |
| 88 | MLX5_CQ_MODIFY_RESEIZE = 0, | 89 | MLX5_CQ_MODIFY_PERIOD = 1 << 0, |
| 89 | MLX5_CQ_MODIFY_MODER = 1, | 90 | MLX5_CQ_MODIFY_COUNT = 1 << 1, |
| 90 | MLX5_CQ_MODIFY_MAPPING = 2, | 91 | MLX5_CQ_MODIFY_OVERRUN = 1 << 2, |
| 92 | }; | ||
| 93 | |||
| 94 | enum { | ||
| 95 | MLX5_CQ_OPMOD_RESIZE = 1, | ||
| 96 | MLX5_MODIFY_CQ_MASK_LOG_SIZE = 1 << 0, | ||
| 97 | MLX5_MODIFY_CQ_MASK_PG_OFFSET = 1 << 1, | ||
| 98 | MLX5_MODIFY_CQ_MASK_PG_SIZE = 1 << 2, | ||
| 91 | }; | 99 | }; |
| 92 | 100 | ||
| 93 | struct mlx5_cq_modify_params { | 101 | struct mlx5_cq_modify_params { |
| @@ -158,7 +166,7 @@ int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | |||
| 158 | int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | 166 | int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, |
| 159 | struct mlx5_query_cq_mbox_out *out); | 167 | struct mlx5_query_cq_mbox_out *out); |
| 160 | int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | 168 | int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, |
| 161 | int type, struct mlx5_cq_modify_params *params); | 169 | struct mlx5_modify_cq_mbox_in *in, int in_sz); |
| 162 | int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | 170 | int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); |
| 163 | void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | 171 | void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); |
| 164 | 172 | ||
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index da78875807fc..817a6fae6d2c 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h | |||
| @@ -104,9 +104,10 @@ enum { | |||
| 104 | }; | 104 | }; |
| 105 | 105 | ||
| 106 | enum { | 106 | enum { |
| 107 | MLX5_BF_REGS_PER_PAGE = 4, | 107 | MLX5_BF_REGS_PER_PAGE = 4, |
| 108 | MLX5_MAX_UAR_PAGES = 1 << 8, | 108 | MLX5_MAX_UAR_PAGES = 1 << 8, |
| 109 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE, | 109 | MLX5_NON_FP_BF_REGS_PER_PAGE = 2, |
| 110 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, | ||
| 110 | }; | 111 | }; |
| 111 | 112 | ||
| 112 | enum { | 113 | enum { |
| @@ -176,6 +177,8 @@ enum { | |||
| 176 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | 177 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, |
| 177 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | 178 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, |
| 178 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, | 179 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, |
| 180 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, | ||
| 181 | MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, | ||
| 179 | MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, | 182 | MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, |
| 180 | MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, | 183 | MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, |
| 181 | MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, | 184 | MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, |
| @@ -231,7 +234,8 @@ enum { | |||
| 231 | }; | 234 | }; |
| 232 | 235 | ||
| 233 | enum { | 236 | enum { |
| 234 | MLX5_ADAPTER_PAGE_SHIFT = 12 | 237 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
| 238 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, | ||
| 235 | }; | 239 | }; |
| 236 | 240 | ||
| 237 | enum { | 241 | enum { |
| @@ -697,6 +701,20 @@ struct mlx5_query_cq_mbox_out { | |||
| 697 | __be64 pas[0]; | 701 | __be64 pas[0]; |
| 698 | }; | 702 | }; |
| 699 | 703 | ||
| 704 | struct mlx5_modify_cq_mbox_in { | ||
| 705 | struct mlx5_inbox_hdr hdr; | ||
| 706 | __be32 cqn; | ||
| 707 | __be32 field_select; | ||
| 708 | struct mlx5_cq_context ctx; | ||
| 709 | u8 rsvd[192]; | ||
| 710 | __be64 pas[0]; | ||
| 711 | }; | ||
| 712 | |||
| 713 | struct mlx5_modify_cq_mbox_out { | ||
| 714 | struct mlx5_outbox_hdr hdr; | ||
| 715 | u8 rsvd[8]; | ||
| 716 | }; | ||
| 717 | |||
| 700 | struct mlx5_enable_hca_mbox_in { | 718 | struct mlx5_enable_hca_mbox_in { |
| 701 | struct mlx5_inbox_hdr hdr; | 719 | struct mlx5_inbox_hdr hdr; |
| 702 | u8 rsvd[8]; | 720 | u8 rsvd[8]; |
| @@ -831,8 +849,8 @@ struct mlx5_create_mkey_mbox_in { | |||
| 831 | struct mlx5_mkey_seg seg; | 849 | struct mlx5_mkey_seg seg; |
| 832 | u8 rsvd1[16]; | 850 | u8 rsvd1[16]; |
| 833 | __be32 xlat_oct_act_size; | 851 | __be32 xlat_oct_act_size; |
| 834 | __be32 bsf_coto_act_size; | 852 | __be32 rsvd2; |
| 835 | u8 rsvd2[168]; | 853 | u8 rsvd3[168]; |
| 836 | __be64 pas[0]; | 854 | __be64 pas[0]; |
| 837 | }; | 855 | }; |
| 838 | 856 | ||
| @@ -871,6 +889,7 @@ struct mlx5_modify_mkey_mbox_in { | |||
| 871 | 889 | ||
| 872 | struct mlx5_modify_mkey_mbox_out { | 890 | struct mlx5_modify_mkey_mbox_out { |
| 873 | struct mlx5_outbox_hdr hdr; | 891 | struct mlx5_outbox_hdr hdr; |
| 892 | u8 rsvd[8]; | ||
| 874 | }; | 893 | }; |
| 875 | 894 | ||
| 876 | struct mlx5_dump_mkey_mbox_in { | 895 | struct mlx5_dump_mkey_mbox_in { |
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index d9e3eacb3a7f..d51eff713549 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h | |||
| @@ -464,4 +464,49 @@ void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); | |||
| 464 | int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); | 464 | int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); |
| 465 | void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); | 465 | void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); |
| 466 | 466 | ||
| 467 | static inline const char *mlx5_qp_type_str(int type) | ||
| 468 | { | ||
| 469 | switch (type) { | ||
| 470 | case MLX5_QP_ST_RC: return "RC"; | ||
| 471 | case MLX5_QP_ST_UC: return "C"; | ||
| 472 | case MLX5_QP_ST_UD: return "UD"; | ||
| 473 | case MLX5_QP_ST_XRC: return "XRC"; | ||
| 474 | case MLX5_QP_ST_MLX: return "MLX"; | ||
| 475 | case MLX5_QP_ST_QP0: return "QP0"; | ||
| 476 | case MLX5_QP_ST_QP1: return "QP1"; | ||
| 477 | case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; | ||
| 478 | case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; | ||
| 479 | case MLX5_QP_ST_SNIFFER: return "SNIFFER"; | ||
| 480 | case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; | ||
| 481 | case MLX5_QP_ST_PTP_1588: return "PTP_1588"; | ||
| 482 | case MLX5_QP_ST_REG_UMR: return "REG_UMR"; | ||
| 483 | default: return "Invalid transport type"; | ||
| 484 | } | ||
| 485 | } | ||
| 486 | |||
| 487 | static inline const char *mlx5_qp_state_str(int state) | ||
| 488 | { | ||
| 489 | switch (state) { | ||
| 490 | case MLX5_QP_STATE_RST: | ||
| 491 | return "RST"; | ||
| 492 | case MLX5_QP_STATE_INIT: | ||
| 493 | return "INIT"; | ||
| 494 | case MLX5_QP_STATE_RTR: | ||
| 495 | return "RTR"; | ||
| 496 | case MLX5_QP_STATE_RTS: | ||
| 497 | return "RTS"; | ||
| 498 | case MLX5_QP_STATE_SQER: | ||
| 499 | return "SQER"; | ||
| 500 | case MLX5_QP_STATE_SQD: | ||
| 501 | return "SQD"; | ||
| 502 | case MLX5_QP_STATE_ERR: | ||
| 503 | return "ERR"; | ||
| 504 | case MLX5_QP_STATE_SQ_DRAINING: | ||
| 505 | return "SQ_DRAINING"; | ||
| 506 | case MLX5_QP_STATE_SUSPENDED: | ||
| 507 | return "SUSPENDED"; | ||
| 508 | default: return "Invalid QP state"; | ||
| 509 | } | ||
| 510 | } | ||
| 511 | |||
| 467 | #endif /* MLX5_QP_H */ | 512 | #endif /* MLX5_QP_H */ |
