Merge tag 'mfd-lee-3.13-1' of git://git.linaro.org/people/ljones/mfd

mfd-lee-3.13-1 MFD patches due for v3.13.
author: Samuel Ortiz <sameo@linux.intel.com> 2013-10-25 05:03:48 -0400
committer: Samuel Ortiz <sameo@linux.intel.com> 2013-10-25 05:03:48 -0400
commit: 8df5a1ba67b1a4b1560472359c30a5b1e3ebcc78 (patch)
tree: 1563cc6270c76867a8dfe60c7c3d1e57064fed79 /include/linux
parent: 46a99d03f97e54d346a35bb8f0fa79ba73687ad0 (diff)
parent: 6bfd1e63de34a278d67db32e3644340838308252 (diff)
11 files changed, 628 insertions, 28 deletions
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 4706d3d46e56..cb49417f8ba9 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -1908,7 +1908,7 @@
 #define ARIZONA_FLL2_SYNC_GAIN_MASK              0x003c  /* FLL2_SYNC_GAIN */
 #define ARIZONA_FLL2_SYNC_GAIN_SHIFT                  2  /* FLL2_SYNC_GAIN */
 #define ARIZONA_FLL2_SYNC_GAIN_WIDTH                  4  /* FLL2_SYNC_GAIN */
-#define ARIZONA_FLL2_SYNC_BW_MASK                0x0001  /* FLL2_SYNC_BW */
+#define ARIZONA_FLL2_SYNC_BW                     0x0001  /* FLL2_SYNC_BW */
 #define ARIZONA_FLL2_SYNC_BW_MASK                0x0001  /* FLL2_SYNC_BW */
 #define ARIZONA_FLL2_SYNC_BW_SHIFT                    0  /* FLL2_SYNC_BW */
 #define ARIZONA_FLL2_SYNC_BW_WIDTH                    1  /* FLL2_SYNC_BW */
diff --git a/include/linux/mfd/as3722.h b/include/linux/mfd/as3722.h
new file mode 100644
index 000000000000..16bf8a0dcd97
--- /dev/null
+++ b/include/linux/mfd/as3722.h
@@ -0,0 +1,423 @@
+/*
+ * as3722 definitions
+ *
+ * Copyright (C) 2013 ams
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * Author: Florian Lobmaier <florian.lobmaier@ams.com>
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#ifndef __LINUX_MFD_AS3722_H__
+#define __LINUX_MFD_AS3722_H__
+#include <linux/regmap.h>
+/* AS3722 registers */
+#define AS3722_SD0_VOLTAGE_REG                          0x00
+#define AS3722_SD1_VOLTAGE_REG                          0x01
+#define AS3722_SD2_VOLTAGE_REG                          0x02
+#define AS3722_SD3_VOLTAGE_REG                          0x03
+#define AS3722_SD4_VOLTAGE_REG                          0x04
+#define AS3722_SD5_VOLTAGE_REG                          0x05
+#define AS3722_SD6_VOLTAGE_REG                          0x06
+#define AS3722_GPIO0_CONTROL_REG                        0x08
+#define AS3722_GPIO1_CONTROL_REG                        0x09
+#define AS3722_GPIO2_CONTROL_REG                        0x0A
+#define AS3722_GPIO3_CONTROL_REG                        0x0B
+#define AS3722_GPIO4_CONTROL_REG                        0x0C
+#define AS3722_GPIO5_CONTROL_REG                        0x0D
+#define AS3722_GPIO6_CONTROL_REG                        0x0E
+#define AS3722_GPIO7_CONTROL_REG                        0x0F
+#define AS3722_LDO0_VOLTAGE_REG                         0x10
+#define AS3722_LDO1_VOLTAGE_REG                         0x11
+#define AS3722_LDO2_VOLTAGE_REG                         0x12
+#define AS3722_LDO3_VOLTAGE_REG                         0x13
+#define AS3722_LDO4_VOLTAGE_REG                         0x14
+#define AS3722_LDO5_VOLTAGE_REG                         0x15
+#define AS3722_LDO6_VOLTAGE_REG                         0x16
+#define AS3722_LDO7_VOLTAGE_REG                         0x17
+#define AS3722_LDO9_VOLTAGE_REG                         0x19
+#define AS3722_LDO10_VOLTAGE_REG                        0x1A
+#define AS3722_LDO11_VOLTAGE_REG                        0x1B
+#define AS3722_GPIO_DEB1_REG                            0x1E
+#define AS3722_GPIO_DEB2_REG                            0x1F
+#define AS3722_GPIO_SIGNAL_OUT_REG                      0x20
+#define AS3722_GPIO_SIGNAL_IN_REG                       0x21
+#define AS3722_REG_SEQU_MOD1_REG                        0x22
+#define AS3722_REG_SEQU_MOD2_REG                        0x23
+#define AS3722_REG_SEQU_MOD3_REG                        0x24
+#define AS3722_SD_PHSW_CTRL_REG                         0x27
+#define AS3722_SD_PHSW_STATUS                           0x28
+#define AS3722_SD0_CONTROL_REG                          0x29
+#define AS3722_SD1_CONTROL_REG                          0x2A
+#define AS3722_SDmph_CONTROL_REG                        0x2B
+#define AS3722_SD23_CONTROL_REG                         0x2C
+#define AS3722_SD4_CONTROL_REG                          0x2D
+#define AS3722_SD5_CONTROL_REG                          0x2E
+#define AS3722_SD6_CONTROL_REG                          0x2F
+#define AS3722_SD_DVM_REG                               0x30
+#define AS3722_RESET_REASON_REG                         0x31
+#define AS3722_BATTERY_VOLTAGE_MONITOR_REG              0x32
+#define AS3722_STARTUP_CONTROL_REG                      0x33
+#define AS3722_RESET_TIMER_REG                          0x34
+#define AS3722_REFERENCE_CONTROL_REG                    0x35
+#define AS3722_RESET_CONTROL_REG                        0x36
+#define AS3722_OVER_TEMP_CONTROL_REG                    0x37
+#define AS3722_WATCHDOG_CONTROL_REG                     0x38
+#define AS3722_REG_STANDBY_MOD1_REG                     0x39
+#define AS3722_REG_STANDBY_MOD2_REG                     0x3A
+#define AS3722_REG_STANDBY_MOD3_REG                     0x3B
+#define AS3722_ENABLE_CTRL1_REG                         0x3C
+#define AS3722_ENABLE_CTRL2_REG                         0x3D
+#define AS3722_ENABLE_CTRL3_REG                         0x3E
+#define AS3722_ENABLE_CTRL4_REG                         0x3F
+#define AS3722_ENABLE_CTRL5_REG                         0x40
+#define AS3722_PWM_CONTROL_L_REG                        0x41
+#define AS3722_PWM_CONTROL_H_REG                        0x42
+#define AS3722_WATCHDOG_TIMER_REG                       0x46
+#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG             0x48
+#define AS3722_IOVOLTAGE_REG                            0x49
+#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG             0x4A
+#define AS3722_SD_CONTROL_REG                           0x4D
+#define AS3722_LDOCONTROL0_REG                          0x4E
+#define AS3722_LDOCONTROL1_REG                          0x4F
+#define AS3722_SD0_PROTECT_REG                          0x50
+#define AS3722_SD6_PROTECT_REG                          0x51
+#define AS3722_PWM_VCONTROL1_REG                        0x52
+#define AS3722_PWM_VCONTROL2_REG                        0x53
+#define AS3722_PWM_VCONTROL3_REG                        0x54
+#define AS3722_PWM_VCONTROL4_REG                        0x55
+#define AS3722_BB_CHARGER_REG                           0x57
+#define AS3722_CTRL_SEQU1_REG                           0x58
+#define AS3722_CTRL_SEQU2_REG                           0x59
+#define AS3722_OVCURRENT_REG                            0x5A
+#define AS3722_OVCURRENT_DEB_REG                        0x5B
+#define AS3722_SDLV_DEB_REG                             0x5C
+#define AS3722_OC_PG_CTRL_REG                           0x5D
+#define AS3722_OC_PG_CTRL2_REG                          0x5E
+#define AS3722_CTRL_STATUS                              0x5F
+#define AS3722_RTC_CONTROL_REG                          0x60
+#define AS3722_RTC_SECOND_REG                           0x61
+#define AS3722_RTC_MINUTE_REG                           0x62
+#define AS3722_RTC_HOUR_REG                             0x63
+#define AS3722_RTC_DAY_REG                              0x64
+#define AS3722_RTC_MONTH_REG                            0x65
+#define AS3722_RTC_YEAR_REG                             0x66
+#define AS3722_RTC_ALARM_SECOND_REG                     0x67
+#define AS3722_RTC_ALARM_MINUTE_REG                     0x68
+#define AS3722_RTC_ALARM_HOUR_REG                       0x69
+#define AS3722_RTC_ALARM_DAY_REG                        0x6A
+#define AS3722_RTC_ALARM_MONTH_REG                      0x6B
+#define AS3722_RTC_ALARM_YEAR_REG                       0x6C
+#define AS3722_SRAM_REG                                 0x6D
+#define AS3722_RTC_ACCESS_REG                           0x6F
+#define AS3722_RTC_STATUS_REG                           0x73
+#define AS3722_INTERRUPT_MASK1_REG                      0x74
+#define AS3722_INTERRUPT_MASK2_REG                      0x75
+#define AS3722_INTERRUPT_MASK3_REG                      0x76
+#define AS3722_INTERRUPT_MASK4_REG                      0x77
+#define AS3722_INTERRUPT_STATUS1_REG                    0x78
+#define AS3722_INTERRUPT_STATUS2_REG                    0x79
+#define AS3722_INTERRUPT_STATUS3_REG                    0x7A
+#define AS3722_INTERRUPT_STATUS4_REG                    0x7B
+#define AS3722_TEMP_STATUS_REG                          0x7D
+#define AS3722_ADC0_CONTROL_REG                         0x80
+#define AS3722_ADC1_CONTROL_REG                         0x81
+#define AS3722_ADC0_MSB_RESULT_REG                      0x82
+#define AS3722_ADC0_LSB_RESULT_REG                      0x83
+#define AS3722_ADC1_MSB_RESULT_REG                      0x84
+#define AS3722_ADC1_LSB_RESULT_REG                      0x85
+#define AS3722_ADC1_THRESHOLD_HI_MSB_REG                0x86
+#define AS3722_ADC1_THRESHOLD_HI_LSB_REG                0x87
+#define AS3722_ADC1_THRESHOLD_LO_MSB_REG                0x88
+#define AS3722_ADC1_THRESHOLD_LO_LSB_REG                0x89
author	Samuel Ortiz <sameo@linux.intel.com>	2013-10-25 05:03:48 -0400
committer	Samuel Ortiz <sameo@linux.intel.com>	2013-10-25 05:03:48 -0400
commit	8df5a1ba67b1a4b1560472359c30a5b1e3ebcc78 (patch)
tree	1563cc6270c76867a8dfe60c7c3d1e57064fed79 /include/linux
parent	46a99d03f97e54d346a35bb8f0fa79ba73687ad0 (diff)
parent	6bfd1e63de34a278d67db32e3644340838308252 (diff)

diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index 4706d3d46e56..cb49417f8ba9 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h
@@ -1908,7 +1908,7 @@
1908	#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */	1908	#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */
1909	#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */	1909	#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */
1910	#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */	1910	#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */
1911	#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */	1911	#define ARIZONA_FLL2_SYNC_BW 0x0001 /* FLL2_SYNC_BW */
1912	#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */	1912	#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
1913	#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */	1913	#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */
1914	#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */	1914	#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */


diff --git a/include/linux/mfd/as3722.h b/include/linux/mfd/as3722.h new file mode 100644 index 000000000000..16bf8a0dcd97 --- /dev/null +++ b/include/linux/mfd/as3722.h
@@ -0,0 +1,423 @@
		1	/*
		2	* as3722 definitions
		3	*
		4	* Copyright (C) 2013 ams
		5	* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
		6	*
		7	* Author: Florian Lobmaier <florian.lobmaier@ams.com>
		8	* Author: Laxman Dewangan <ldewangan@nvidia.com>
		9	*
		10	* This program is free software; you can redistribute it and/or modify
		11	* it under the terms of the GNU General Public License as published by
		12	* the Free Software Foundation; either version 2 of the License, or
		13	* (at your option) any later version.
		14	*
		15	* This program is distributed in the hope that it will be useful,
		16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
		17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		18	* GNU General Public License for more details.
		19	*
		20	* You should have received a copy of the GNU General Public License
		21	* along with this program; if not, write to the Free Software
		22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		23	*
		24	*/
		25
		26	#ifndef __LINUX_MFD_AS3722_H__
		27	#define __LINUX_MFD_AS3722_H__
		28
		29	#include <linux/regmap.h>
		30
		31	/* AS3722 registers */
		32	#define AS3722_SD0_VOLTAGE_REG 0x00
		33	#define AS3722_SD1_VOLTAGE_REG 0x01
		34	#define AS3722_SD2_VOLTAGE_REG 0x02
		35	#define AS3722_SD3_VOLTAGE_REG 0x03
		36	#define AS3722_SD4_VOLTAGE_REG 0x04
		37	#define AS3722_SD5_VOLTAGE_REG 0x05
		38	#define AS3722_SD6_VOLTAGE_REG 0x06
		39	#define AS3722_GPIO0_CONTROL_REG 0x08
		40	#define AS3722_GPIO1_CONTROL_REG 0x09
		41	#define AS3722_GPIO2_CONTROL_REG 0x0A
		42	#define AS3722_GPIO3_CONTROL_REG 0x0B
		43	#define AS3722_GPIO4_CONTROL_REG 0x0C
		44	#define AS3722_GPIO5_CONTROL_REG 0x0D
		45	#define AS3722_GPIO6_CONTROL_REG 0x0E
		46	#define AS3722_GPIO7_CONTROL_REG 0x0F
		47	#define AS3722_LDO0_VOLTAGE_REG 0x10
		48	#define AS3722_LDO1_VOLTAGE_REG 0x11
		49	#define AS3722_LDO2_VOLTAGE_REG 0x12
		50	#define AS3722_LDO3_VOLTAGE_REG 0x13
		51	#define AS3722_LDO4_VOLTAGE_REG 0x14
		52	#define AS3722_LDO5_VOLTAGE_REG 0x15
		53	#define AS3722_LDO6_VOLTAGE_REG 0x16
		54	#define AS3722_LDO7_VOLTAGE_REG 0x17
		55	#define AS3722_LDO9_VOLTAGE_REG 0x19
		56	#define AS3722_LDO10_VOLTAGE_REG 0x1A
		57	#define AS3722_LDO11_VOLTAGE_REG 0x1B
		58	#define AS3722_GPIO_DEB1_REG 0x1E
		59	#define AS3722_GPIO_DEB2_REG 0x1F
		60	#define AS3722_GPIO_SIGNAL_OUT_REG 0x20
		61	#define AS3722_GPIO_SIGNAL_IN_REG 0x21
		62	#define AS3722_REG_SEQU_MOD1_REG 0x22
		63	#define AS3722_REG_SEQU_MOD2_REG 0x23
		64	#define AS3722_REG_SEQU_MOD3_REG 0x24
		65	#define AS3722_SD_PHSW_CTRL_REG 0x27
		66	#define AS3722_SD_PHSW_STATUS 0x28
		67	#define AS3722_SD0_CONTROL_REG 0x29
		68	#define AS3722_SD1_CONTROL_REG 0x2A
		69	#define AS3722_SDmph_CONTROL_REG 0x2B
		70	#define AS3722_SD23_CONTROL_REG 0x2C
		71	#define AS3722_SD4_CONTROL_REG 0x2D
		72	#define AS3722_SD5_CONTROL_REG 0x2E
		73	#define AS3722_SD6_CONTROL_REG 0x2F
		74	#define AS3722_SD_DVM_REG 0x30
		75	#define AS3722_RESET_REASON_REG 0x31
		76	#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
		77	#define AS3722_STARTUP_CONTROL_REG 0x33
		78	#define AS3722_RESET_TIMER_REG 0x34
		79	#define AS3722_REFERENCE_CONTROL_REG 0x35
		80	#define AS3722_RESET_CONTROL_REG 0x36
		81	#define AS3722_OVER_TEMP_CONTROL_REG 0x37
		82	#define AS3722_WATCHDOG_CONTROL_REG 0x38
		83	#define AS3722_REG_STANDBY_MOD1_REG 0x39
		84	#define AS3722_REG_STANDBY_MOD2_REG 0x3A
		85	#define AS3722_REG_STANDBY_MOD3_REG 0x3B
		86	#define AS3722_ENABLE_CTRL1_REG 0x3C
		87	#define AS3722_ENABLE_CTRL2_REG 0x3D
		88	#define AS3722_ENABLE_CTRL3_REG 0x3E
		89	#define AS3722_ENABLE_CTRL4_REG 0x3F
		90	#define AS3722_ENABLE_CTRL5_REG 0x40
		91	#define AS3722_PWM_CONTROL_L_REG 0x41
		92	#define AS3722_PWM_CONTROL_H_REG 0x42
		93	#define AS3722_WATCHDOG_TIMER_REG 0x46
		94	#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
		95	#define AS3722_IOVOLTAGE_REG 0x49
		96	#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
		97	#define AS3722_SD_CONTROL_REG 0x4D
		98	#define AS3722_LDOCONTROL0_REG 0x4E
		99	#define AS3722_LDOCONTROL1_REG 0x4F
		100	#define AS3722_SD0_PROTECT_REG 0x50
		101	#define AS3722_SD6_PROTECT_REG 0x51
		102	#define AS3722_PWM_VCONTROL1_REG 0x52
		103	#define AS3722_PWM_VCONTROL2_REG 0x53
		104	#define AS3722_PWM_VCONTROL3_REG 0x54
		105	#define AS3722_PWM_VCONTROL4_REG 0x55
		106	#define AS3722_BB_CHARGER_REG 0x57
		107	#define AS3722_CTRL_SEQU1_REG 0x58
		108	#define AS3722_CTRL_SEQU2_REG 0x59
		109	#define AS3722_OVCURRENT_REG 0x5A
		110	#define AS3722_OVCURRENT_DEB_REG 0x5B
		111	#define AS3722_SDLV_DEB_REG 0x5C
		112	#define AS3722_OC_PG_CTRL_REG 0x5D
		113	#define AS3722_OC_PG_CTRL2_REG 0x5E
		114	#define AS3722_CTRL_STATUS 0x5F
		115	#define AS3722_RTC_CONTROL_REG 0x60
		116	#define AS3722_RTC_SECOND_REG 0x61
		117	#define AS3722_RTC_MINUTE_REG 0x62
		118	#define AS3722_RTC_HOUR_REG 0x63
		119	#define AS3722_RTC_DAY_REG 0x64
		120	#define AS3722_RTC_MONTH_REG 0x65
		121	#define AS3722_RTC_YEAR_REG 0x66
		122	#define AS3722_RTC_ALARM_SECOND_REG 0x67
		123	#define AS3722_RTC_ALARM_MINUTE_REG 0x68
		124	#define AS3722_RTC_ALARM_HOUR_REG 0x69
		125	#define AS3722_RTC_ALARM_DAY_REG 0x6A
		126	#define AS3722_RTC_ALARM_MONTH_REG 0x6B
		127	#define AS3722_RTC_ALARM_YEAR_REG 0x6C
		128	#define AS3722_SRAM_REG 0x6D
		129	#define AS3722_RTC_ACCESS_REG 0x6F
		130	#define AS3722_RTC_STATUS_REG 0x73
		131	#define AS3722_INTERRUPT_MASK1_REG 0x74
		132	#define AS3722_INTERRUPT_MASK2_REG 0x75
		133	#define AS3722_INTERRUPT_MASK3_REG 0x76
		134	#define AS3722_INTERRUPT_MASK4_REG 0x77
		135	#define AS3722_INTERRUPT_STATUS1_REG 0x78
		136	#define AS3722_INTERRUPT_STATUS2_REG 0x79
		137	#define AS3722_INTERRUPT_STATUS3_REG 0x7A
		138	#define AS3722_INTERRUPT_STATUS4_REG 0x7B
		139	#define AS3722_TEMP_STATUS_REG 0x7D
		140	#define AS3722_ADC0_CONTROL_REG 0x80
		141	#define AS3722_ADC1_CONTROL_REG 0x81
		142	#define AS3722_ADC0_MSB_RESULT_REG 0x82
		143	#define AS3722_ADC0_LSB_RESULT_REG 0x83
		144	#define AS3722_ADC1_MSB_RESULT_REG 0x84
		145	#define AS3722_ADC1_LSB_RESULT_REG 0x85
		146	#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
		147	#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
		148	#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
		149	#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
		150