diff options
| author | Huang Shijie <b32955@freescale.com> | 2014-02-24 05:37:36 -0500 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2014-04-14 14:22:58 -0400 |
| commit | 6e602ef73334550bbbb8be1041a3ce6eecbd42f1 (patch) | |
| tree | ed7bdda5b4f68113ca57a996dcec304332426aca /include/linux | |
| parent | f39d2fa0122e6abd8505a3598f3aa535d0d5aade (diff) | |
mtd: spi-nor: add the basic data structures
The spi_nor{} is cloned from the m25p{}.
The spi_nor{} can be used by both the m25p80 and spi-nor controller.
We also add the spi_nor_xfer_cfg{} which can be used by the two
fundamental primitives: read_xfer/write_xfer.
1) the hooks for spi_nor{}:
@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them
by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready.
@read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.
2) Add a new field sst_write_second for the SST NOR write.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 483fc2a086c4..3a3c3872c8cd 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h | |||
| @@ -52,4 +52,114 @@ | |||
| 52 | /* Configuration Register bits. */ | 52 | /* Configuration Register bits. */ |
| 53 | #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ | 53 | #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ |
| 54 | 54 | ||
| 55 | enum read_mode { | ||
| 56 | SPI_NOR_NORMAL = 0, | ||
| 57 | SPI_NOR_FAST, | ||
| 58 | SPI_NOR_DUAL, | ||
| 59 | SPI_NOR_QUAD, | ||
| 60 | }; | ||
| 61 | |||
| 62 | /** | ||
| 63 | * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer | ||
| 64 | * @wren: command for "Write Enable", or 0x00 for not required | ||
| 65 | * @cmd: command for operation | ||
| 66 | * @cmd_pins: number of pins to send @cmd (1, 2, 4) | ||
| 67 | * @addr: address for operation | ||
| 68 | * @addr_pins: number of pins to send @addr (1, 2, 4) | ||
| 69 | * @addr_width: number of address bytes | ||
| 70 | * (3,4, or 0 for address not required) | ||
| 71 | * @mode: mode data | ||
| 72 | * @mode_pins: number of pins to send @mode (1, 2, 4) | ||
| 73 | * @mode_cycles: number of mode cycles (0 for mode not required) | ||
| 74 | * @dummy_cycles: number of dummy cycles (0 for dummy not required) | ||
| 75 | */ | ||
| 76 | struct spi_nor_xfer_cfg { | ||
| 77 | u8 wren; | ||
| 78 | u8 cmd; | ||
| 79 | u8 cmd_pins; | ||
| 80 | u32 addr; | ||
| 81 | u8 addr_pins; | ||
| 82 | u8 addr_width; | ||
| 83 | u8 mode; | ||
| 84 | u8 mode_pins; | ||
| 85 | u8 mode_cycles; | ||
| 86 | u8 dummy_cycles; | ||
| 87 | }; | ||
| 88 | |||
| 89 | #define SPI_NOR_MAX_CMD_SIZE 8 | ||
| 90 | enum spi_nor_ops { | ||
| 91 | SPI_NOR_OPS_READ = 0, | ||
| 92 | SPI_NOR_OPS_WRITE, | ||
| 93 | SPI_NOR_OPS_ERASE, | ||
| 94 | SPI_NOR_OPS_LOCK, | ||
| 95 | SPI_NOR_OPS_UNLOCK, | ||
| 96 | }; | ||
| 97 | |||
| 98 | /** | ||
| 99 | * struct spi_nor - Structure for defining a the SPI NOR layer | ||
| 100 | * @mtd: point to a mtd_info structure | ||
| 101 | * @lock: the lock for the read/write/erase/lock/unlock operations | ||
| 102 | * @dev: point to a spi device, or a spi nor controller device. | ||
| 103 | * @page_size: the page size of the SPI NOR | ||
| 104 | * @addr_width: number of address bytes | ||
| 105 | * @erase_opcode: the opcode for erasing a sector | ||
| 106 | * @read_opcode: the read opcode | ||
| 107 | * @read_dummy: the dummy needed by the read operation | ||
| 108 | * @program_opcode: the program opcode | ||
| 109 | * @flash_read: the mode of the read | ||
| 110 | * @sst_write_second: used by the SST write operation | ||
| 111 | * @cfg: used by the read_xfer/write_xfer | ||
| 112 | * @cmd_buf: used by the write_reg | ||
| 113 | * @prepare: [OPTIONAL] do some preparations for the | ||
| 114 | * read/write/erase/lock/unlock operations | ||
| 115 | * @unprepare: [OPTIONAL] do some post work after the | ||
| 116 | * read/write/erase/lock/unlock operations | ||
| 117 | * @read_xfer: [OPTIONAL] the read fundamental primitive | ||
| 118 | * @write_xfer: [OPTIONAL] the writefundamental primitive | ||
| 119 | * @read_reg: [DRIVER-SPECIFIC] read out the register | ||
| 120 | * @write_reg: [DRIVER-SPECIFIC] write data to the register | ||
| 121 | * @read_id: [REPLACEABLE] read out the ID data, and find | ||
| 122 | * the proper spi_device_id | ||
| 123 | * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready | ||
| 124 | * @read: [DRIVER-SPECIFIC] read data from the SPI NOR | ||
| 125 | * @write: [DRIVER-SPECIFIC] write data to the SPI NOR | ||
| 126 | * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR | ||
| 127 | * at the offset @offs | ||
| 128 | * @priv: the private data | ||
| 129 | */ | ||
| 130 | struct spi_nor { | ||
| 131 | struct mtd_info *mtd; | ||
| 132 | struct mutex lock; | ||
| 133 | struct device *dev; | ||
| 134 | u32 page_size; | ||
| 135 | u8 addr_width; | ||
| 136 | u8 erase_opcode; | ||
| 137 | u8 read_opcode; | ||
| 138 | u8 read_dummy; | ||
| 139 | u8 program_opcode; | ||
| 140 | enum read_mode flash_read; | ||
| 141 | bool sst_write_second; | ||
| 142 | struct spi_nor_xfer_cfg cfg; | ||
| 143 | u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; | ||
| 144 | |||
| 145 | int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); | ||
| 146 | void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); | ||
| 147 | int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, | ||
| 148 | u8 *buf, size_t len); | ||
| 149 | int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, | ||
| 150 | u8 *buf, size_t len); | ||
| 151 | int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); | ||
| 152 | int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, | ||
| 153 | int write_enable); | ||
| 154 | const struct spi_device_id *(*read_id)(struct spi_nor *nor); | ||
| 155 | int (*wait_till_ready)(struct spi_nor *nor); | ||
| 156 | |||
| 157 | int (*read)(struct spi_nor *nor, loff_t from, | ||
| 158 | size_t len, size_t *retlen, u_char *read_buf); | ||
| 159 | void (*write)(struct spi_nor *nor, loff_t to, | ||
| 160 | size_t len, size_t *retlen, const u_char *write_buf); | ||
| 161 | int (*erase)(struct spi_nor *nor, loff_t offs); | ||
| 162 | |||
| 163 | void *priv; | ||
| 164 | }; | ||
| 55 | #endif | 165 | #endif |
