diff options
| author | He, Qing <qing.he@intel.com> | 2007-08-05 03:49:16 -0400 |
|---|---|---|
| committer | Avi Kivity <avi@qumranet.com> | 2007-10-13 04:18:25 -0400 |
| commit | 6bf9e962d14deb9e460afbbfd83ea2f450325c2d (patch) | |
| tree | 050b2be2fcded255afbb2512ed9c07adbd3f5b0f /include/linux | |
| parent | c52fb35a8b5dada749d35fbe15ac1f9857b22896 (diff) | |
KVM: in-kernel IOAPIC save and restore support
This patch adds support for in-kernel ioapic save and restore (to
and from userspace). It uses the same get/set_irqchip ioctl as
in-kernel PIC.
Signed-off-by: Qing He <qing.he@intel.com>
Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@intel.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/kvm.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 6560f11870fd..42d15150d7a3 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h | |||
| @@ -45,7 +45,7 @@ struct kvm_irq_level { | |||
| 45 | __u32 level; | 45 | __u32 level; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | /* for KVM_GET_IRQCHIP / KVM_SET_IRQCHIP */ | 48 | /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ |
| 49 | struct kvm_pic_state { | 49 | struct kvm_pic_state { |
| 50 | __u8 last_irr; /* edge detection */ | 50 | __u8 last_irr; /* edge detection */ |
| 51 | __u8 irr; /* interrupt request register */ | 51 | __u8 irr; /* interrupt request register */ |
| @@ -65,9 +65,35 @@ struct kvm_pic_state { | |||
| 65 | __u8 elcr_mask; | 65 | __u8 elcr_mask; |
| 66 | }; | 66 | }; |
| 67 | 67 | ||
| 68 | #define KVM_IOAPIC_NUM_PINS 24 | ||
| 69 | struct kvm_ioapic_state { | ||
| 70 | __u64 base_address; | ||
| 71 | __u32 ioregsel; | ||
| 72 | __u32 id; | ||
| 73 | __u32 irr; | ||
| 74 | __u32 pad; | ||
| 75 | union { | ||
| 76 | __u64 bits; | ||
| 77 | struct { | ||
| 78 | __u8 vector; | ||
| 79 | __u8 delivery_mode:3; | ||
| 80 | __u8 dest_mode:1; | ||
| 81 | __u8 delivery_status:1; | ||
| 82 | __u8 polarity:1; | ||
| 83 | __u8 remote_irr:1; | ||
| 84 | __u8 trig_mode:1; | ||
| 85 | __u8 mask:1; | ||
| 86 | __u8 reserve:7; | ||
| 87 | __u8 reserved[4]; | ||
| 88 | __u8 dest_id; | ||
| 89 | } fields; | ||
| 90 | } redirtbl[KVM_IOAPIC_NUM_PINS]; | ||
| 91 | }; | ||
| 92 | |||
| 68 | enum kvm_irqchip_id { | 93 | enum kvm_irqchip_id { |
| 69 | KVM_IRQCHIP_PIC_MASTER = 0, | 94 | KVM_IRQCHIP_PIC_MASTER = 0, |
| 70 | KVM_IRQCHIP_PIC_SLAVE = 1, | 95 | KVM_IRQCHIP_PIC_SLAVE = 1, |
| 96 | KVM_IRQCHIP_IOAPIC = 2, | ||
| 71 | }; | 97 | }; |
| 72 | 98 | ||
| 73 | struct kvm_irqchip { | 99 | struct kvm_irqchip { |
| @@ -76,6 +102,7 @@ struct kvm_irqchip { | |||
| 76 | union { | 102 | union { |
| 77 | char dummy[512]; /* reserving space */ | 103 | char dummy[512]; /* reserving space */ |
| 78 | struct kvm_pic_state pic; | 104 | struct kvm_pic_state pic; |
| 105 | struct kvm_ioapic_state ioapic; | ||
| 79 | } chip; | 106 | } chip; |
| 80 | }; | 107 | }; |
| 81 | 108 | ||
