Merge tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/drivers

Merge "at91: drivers for 3.20 #1" from Nicolas Ferre:

First batch of drivers changes for 3.20:
- Internal AHB bus matrix (Matrix) and Static Memory Controller (SMC) are now
  mfd/syscon drivers.
- USB gadget full speed (at91_udc): fixes, simplification and multi-platform awareness
  DT enhancement.

* tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
  usb: gadget: at91_udc: Allocate udc instance
  usb: gadget: at91_udc: Update DT binding documentation
  usb: gadget: at91_udc: Rework for multi-platform kernel support
  usb: gadget: at91_udc: Simplify probe and remove functions
  usb: gadget: at91_udc: Remove non-DT handling code
  usb: gadget: at91_udc: Document DT clocks and clock-names property
  usb: gadget: at91_udc: Drop uclk clock
  usb: gadget: at91_udc: Fix clock names
  mfd: syscon: Add Atmel SMC binding doc
  mfd: syscon: Add atmel-smc registers definition
  mfd: syscon: Add Atmel Matrix bus DT binding documentation
  mfd: syscon: Add atmel-matrix registers definition

Signed-off-by: Olof Johansson <olof@lixom.net>

2 files changed, 290 insertions, 0 deletions

diff --git a/include/linux/mfd/syscon/atmel-matrix.h b/include/linux/mfd/syscon/atmel-matrix.h
new file mode 100644
index 000000000000..8293c3e2a82a
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-matrix.h
@@ -0,0 +1,117 @@
+/*
+ *  Copyright (C) 2014 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+#define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+
+#define AT91SAM9260_MATRIX_MCFG                 0x00
+#define AT91SAM9260_MATRIX_SCFG                 0x40
+#define AT91SAM9260_MATRIX_PRS                  0x80
+#define AT91SAM9260_MATRIX_MRCR                 0x100
+#define AT91SAM9260_MATRIX_EBICSA               0x11c
+
+#define AT91SAM9261_MATRIX_MRCR                 0x0
+#define AT91SAM9261_MATRIX_SCFG                 0x4
+#define AT91SAM9261_MATRIX_TCR                  0x24
+#define AT91SAM9261_MATRIX_EBICSA               0x30
+#define AT91SAM9261_MATRIX_USBPUCR              0x34
+
+#define AT91SAM9263_MATRIX_MCFG                 0x00
+#define AT91SAM9263_MATRIX_SCFG                 0x40
+#define AT91SAM9263_MATRIX_PRS                  0x80
+#define AT91SAM9263_MATRIX_MRCR                 0x100
+#define AT91SAM9263_MATRIX_TCR                  0x114
+#define AT91SAM9263_MATRIX_EBI0CSA              0x120
+#define AT91SAM9263_MATRIX_EBI1CSA              0x124
+
+#define AT91SAM9RL_MATRIX_MCFG                  0x00
+#define AT91SAM9RL_MATRIX_SCFG                  0x40
+#define AT91SAM9RL_MATRIX_PRS                   0x80
+#define AT91SAM9RL_MATRIX_MRCR                  0x100
+#define AT91SAM9RL_MATRIX_TCR                   0x114
+#define AT91SAM9RL_MATRIX_EBICSA                0x120
+
+#define AT91SAM9G45_MATRIX_MCFG                 0x00
+#define AT91SAM9G45_MATRIX_SCFG                 0x40
+#define AT91SAM9G45_MATRIX_PRS                  0x80
+#define AT91SAM9G45_MATRIX_MRCR                 0x100
+#define AT91SAM9G45_MATRIX_TCR                  0x110
+#define AT91SAM9G45_MATRIX_DDRMPR               0x118
+#define AT91SAM9G45_MATRIX_EBICSA               0x128
+
+#define AT91SAM9N12_MATRIX_MCFG                 0x00
+#define AT91SAM9N12_MATRIX_SCFG                 0x40
+#define AT91SAM9N12_MATRIX_PRS                  0x80
+#define AT91SAM9N12_MATRIX_MRCR                 0x100
+#define AT91SAM9N12_MATRIX_EBICSA               0x118
+
+#define AT91SAM9X5_MATRIX_MCFG                  0x00
+#define AT91SAM9X5_MATRIX_SCFG                  0x40
+#define AT91SAM9X5_MATRIX_PRS                   0x80
+#define AT91SAM9X5_MATRIX_MRCR                  0x100
+#define AT91SAM9X5_MATRIX_EBICSA                0x120
+
+#define SAMA5D3_MATRIX_MCFG                     0x00
+#define SAMA5D3_MATRIX_SCFG                     0x40
+#define SAMA5D3_MATRIX_PRS                      0x80
+#define SAMA5D3_MATRIX_MRCR                     0x100
+
+#define AT91_MATRIX_MCFG(o, x)                  ((o) + ((x) * 0x4))
+#define AT91_MATRIX_ULBT                        GENMASK(2, 0)
+#define AT91_MATRIX_ULBT_INFINITE               (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE                 (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR                   (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT                  (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN                (4 << 0)
+
+#define AT91_MATRIX_SCFG(o, x)                  ((o) + ((x) * 0x4))
+#define AT91_MATRIX_SLOT_CYCLE                  GENMASK(7,  0)
+#define AT91_MATRIX_DEFMSTR_TYPE                GENMASK(17, 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE           (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST           (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED          (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR               GENMASK(20, 18)
+#define AT91_MATRIX_ARBT                        GENMASK(25, 24)
+#define AT91_MATRIX_ARBT_ROUND_ROBIN            (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY         (1 << 24)
+
+#define AT91_MATRIX_ITCM_SIZE                   GENMASK(3, 0)
+#define AT91_MATRIX_ITCM_0                      (0 << 0)
+#define AT91_MATRIX_ITCM_16                     (5 << 0)
+#define AT91_MATRIX_ITCM_32                     (6 << 0)
+#define AT91_MATRIX_ITCM_64                     (7 << 0)
+#define AT91_MATRIX_DTCM_SIZE                   GENMASK(7, 4)
+#define AT91_MATRIX_DTCM_0                      (0 << 4)
+#define AT91_MATRIX_DTCM_16                     (5 << 4)
+#define AT91_MATRIX_DTCM_32                     (6 << 4)
+#define AT91_MATRIX_DTCM_64                     (7 << 4)
+
+#define AT91_MATRIX_PRAS(o, x)                  ((o) + ((x) * 0x8))
+#define AT91_MATRIX_PRBS(o, x)                  ((o) + ((x) * 0x8) + 0x4)
+#define AT91_MATRIX_MPR(x)                      GENMASK(((x) * 0x4) + 1, ((x) * 0x4))
+
+#define AT91_MATRIX_RCB(x)                      BIT(x)
+
+#define AT91_MATRIX_CSA(cs, val)                (val << (cs))
+#define AT91_MATRIX_DBPUC                       BIT(8)
+#define AT91_MATRIX_DBPDC                       BIT(9)
+#define AT91_MATRIX_VDDIOMSEL                   BIT(16)
+#define AT91_MATRIX_VDDIOMSEL_1_8V              (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V              (1 << 16)
+#define AT91_MATRIX_EBI_IOSR                    BIT(17)
+#define AT91_MATRIX_DDR_IOSR                    BIT(18)
+#define AT91_MATRIX_NFD0_SELECT                 BIT(24)
+#define AT91_MATRIX_DDR_MP_EN                   BIT(25)
+#define AT91_MATRIX_EBI_NUM_CS                  8
+
+#define AT91_MATRIX_USBPUCR_PUON                BIT(30)
+
+#endif /* _LINUX_MFD_SYSCON_ATMEL_MATRIX_H */
diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h
new file mode 100644
index 000000000000..be6ebe64eebe
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-smc.h
@@ -0,0 +1,173 @@
+/*
+ * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
+ *
+ * Copyright (C) 2014 Atmel
+ * Copyright (C) 2014 Free Electrons
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
+#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
+
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#define AT91SAM9_SMC_GENERIC            0x00
+#define AT91SAM9_SMC_GENERIC_BLK_SZ     0x10
+
+#define SAMA5_SMC_GENERIC               0x600
+#define SAMA5_SMC_GENERIC_BLK_SZ        0x14
+
+#define AT91SAM9_SMC_SETUP(o)           ((o) + 0x00)
+#define AT91SAM9_SMC_NWESETUP(x)        (x)
+#define AT91SAM9_SMC_NCS_WRSETUP(x)     ((x) << 8)
+#define AT91SAM9_SMC_NRDSETUP(x)        ((x) << 16)
+#define AT91SAM9_SMC_NCS_NRDSETUP(x)    ((x) << 24)
+
+#define AT91SAM9_SMC_PULSE(o)           ((o) + 0x04)
+#define AT91SAM9_SMC_NWEPULSE(x)        (x)
+#define AT91SAM9_SMC_NCS_WRPULSE(x)     ((x) << 8)
+#define AT91SAM9_SMC_NRDPULSE(x)        ((x) << 16)
+#define AT91SAM9_SMC_NCS_NRDPULSE(x)    ((x) << 24)
+
+#define AT91SAM9_SMC_CYCLE(o)           ((o) + 0x08)
+#define AT91SAM9_SMC_NWECYCLE(x)        (x)
+#define AT91SAM9_SMC_NRDCYCLE(x)        ((x) << 16)
+
+#define AT91SAM9_SMC_MODE(o)            ((o) + 0x0c)
+#define SAMA5_SMC_MODE(o)               ((o) + 0x10)
+#define AT91_SMC_READMODE               BIT(0)
+#define AT91_SMC_READMODE_NCS           (0 << 0)
+#define AT91_SMC_READMODE_NRD           (1 << 0)
+#define AT91_SMC_WRITEMODE              BIT(1)
+#define AT91_SMC_WRITEMODE_NCS          (0 << 1)
+#define AT91_SMC_WRITEMODE_NWE          (1 << 1)
+#define AT91_SMC_EXNWMODE               GENMASK(5, 4)
+#define AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define AT91_SMC_BAT                    BIT(8)
+#define AT91_SMC_BAT_SELECT             (0 << 8)
+#define AT91_SMC_BAT_WRITE              (1 << 8)
+#define AT91_SMC_DBW                    GENMASK(13, 12)
+#define AT91_SMC_DBW_8                  (0 << 12)
+#define AT91_SMC_DBW_16                 (1 << 12)
+#define AT91_SMC_DBW_32                 (2 << 12)
+#define AT91_SMC_TDF                    GENMASK(19, 16)
+#define AT91_SMC_TDF_(x)                ((((x) - 1) << 16) & AT91_SMC_TDF)
+#define AT91_SMC_TDF_MAX                16
+#define AT91_SMC_TDFMODE_OPTIMIZED      BIT(20)
+#define AT91_SMC_PMEN                   BIT(24)
+#define AT91_SMC_PS                     GENMASK(29, 28)
+#define AT91_SMC_PS_4                   (0 << 28)
+#define AT91_SMC_PS_8                   (1 << 28)
+#define AT91_SMC_PS_16                  (2 << 28)
+#define AT91_SMC_PS_32                  (3 << 28)
+
+
+/*
+ * This function converts a setup timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_SETUP register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Setup Register"):
+ *
+ * setup length = (128* SETUP[5] + SETUP[4:0])
+ *
+ * where setup length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,
+                                                  u32 timing_ns)
+{
+        u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+        u32 coded_cycles = 0;
+        u32 cycles;
+
+        cycles = DIV_ROUND_UP(timing_ns, clk_period);
+        if (cycles / 32) {
+                coded_cycles |= 1 << 5;
+                if (cycles < 128)
+                        cycles = 0;
+        }
+
+        coded_cycles |= cycles % 32;
+
+        return coded_cycles;
+}
+
+/*
+ * This function converts a pulse timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_PULSE register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Pulse Register"):
+ *
+ * pulse length = (256* PULSE[6] + PULSE[5:0])
+ *
+ * where pulse length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate,
+                                                  u32 timing_ns)
+{
+        u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+        u32 coded_cycles = 0;
+        u32 cycles;
+
+        cycles = DIV_ROUND_UP(timing_ns, clk_period);
+        if (cycles / 64) {
+                coded_cycles |= 1 << 6;
+                if (cycles < 256)
+                        cycles = 0;
+        }
+
+        coded_cycles |= cycles % 64;
+
+        return coded_cycles;
+}
+
+/*
+ * This function converts a cycle timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_CYCLE register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Cycle Register"):
+ *
+ * cycle length = (CYCLE[8:7]*256 + CYCLE[6:0])
+ *
+ * where cycle length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,
+                                                  u32 timing_ns)
+{
+        u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+        u32 coded_cycles = 0;
+        u32 cycles;
+
+        cycles = DIV_ROUND_UP(timing_ns, clk_period);
+        if (cycles / 128) {
+                coded_cycles = cycles / 256;
+                cycles %= 256;
+                if (cycles >= 128) {
+                        coded_cycles++;
+                        cycles = 0;
+                }
+
+                if (coded_cycles > 0x3) {
+                        coded_cycles = 0x3;
+                        cycles = 0x7f;
+                }
+
+                coded_cycles <<= 7;
+        }
+
+        coded_cycles |= cycles % 128;
+
+        return coded_cycles;
+}
+
+#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */