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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-01 19:13:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-01 19:13:21 -0400
commit675c354a95d5375153b8bb80a0448cab916c7991 (patch)
tree88cbc5a5a31dd1c1016271006a8d56cfe0abf7bd /include/linux
parentc70929147a10fa4538886cb23b934b509c4c0e49 (diff)
parent1b3fa22e0234d613df967445cd34807e10fa54fa (diff)
Merge tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver patches from Greg KH: "Here's the big char/misc driver updates for 3.15-rc1. Lots of various things here, including the new mcb driver subsystem. All of these have been in linux-next for a while" * tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (118 commits) extcon: Move OF helper function to extcon core and change function name extcon: of: Remove unnecessary function call by using the name of device_node extcon: gpio: Use SIMPLE_DEV_PM_OPS macro extcon: palmas: Use SIMPLE_DEV_PM_OPS macro mei: don't use deprecated DEFINE_PCI_DEVICE_TABLE macro mei: amthif: fix checkpatch error mei: client.h fix checkpatch errors mei: use cl_dbg where appropriate mei: fix Unnecessary space after function pointer name mei: report consistently copy_from/to_user failures mei: drop pr_fmt macros mei: make me hw headers private to me hw. mei: fix memory leak of pending write cb objects mei: me: do not reset when less than expected data is received drivers: mcb: Fix build error discovered by 0-day bot cs5535-mfgpt: Simplify dependencies spmi: pm: drop bus-level PM suspend/resume routines spmi: pmic_arb: make selectable on ARCH_QCOM Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle pch_phub: Report error writing MAC back to user ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/connector.h2
-rw-r--r--include/linux/extcon.h12
-rw-r--r--include/linux/extcon/of_extcon.h31
-rw-r--r--include/linux/fmc-sdb.h2
-rw-r--r--include/linux/fsl_ifc.h838
-rw-r--r--include/linux/hyperv.h353
-rw-r--r--include/linux/mcb.h119
-rw-r--r--include/linux/miscdevice.h16
-rw-r--r--include/linux/mod_devicetable.h13
-rw-r--r--include/linux/regmap.h12
-rw-r--r--include/linux/spmi.h191
11 files changed, 1223 insertions, 366 deletions
diff --git a/include/linux/connector.h b/include/linux/connector.h
index b2b5a41b6a24..be9c4747d511 100644
--- a/include/linux/connector.h
+++ b/include/linux/connector.h
@@ -71,7 +71,7 @@ struct cn_dev {
71int cn_add_callback(struct cb_id *id, const char *name, 71int cn_add_callback(struct cb_id *id, const char *name,
72 void (*callback)(struct cn_msg *, struct netlink_skb_parms *)); 72 void (*callback)(struct cn_msg *, struct netlink_skb_parms *));
73void cn_del_callback(struct cb_id *); 73void cn_del_callback(struct cb_id *);
74int cn_netlink_send(struct cn_msg *, u32, gfp_t); 74int cn_netlink_send(struct cn_msg *msg, u32 portid, u32 group, gfp_t gfp_mask);
75 75
76int cn_queue_add_callback(struct cn_queue_dev *dev, const char *name, 76int cn_queue_add_callback(struct cn_queue_dev *dev, const char *name,
77 struct cb_id *id, 77 struct cb_id *id,
diff --git a/include/linux/extcon.h b/include/linux/extcon.h
index 21c59af1150b..f488145bb2d4 100644
--- a/include/linux/extcon.h
+++ b/include/linux/extcon.h
@@ -240,6 +240,12 @@ extern int extcon_register_notifier(struct extcon_dev *edev,
240 struct notifier_block *nb); 240 struct notifier_block *nb);
241extern int extcon_unregister_notifier(struct extcon_dev *edev, 241extern int extcon_unregister_notifier(struct extcon_dev *edev,
242 struct notifier_block *nb); 242 struct notifier_block *nb);
243
244/*
245 * Following API get the extcon device from devicetree.
246 * This function use phandle of devicetree to get extcon device directly.
247 */
248extern struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index);
243#else /* CONFIG_EXTCON */ 249#else /* CONFIG_EXTCON */
244static inline int extcon_dev_register(struct extcon_dev *edev) 250static inline int extcon_dev_register(struct extcon_dev *edev)
245{ 251{
@@ -324,5 +330,11 @@ static inline int extcon_unregister_interest(struct extcon_specific_cable_nb
324{ 330{
325 return 0; 331 return 0;
326} 332}
333
334static inline struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev,
335 int index)
336{
337 return ERR_PTR(-ENODEV);
338}
327#endif /* CONFIG_EXTCON */ 339#endif /* CONFIG_EXTCON */
328#endif /* __LINUX_EXTCON_H__ */ 340#endif /* __LINUX_EXTCON_H__ */
diff --git a/include/linux/extcon/of_extcon.h b/include/linux/extcon/of_extcon.h
deleted file mode 100644
index 0ebfeff1b55d..000000000000
--- a/include/linux/extcon/of_extcon.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * OF helpers for External connector (extcon) framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 * Kishon Vijay Abraham I <kishon@ti.com>
6 *
7 * Copyright (C) 2013 Samsung Electronics
8 * Chanwoo Choi <cw00.choi@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef __LINUX_OF_EXTCON_H
17#define __LINUX_OF_EXTCON_H
18
19#include <linux/err.h>
20
21#if IS_ENABLED(CONFIG_OF_EXTCON)
22extern struct extcon_dev
23 *of_extcon_get_extcon_dev(struct device *dev, int index);
24#else
25static inline struct extcon_dev
26 *of_extcon_get_extcon_dev(struct device *dev, int index)
27{
28 return ERR_PTR(-ENOSYS);
29}
30#endif /* CONFIG_OF_EXTCON */
31#endif /* __LINUX_OF_EXTCON_H */
diff --git a/include/linux/fmc-sdb.h b/include/linux/fmc-sdb.h
index 1974317a9b3d..599bd6bab56d 100644
--- a/include/linux/fmc-sdb.h
+++ b/include/linux/fmc-sdb.h
@@ -14,6 +14,8 @@ union sdb_record {
14 struct sdb_bridge bridge; 14 struct sdb_bridge bridge;
15 struct sdb_integration integr; 15 struct sdb_integration integr;
16 struct sdb_empty empty; 16 struct sdb_empty empty;
17 struct sdb_synthesis synthesis;
18 struct sdb_repo_url repo_url;
17}; 19};
18 20
19struct fmc_device; 21struct fmc_device;
diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
new file mode 100644
index 000000000000..f49ddb1b2273
--- /dev/null
+++ b/include/linux/fsl_ifc.h
@@ -0,0 +1,838 @@
1/* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_FSL_IFC_H
23#define __ASM_FSL_IFC_H
24
25#include <linux/compiler.h>
26#include <linux/types.h>
27#include <linux/io.h>
28
29#include <linux/of_platform.h>
30#include <linux/interrupt.h>
31
32#define FSL_IFC_BANK_COUNT 4
33
34/*
35 * CSPR - Chip Select Property Register
36 */
37#define CSPR_BA 0xFFFF0000
38#define CSPR_BA_SHIFT 16
39#define CSPR_PORT_SIZE 0x00000180
40#define CSPR_PORT_SIZE_SHIFT 7
41/* Port Size 8 bit */
42#define CSPR_PORT_SIZE_8 0x00000080
43/* Port Size 16 bit */
44#define CSPR_PORT_SIZE_16 0x00000100
45/* Port Size 32 bit */
46#define CSPR_PORT_SIZE_32 0x00000180
47/* Write Protect */
48#define CSPR_WP 0x00000040
49#define CSPR_WP_SHIFT 6
50/* Machine Select */
51#define CSPR_MSEL 0x00000006
52#define CSPR_MSEL_SHIFT 1
53/* NOR */
54#define CSPR_MSEL_NOR 0x00000000
55/* NAND */
56#define CSPR_MSEL_NAND 0x00000002
57/* GPCM */
58#define CSPR_MSEL_GPCM 0x00000004
59/* Bank Valid */
60#define CSPR_V 0x00000001
61#define CSPR_V_SHIFT 0
62
63/*
64 * Address Mask Register
65 */
66#define IFC_AMASK_MASK 0xFFFF0000
67#define IFC_AMASK_SHIFT 16
68#define IFC_AMASK(n) (IFC_AMASK_MASK << \
69 (__ilog2(n) - IFC_AMASK_SHIFT))
70
71/*
72 * Chip Select Option Register IFC_NAND Machine
73 */
74/* Enable ECC Encoder */
75#define CSOR_NAND_ECC_ENC_EN 0x80000000
76#define CSOR_NAND_ECC_MODE_MASK 0x30000000
77/* 4 bit correction per 520 Byte sector */
78#define CSOR_NAND_ECC_MODE_4 0x00000000
79/* 8 bit correction per 528 Byte sector */
80#define CSOR_NAND_ECC_MODE_8 0x10000000
81/* Enable ECC Decoder */
82#define CSOR_NAND_ECC_DEC_EN 0x04000000
83/* Row Address Length */
84#define CSOR_NAND_RAL_MASK 0x01800000
85#define CSOR_NAND_RAL_SHIFT 20
86#define CSOR_NAND_RAL_1 0x00000000
87#define CSOR_NAND_RAL_2 0x00800000
88#define CSOR_NAND_RAL_3 0x01000000
89#define CSOR_NAND_RAL_4 0x01800000
90/* Page Size 512b, 2k, 4k */
91#define CSOR_NAND_PGS_MASK 0x00180000
92#define CSOR_NAND_PGS_SHIFT 16
93#define CSOR_NAND_PGS_512 0x00000000
94#define CSOR_NAND_PGS_2K 0x00080000
95#define CSOR_NAND_PGS_4K 0x00100000
96#define CSOR_NAND_PGS_8K 0x00180000
97/* Spare region Size */
98#define CSOR_NAND_SPRZ_MASK 0x0000E000
99#define CSOR_NAND_SPRZ_SHIFT 13
100#define CSOR_NAND_SPRZ_16 0x00000000
101#define CSOR_NAND_SPRZ_64 0x00002000
102#define CSOR_NAND_SPRZ_128 0x00004000
103#define CSOR_NAND_SPRZ_210 0x00006000
104#define CSOR_NAND_SPRZ_218 0x00008000
105#define CSOR_NAND_SPRZ_224 0x0000A000
106#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
107/* Pages Per Block */
108#define CSOR_NAND_PB_MASK 0x00000700
109#define CSOR_NAND_PB_SHIFT 8
110#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111/* Time for Read Enable High to Output High Impedance */
112#define CSOR_NAND_TRHZ_MASK 0x0000001C
113#define CSOR_NAND_TRHZ_SHIFT 2
114#define CSOR_NAND_TRHZ_20 0x00000000
115#define CSOR_NAND_TRHZ_40 0x00000004
116#define CSOR_NAND_TRHZ_60 0x00000008
117#define CSOR_NAND_TRHZ_80 0x0000000C
118#define CSOR_NAND_TRHZ_100 0x00000010
119/* Buffer control disable */
120#define CSOR_NAND_BCTLD 0x00000001
121
122/*
123 * Chip Select Option Register - NOR Flash Mode
124 */
125/* Enable Address shift Mode */
126#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
127/* Page Read Enable from NOR device */
128#define CSOR_NOR_PGRD_EN 0x10000000
129/* AVD Toggle Enable during Burst Program */
130#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
131/* Address Data Multiplexing Shift */
132#define CSOR_NOR_ADM_MASK 0x0003E000
133#define CSOR_NOR_ADM_SHIFT_SHIFT 13
134#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
135/* Type of the NOR device hooked */
136#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
137#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
138/* Time for Read Enable High to Output High Impedance */
139#define CSOR_NOR_TRHZ_MASK 0x0000001C
140#define CSOR_NOR_TRHZ_SHIFT 2
141#define CSOR_NOR_TRHZ_20 0x00000000
142#define CSOR_NOR_TRHZ_40 0x00000004
143#define CSOR_NOR_TRHZ_60 0x00000008
144#define CSOR_NOR_TRHZ_80 0x0000000C
145#define CSOR_NOR_TRHZ_100 0x00000010
146/* Buffer control disable */
147#define CSOR_NOR_BCTLD 0x00000001
148
149/*
150 * Chip Select Option Register - GPCM Mode
151 */
152/* GPCM Mode - Normal */
153#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
154/* GPCM Mode - GenericASIC */
155#define CSOR_GPCM_GPMODE_ASIC 0x80000000
156/* Parity Mode odd/even */
157#define CSOR_GPCM_PARITY_EVEN 0x40000000
158/* Parity Checking enable/disable */
159#define CSOR_GPCM_PAR_EN 0x20000000
160/* GPCM Timeout Count */
161#define CSOR_GPCM_GPTO_MASK 0x0F000000
162#define CSOR_GPCM_GPTO_SHIFT 24
163#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
164/* GPCM External Access Termination mode for read access */
165#define CSOR_GPCM_RGETA_EXT 0x00080000
166/* GPCM External Access Termination mode for write access */
167#define CSOR_GPCM_WGETA_EXT 0x00040000
168/* Address Data Multiplexing Shift */
169#define CSOR_GPCM_ADM_MASK 0x0003E000
170#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
171#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
172/* Generic ASIC Parity error indication delay */
173#define CSOR_GPCM_GAPERRD_MASK 0x00000180
174#define CSOR_GPCM_GAPERRD_SHIFT 7
175#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
176/* Time for Read Enable High to Output High Impedance */
177#define CSOR_GPCM_TRHZ_MASK 0x0000001C
178#define CSOR_GPCM_TRHZ_20 0x00000000
179#define CSOR_GPCM_TRHZ_40 0x00000004
180#define CSOR_GPCM_TRHZ_60 0x00000008
181#define CSOR_GPCM_TRHZ_80 0x0000000C
182#define CSOR_GPCM_TRHZ_100 0x00000010
183/* Buffer control disable */
184#define CSOR_GPCM_BCTLD 0x00000001
185
186/*
187 * Ready Busy Status Register (RB_STAT)
188 */
189/* CSn is READY */
190#define IFC_RB_STAT_READY_CS0 0x80000000
191#define IFC_RB_STAT_READY_CS1 0x40000000
192#define IFC_RB_STAT_READY_CS2 0x20000000
193#define IFC_RB_STAT_READY_CS3 0x10000000
194
195/*
196 * General Control Register (GCR)
197 */
198#define IFC_GCR_MASK 0x8000F800
199/* reset all IFC hardware */
200#define IFC_GCR_SOFT_RST_ALL 0x80000000
201/* Turnaroud Time of external buffer */
202#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
203#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
204
205/*
206 * Common Event and Error Status Register (CM_EVTER_STAT)
207 */
208/* Chip select error */
209#define IFC_CM_EVTER_STAT_CSER 0x80000000
210
211/*
212 * Common Event and Error Enable Register (CM_EVTER_EN)
213 */
214/* Chip select error checking enable */
215#define IFC_CM_EVTER_EN_CSEREN 0x80000000
216
217/*
218 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
219 */
220/* Chip select error interrupt enable */
221#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
222
223/*
224 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
225 */
226/* transaction type of error Read/Write */
227#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
228#define IFC_CM_ERATTR0_ERAID 0x0FF00000
229#define IFC_CM_ERATTR0_ERAID_SHIFT 20
230#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
231#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
232
233/*
234 * Clock Control Register (CCR)
235 */
236#define IFC_CCR_MASK 0x0F0F8800
237/* Clock division ratio */
238#define IFC_CCR_CLK_DIV_MASK 0x0F000000
239#define IFC_CCR_CLK_DIV_SHIFT 24
240#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
241/* IFC Clock Delay */
242#define IFC_CCR_CLK_DLY_MASK 0x000F0000
243#define IFC_CCR_CLK_DLY_SHIFT 16
244#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
245/* Invert IFC clock before sending out */
246#define IFC_CCR_INV_CLK_EN 0x00008000
247/* Fedback IFC Clock */
248#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
249
250/*
251 * Clock Status Register (CSR)
252 */
253/* Clk is stable */
254#define IFC_CSR_CLK_STAT_STABLE 0x80000000
255
256/*
257 * IFC_NAND Machine Specific Registers
258 */
259/*
260 * NAND Configuration Register (NCFGR)
261 */
262/* Auto Boot Mode */
263#define IFC_NAND_NCFGR_BOOT 0x80000000
264/* Addressing Mode-ROW0+n/COL0 */
265#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
266/* Addressing Mode-ROW0+n/COL0+n */
267#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
268/* Number of loop iterations of FIR sequences for multi page operations */
269#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
270#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
271#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
272/* Number of wait cycles */
273#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
274#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
275
276/*
277 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
278 */
279/* General purpose FCM flash command bytes CMD0-CMD7 */
280#define IFC_NAND_FCR0_CMD0 0xFF000000
281#define IFC_NAND_FCR0_CMD0_SHIFT 24
282#define IFC_NAND_FCR0_CMD1 0x00FF0000
283#define IFC_NAND_FCR0_CMD1_SHIFT 16
284#define IFC_NAND_FCR0_CMD2 0x0000FF00
285#define IFC_NAND_FCR0_CMD2_SHIFT 8
286#define IFC_NAND_FCR0_CMD3 0x000000FF
287#define IFC_NAND_FCR0_CMD3_SHIFT 0
288#define IFC_NAND_FCR1_CMD4 0xFF000000
289#define IFC_NAND_FCR1_CMD4_SHIFT 24
290#define IFC_NAND_FCR1_CMD5 0x00FF0000
291#define IFC_NAND_FCR1_CMD5_SHIFT 16
292#define IFC_NAND_FCR1_CMD6 0x0000FF00
293#define IFC_NAND_FCR1_CMD6_SHIFT 8
294#define IFC_NAND_FCR1_CMD7 0x000000FF
295#define IFC_NAND_FCR1_CMD7_SHIFT 0
296
297/*
298 * Flash ROW and COL Address Register (ROWn, COLn)
299 */
300/* Main/spare region locator */
301#define IFC_NAND_COL_MS 0x80000000
302/* Column Address */
303#define IFC_NAND_COL_CA_MASK 0x00000FFF
304
305/*
306 * NAND Flash Byte Count Register (NAND_BC)
307 */
308/* Byte Count for read/Write */
309#define IFC_NAND_BC 0x000001FF
310
311/*
312 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
313 */
314/* NAND Machine specific opcodes OP0-OP14*/
315#define IFC_NAND_FIR0_OP0 0xFC000000
316#define IFC_NAND_FIR0_OP0_SHIFT 26
317#define IFC_NAND_FIR0_OP1 0x03F00000
318#define IFC_NAND_FIR0_OP1_SHIFT 20
319#define IFC_NAND_FIR0_OP2 0x000FC000
320#define IFC_NAND_FIR0_OP2_SHIFT 14
321#define IFC_NAND_FIR0_OP3 0x00003F00
322#define IFC_NAND_FIR0_OP3_SHIFT 8
323#define IFC_NAND_FIR0_OP4 0x000000FC
324#define IFC_NAND_FIR0_OP4_SHIFT 2
325#define IFC_NAND_FIR1_OP5 0xFC000000
326#define IFC_NAND_FIR1_OP5_SHIFT 26
327#define IFC_NAND_FIR1_OP6 0x03F00000
328#define IFC_NAND_FIR1_OP6_SHIFT 20
329#define IFC_NAND_FIR1_OP7 0x000FC000
330#define IFC_NAND_FIR1_OP7_SHIFT 14
331#define IFC_NAND_FIR1_OP8 0x00003F00
332#define IFC_NAND_FIR1_OP8_SHIFT 8
333#define IFC_NAND_FIR1_OP9 0x000000FC
334#define IFC_NAND_FIR1_OP9_SHIFT 2
335#define IFC_NAND_FIR2_OP10 0xFC000000
336#define IFC_NAND_FIR2_OP10_SHIFT 26
337#define IFC_NAND_FIR2_OP11 0x03F00000
338#define IFC_NAND_FIR2_OP11_SHIFT 20
339#define IFC_NAND_FIR2_OP12 0x000FC000
340#define IFC_NAND_FIR2_OP12_SHIFT 14
341#define IFC_NAND_FIR2_OP13 0x00003F00
342#define IFC_NAND_FIR2_OP13_SHIFT 8
343#define IFC_NAND_FIR2_OP14 0x000000FC
344#define IFC_NAND_FIR2_OP14_SHIFT 2
345
346/*
347 * Instruction opcodes to be programmed
348 * in FIR registers- 6bits
349 */
350enum ifc_nand_fir_opcodes {
351 IFC_FIR_OP_NOP,
352 IFC_FIR_OP_CA0,
353 IFC_FIR_OP_CA1,
354 IFC_FIR_OP_CA2,
355 IFC_FIR_OP_CA3,
356 IFC_FIR_OP_RA0,
357 IFC_FIR_OP_RA1,
358 IFC_FIR_OP_RA2,
359 IFC_FIR_OP_RA3,
360 IFC_FIR_OP_CMD0,
361 IFC_FIR_OP_CMD1,
362 IFC_FIR_OP_CMD2,
363 IFC_FIR_OP_CMD3,
364 IFC_FIR_OP_CMD4,
365 IFC_FIR_OP_CMD5,
366 IFC_FIR_OP_CMD6,
367 IFC_FIR_OP_CMD7,
368 IFC_FIR_OP_CW0,
369 IFC_FIR_OP_CW1,
370 IFC_FIR_OP_CW2,
371 IFC_FIR_OP_CW3,
372 IFC_FIR_OP_CW4,
373 IFC_FIR_OP_CW5,
374 IFC_FIR_OP_CW6,
375 IFC_FIR_OP_CW7,
376 IFC_FIR_OP_WBCD,
377 IFC_FIR_OP_RBCD,
378 IFC_FIR_OP_BTRD,
379 IFC_FIR_OP_RDSTAT,
380 IFC_FIR_OP_NWAIT,
381 IFC_FIR_OP_WFR,
382 IFC_FIR_OP_SBRD,
383 IFC_FIR_OP_UA,
384 IFC_FIR_OP_RB,
385};
386
387/*
388 * NAND Chip Select Register (NAND_CSEL)
389 */
390#define IFC_NAND_CSEL 0x0C000000
391#define IFC_NAND_CSEL_SHIFT 26
392#define IFC_NAND_CSEL_CS0 0x00000000
393#define IFC_NAND_CSEL_CS1 0x04000000
394#define IFC_NAND_CSEL_CS2 0x08000000
395#define IFC_NAND_CSEL_CS3 0x0C000000
396
397/*
398 * NAND Operation Sequence Start (NANDSEQ_STRT)
399 */
400/* NAND Flash Operation Start */
401#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
402/* Automatic Erase */
403#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
404/* Automatic Program */
405#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
406/* Automatic Copyback */
407#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
408/* Automatic Read Operation */
409#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
410/* Automatic Status Read */
411#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
412
413/*
414 * NAND Event and Error Status Register (NAND_EVTER_STAT)
415 */
416/* Operation Complete */
417#define IFC_NAND_EVTER_STAT_OPC 0x80000000
418/* Flash Timeout Error */
419#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
420/* Write Protect Error */
421#define IFC_NAND_EVTER_STAT_WPER 0x04000000
422/* ECC Error */
423#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
424/* RCW Load Done */
425#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
426/* Boot Loadr Done */
427#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
428/* Bad Block Indicator search select */
429#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
430
431/*
432 * NAND Flash Page Read Completion Event Status Register
433 * (PGRDCMPL_EVT_STAT)
434 */
435#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
436/* Small Page 0-15 Done */
437#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
438/* Large Page(2K) 0-3 Done */
439#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
440/* Large Page(4K) 0-1 Done */
441#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
442
443/*
444 * NAND Event and Error Enable Register (NAND_EVTER_EN)
445 */
446/* Operation complete event enable */
447#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
448/* Page read complete event enable */
449#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
450/* Flash Timeout error enable */
451#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
452/* Write Protect error enable */
453#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
454/* ECC error logging enable */
455#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
456
457/*
458 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
459 */
460/* Enable interrupt for operation complete */
461#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
462/* Enable interrupt for Page read complete */
463#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
464/* Enable interrupt for Flash timeout error */
465#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
466/* Enable interrupt for Write protect error */
467#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
468/* Enable interrupt for ECC error*/
469#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
470
471/*
472 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
473 */
474#define IFC_NAND_ERATTR0_MASK 0x0C080000
475/* Error on CS0-3 for NAND */
476#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
477#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
478#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
479#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
480/* Transaction type of error Read/Write */
481#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
482
483/*
484 * NAND Flash Status Register (NAND_FSR)
485 */
486/* First byte of data read from read status op */
487#define IFC_NAND_NFSR_RS0 0xFF000000
488/* Second byte of data read from read status op */
489#define IFC_NAND_NFSR_RS1 0x00FF0000
490
491/*
492 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
493 */
494/* Number of ECC errors on sector n (n = 0-15) */
495#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
496#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
497#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
498#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
499#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
500#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
501#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
502#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
503#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
504#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
505#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
506#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
507#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
508#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
509#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
510#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
511#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
512#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
513#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
514#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
515#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
516#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
517#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
518#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
519#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
520#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
521#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
522#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
523#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
524#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
525#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
526#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
527
528/*
529 * NAND Control Register (NANDCR)
530 */
531#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
532#define IFC_NAND_NCR_FTOCNT_SHIFT 25
533#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
534
535/*
536 * NAND_AUTOBOOT_TRGR
537 */
538/* Trigger RCW load */
539#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
540/* Trigget Auto Boot */
541#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
542
543/*
544 * NAND_MDR
545 */
546/* 1st read data byte when opcode SBRD */
547#define IFC_NAND_MDR_RDATA0 0xFF000000
548/* 2nd read data byte when opcode SBRD */
549#define IFC_NAND_MDR_RDATA1 0x00FF0000
550
551/*
552 * NOR Machine Specific Registers
553 */
554/*
555 * NOR Event and Error Status Register (NOR_EVTER_STAT)
556 */
557/* NOR Command Sequence Operation Complete */
558#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
559/* Write Protect Error */
560#define IFC_NOR_EVTER_STAT_WPER 0x04000000
561/* Command Sequence Timeout Error */
562#define IFC_NOR_EVTER_STAT_STOER 0x01000000
563
564/*
565 * NOR Event and Error Enable Register (NOR_EVTER_EN)
566 */
567/* NOR Command Seq complete event enable */
568#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
569/* Write Protect Error Checking Enable */
570#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
571/* Timeout Error Enable */
572#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
573
574/*
575 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
576 */
577/* Enable interrupt for OPC complete */
578#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
579/* Enable interrupt for write protect error */
580#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
581/* Enable interrupt for timeout error */
582#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
583
584/*
585 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
586 */
587/* Source ID for error transaction */
588#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
589/* AXI ID for error transation */
590#define IFC_NOR_ERATTR0_ERAID 0x000FF000
591/* Chip select corresponds to NOR error */
592#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
593#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
594#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
595#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
596/* Type of transaction read/write */
597#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
598
599/*
600 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
601 */
602#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
603#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
604
605/*
606 * NOR Control Register (NORCR)
607 */
608#define IFC_NORCR_MASK 0x0F0F0000
609/* No. of Address/Data Phase */
610#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
611#define IFC_NORCR_NUM_PHASE_SHIFT 24
612#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
613/* Sequence Timeout Count */
614#define IFC_NORCR_STOCNT_MASK 0x000F0000
615#define IFC_NORCR_STOCNT_SHIFT 16
616#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
617
618/*
619 * GPCM Machine specific registers
620 */
621/*
622 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
623 */
624/* Timeout error */
625#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
626/* Parity error */
627#define IFC_GPCM_EVTER_STAT_PER 0x01000000
628
629/*
630 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
631 */
632/* Timeout error enable */
633#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
634/* Parity error enable */
635#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
636
637/*
638 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
639 */
640/* Enable Interrupt for timeout error */
641#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
642/* Enable Interrupt for Parity error */
643#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
644
645/*
646 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
647 */
648/* Source ID for error transaction */
649#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
650/* AXI ID for error transaction */
651#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
652/* Chip select corresponds to GPCM error */
653#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
654#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
655#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
656#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
657/* Type of transaction read/Write */
658#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
659
660/*
661 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
662 */
663/* On which beat of address/data parity error is observed */
664#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
665/* Parity Error on byte */
666#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
667/* Parity Error reported in addr or data phase */
668#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
669
670/*
671 * GPCM Status Register (GPCM_STAT)
672 */
673#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
674
675/*
676 * IFC Controller NAND Machine registers
677 */
678struct fsl_ifc_nand {
679 __be32 ncfgr;
680 u32 res1[0x4];
681 __be32 nand_fcr0;
682 __be32 nand_fcr1;
683 u32 res2[0x8];
684 __be32 row0;
685 u32 res3;
686 __be32 col0;
687 u32 res4;
688 __be32 row1;
689 u32 res5;
690 __be32 col1;
691 u32 res6;
692 __be32 row2;
693 u32 res7;
694 __be32 col2;
695 u32 res8;
696 __be32 row3;
697 u32 res9;
698 __be32 col3;
699 u32 res10[0x24];
700 __be32 nand_fbcr;
701 u32 res11;
702 __be32 nand_fir0;
703 __be32 nand_fir1;
704 __be32 nand_fir2;
705 u32 res12[0x10];
706 __be32 nand_csel;
707 u32 res13;
708 __be32 nandseq_strt;
709 u32 res14;
710 __be32 nand_evter_stat;
711 u32 res15;
712 __be32 pgrdcmpl_evt_stat;
713 u32 res16[0x2];
714 __be32 nand_evter_en;
715 u32 res17[0x2];
716 __be32 nand_evter_intr_en;
717 u32 res18[0x2];
718 __be32 nand_erattr0;
719 __be32 nand_erattr1;
720 u32 res19[0x10];
721 __be32 nand_fsr;
722 u32 res20;
723 __be32 nand_eccstat[4];
724 u32 res21[0x20];
725 __be32 nanndcr;
726 u32 res22[0x2];
727 __be32 nand_autoboot_trgr;
728 u32 res23;
729 __be32 nand_mdr;
730 u32 res24[0x5C];
731};
732
733/*
734 * IFC controller NOR Machine registers
735 */
736struct fsl_ifc_nor {
737 __be32 nor_evter_stat;
738 u32 res1[0x2];
739 __be32 nor_evter_en;
740 u32 res2[0x2];
741 __be32 nor_evter_intr_en;
742 u32 res3[0x2];
743 __be32 nor_erattr0;
744 __be32 nor_erattr1;
745 __be32 nor_erattr2;
746 u32 res4[0x4];
747 __be32 norcr;
748 u32 res5[0xEF];
749};
750
751/*
752 * IFC controller GPCM Machine registers
753 */
754struct fsl_ifc_gpcm {
755 __be32 gpcm_evter_stat;
756 u32 res1[0x2];
757 __be32 gpcm_evter_en;
758 u32 res2[0x2];
759 __be32 gpcm_evter_intr_en;
760 u32 res3[0x2];
761 __be32 gpcm_erattr0;
762 __be32 gpcm_erattr1;
763 __be32 gpcm_erattr2;
764 __be32 gpcm_stat;
765 u32 res4[0x1F3];
766};
767
768/*
769 * IFC Controller Registers
770 */
771struct fsl_ifc_regs {
772 __be32 ifc_rev;
773 u32 res1[0x2];
774 struct {
775 __be32 cspr_ext;
776 __be32 cspr;
777 u32 res2;
778 } cspr_cs[FSL_IFC_BANK_COUNT];
779 u32 res3[0x19];
780 struct {
781 __be32 amask;
782 u32 res4[0x2];
783 } amask_cs[FSL_IFC_BANK_COUNT];
784 u32 res5[0x17];
785 struct {
786 __be32 csor_ext;
787 __be32 csor;
788 u32 res6;
789 } csor_cs[FSL_IFC_BANK_COUNT];
790 u32 res7[0x19];
791 struct {
792 __be32 ftim[4];
793 u32 res8[0x8];
794 } ftim_cs[FSL_IFC_BANK_COUNT];
795 u32 res9[0x60];
796 __be32 rb_stat;
797 u32 res10[0x2];
798 __be32 ifc_gcr;
799 u32 res11[0x2];
800 __be32 cm_evter_stat;
801 u32 res12[0x2];
802 __be32 cm_evter_en;
803 u32 res13[0x2];
804 __be32 cm_evter_intr_en;
805 u32 res14[0x2];
806 __be32 cm_erattr0;
807 __be32 cm_erattr1;
808 u32 res15[0x2];
809 __be32 ifc_ccr;
810 __be32 ifc_csr;
811 u32 res16[0x2EB];
812 struct fsl_ifc_nand ifc_nand;
813 struct fsl_ifc_nor ifc_nor;
814 struct fsl_ifc_gpcm ifc_gpcm;
815};
816
817extern unsigned int convert_ifc_address(phys_addr_t addr_base);
818extern int fsl_ifc_find(phys_addr_t addr_base);
819
820/* overview of the fsl ifc controller */
821
822struct fsl_ifc_ctrl {
823 /* device info */
824 struct device *dev;
825 struct fsl_ifc_regs __iomem *regs;
826 int irq;
827 int nand_irq;
828 spinlock_t lock;
829 void *nand;
830
831 u32 nand_stat;
832 wait_queue_head_t nand_wait;
833};
834
835extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
836
837
838#endif /* __ASM_FSL_IFC_H */
diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h
index 344883dce584..ab7359fde987 100644
--- a/include/linux/hyperv.h
+++ b/include/linux/hyperv.h
@@ -25,328 +25,11 @@
25#ifndef _HYPERV_H 25#ifndef _HYPERV_H
26#define _HYPERV_H 26#define _HYPERV_H
27 27
28#include <linux/types.h> 28#include <uapi/linux/hyperv.h>
29
30/*
31 * Framework version for util services.
32 */
33#define UTIL_FW_MINOR 0
34
35#define UTIL_WS2K8_FW_MAJOR 1
36#define UTIL_WS2K8_FW_VERSION (UTIL_WS2K8_FW_MAJOR << 16 | UTIL_FW_MINOR)
37
38#define UTIL_FW_MAJOR 3
39#define UTIL_FW_VERSION (UTIL_FW_MAJOR << 16 | UTIL_FW_MINOR)
40
41
42/*
43 * Implementation of host controlled snapshot of the guest.
44 */
45
46#define VSS_OP_REGISTER 128
47
48enum hv_vss_op {
49 VSS_OP_CREATE = 0,
50 VSS_OP_DELETE,
51 VSS_OP_HOT_BACKUP,
52 VSS_OP_GET_DM_INFO,
53 VSS_OP_BU_COMPLETE,
54 /*
55 * Following operations are only supported with IC version >= 5.0
56 */
57 VSS_OP_FREEZE, /* Freeze the file systems in the VM */
58 VSS_OP_THAW, /* Unfreeze the file systems */
59 VSS_OP_AUTO_RECOVER,
60 VSS_OP_COUNT /* Number of operations, must be last */
61};
62
63
64/*
65 * Header for all VSS messages.
66 */
67struct hv_vss_hdr {
68 __u8 operation;
69 __u8 reserved[7];
70} __attribute__((packed));
71
72
73/*
74 * Flag values for the hv_vss_check_feature. Linux supports only
75 * one value.
76 */
77#define VSS_HBU_NO_AUTO_RECOVERY 0x00000005
78
79struct hv_vss_check_feature {
80 __u32 flags;
81} __attribute__((packed));
82
83struct hv_vss_check_dm_info {
84 __u32 flags;
85} __attribute__((packed));
86
87struct hv_vss_msg {
88 union {
89 struct hv_vss_hdr vss_hdr;
90 int error;
91 };
92 union {
93 struct hv_vss_check_feature vss_cf;
94 struct hv_vss_check_dm_info dm_info;
95 };
96} __attribute__((packed));
97
98/*
99 * An implementation of HyperV key value pair (KVP) functionality for Linux.
100 *
101 *
102 * Copyright (C) 2010, Novell, Inc.
103 * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
104 *
105 */
106
107/*
108 * Maximum value size - used for both key names and value data, and includes
109 * any applicable NULL terminators.
110 *
111 * Note: This limit is somewhat arbitrary, but falls easily within what is
112 * supported for all native guests (back to Win 2000) and what is reasonable
113 * for the IC KVP exchange functionality. Note that Windows Me/98/95 are
114 * limited to 255 character key names.
115 *
116 * MSDN recommends not storing data values larger than 2048 bytes in the
117 * registry.
118 *
119 * Note: This value is used in defining the KVP exchange message - this value
120 * cannot be modified without affecting the message size and compatibility.
121 */
122
123/*
124 * bytes, including any null terminators
125 */
126#define HV_KVP_EXCHANGE_MAX_VALUE_SIZE (2048)
127
128
129/*
130 * Maximum key size - the registry limit for the length of an entry name
131 * is 256 characters, including the null terminator
132 */
133
134#define HV_KVP_EXCHANGE_MAX_KEY_SIZE (512)
135
136/*
137 * In Linux, we implement the KVP functionality in two components:
138 * 1) The kernel component which is packaged as part of the hv_utils driver
139 * is responsible for communicating with the host and responsible for
140 * implementing the host/guest protocol. 2) A user level daemon that is
141 * responsible for data gathering.
142 *
143 * Host/Guest Protocol: The host iterates over an index and expects the guest
144 * to assign a key name to the index and also return the value corresponding to
145 * the key. The host will have atmost one KVP transaction outstanding at any
146 * given point in time. The host side iteration stops when the guest returns
147 * an error. Microsoft has specified the following mapping of key names to
148 * host specified index:
149 *
150 * Index Key Name
151 * 0 FullyQualifiedDomainName
152 * 1 IntegrationServicesVersion
153 * 2 NetworkAddressIPv4
154 * 3 NetworkAddressIPv6
155 * 4 OSBuildNumber
156 * 5 OSName
157 * 6 OSMajorVersion
158 * 7 OSMinorVersion
159 * 8 OSVersion
160 * 9 ProcessorArchitecture
161 *
162 * The Windows host expects the Key Name and Key Value to be encoded in utf16.
163 *
164 * Guest Kernel/KVP Daemon Protocol: As noted earlier, we implement all of the
165 * data gathering functionality in a user mode daemon. The user level daemon
166 * is also responsible for binding the key name to the index as well. The
167 * kernel and user-level daemon communicate using a connector channel.
168 *
169 * The user mode component first registers with the
170 * the kernel component. Subsequently, the kernel component requests, data
171 * for the specified keys. In response to this message the user mode component
172 * fills in the value corresponding to the specified key. We overload the
173 * sequence field in the cn_msg header to define our KVP message types.
174 *
175 *
176 * The kernel component simply acts as a conduit for communication between the
177 * Windows host and the user-level daemon. The kernel component passes up the
178 * index received from the Host to the user-level daemon. If the index is
179 * valid (supported), the corresponding key as well as its
180 * value (both are strings) is returned. If the index is invalid
181 * (not supported), a NULL key string is returned.
182 */
183
184
185/*
186 * Registry value types.
187 */
188
189#define REG_SZ 1
190#define REG_U32 4
191#define REG_U64 8
192
193/*
194 * As we look at expanding the KVP functionality to include
195 * IP injection functionality, we need to maintain binary
196 * compatibility with older daemons.
197 *
198 * The KVP opcodes are defined by the host and it was unfortunate
199 * that I chose to treat the registration operation as part of the
200 * KVP operations defined by the host.
201 * Here is the level of compatibility
202 * (between the user level daemon and the kernel KVP driver) that we
203 * will implement:
204 *
205 * An older daemon will always be supported on a newer driver.
206 * A given user level daemon will require a minimal version of the
207 * kernel driver.
208 * If we cannot handle the version differences, we will fail gracefully
209 * (this can happen when we have a user level daemon that is more
210 * advanced than the KVP driver.
211 *
212 * We will use values used in this handshake for determining if we have
213 * workable user level daemon and the kernel driver. We begin by taking the
214 * registration opcode out of the KVP opcode namespace. We will however,
215 * maintain compatibility with the existing user-level daemon code.
216 */
217
218/*
219 * Daemon code not supporting IP injection (legacy daemon).
220 */
221
222#define KVP_OP_REGISTER 4
223
224/*
225 * Daemon code supporting IP injection.
226 * The KVP opcode field is used to communicate the
227 * registration information; so define a namespace that
228 * will be distinct from the host defined KVP opcode.
229 */
230
231#define KVP_OP_REGISTER1 100
232
233enum hv_kvp_exchg_op {
234 KVP_OP_GET = 0,
235 KVP_OP_SET,
236 KVP_OP_DELETE,
237 KVP_OP_ENUMERATE,
238 KVP_OP_GET_IP_INFO,
239 KVP_OP_SET_IP_INFO,
240 KVP_OP_COUNT /* Number of operations, must be last. */
241};
242
243enum hv_kvp_exchg_pool {
244 KVP_POOL_EXTERNAL = 0,
245 KVP_POOL_GUEST,
246 KVP_POOL_AUTO,
247 KVP_POOL_AUTO_EXTERNAL,
248 KVP_POOL_AUTO_INTERNAL,
249 KVP_POOL_COUNT /* Number of pools, must be last. */
250};
251
252/*
253 * Some Hyper-V status codes.
254 */
255 29
256#define HV_S_OK 0x00000000 30#include <linux/types.h>
257#define HV_E_FAIL 0x80004005
258#define HV_S_CONT 0x80070103
259#define HV_ERROR_NOT_SUPPORTED 0x80070032
260#define HV_ERROR_MACHINE_LOCKED 0x800704F7
261#define HV_ERROR_DEVICE_NOT_CONNECTED 0x8007048F
262#define HV_INVALIDARG 0x80070057
263#define HV_GUID_NOTFOUND 0x80041002
264
265#define ADDR_FAMILY_NONE 0x00
266#define ADDR_FAMILY_IPV4 0x01
267#define ADDR_FAMILY_IPV6 0x02
268
269#define MAX_ADAPTER_ID_SIZE 128
270#define MAX_IP_ADDR_SIZE 1024
271#define MAX_GATEWAY_SIZE 512
272
273
274struct hv_kvp_ipaddr_value {
275 __u16 adapter_id[MAX_ADAPTER_ID_SIZE];
276 __u8 addr_family;
277 __u8 dhcp_enabled;
278 __u16 ip_addr[MAX_IP_ADDR_SIZE];
279 __u16 sub_net[MAX_IP_ADDR_SIZE];
280 __u16 gate_way[MAX_GATEWAY_SIZE];
281 __u16 dns_addr[MAX_IP_ADDR_SIZE];
282} __attribute__((packed));
283
284
285struct hv_kvp_hdr {
286 __u8 operation;
287 __u8 pool;
288 __u16 pad;
289} __attribute__((packed));
290
291struct hv_kvp_exchg_msg_value {
292 __u32 value_type;
293 __u32 key_size;
294 __u32 value_size;
295 __u8 key[HV_KVP_EXCHANGE_MAX_KEY_SIZE];
296 union {
297 __u8 value[HV_KVP_EXCHANGE_MAX_VALUE_SIZE];
298 __u32 value_u32;
299 __u64 value_u64;
300 };
301} __attribute__((packed));
302
303struct hv_kvp_msg_enumerate {
304 __u32 index;
305 struct hv_kvp_exchg_msg_value data;
306} __attribute__((packed));
307
308struct hv_kvp_msg_get {
309 struct hv_kvp_exchg_msg_value data;
310};
311
312struct hv_kvp_msg_set {
313 struct hv_kvp_exchg_msg_value data;
314};
315
316struct hv_kvp_msg_delete {
317 __u32 key_size;
318 __u8 key[HV_KVP_EXCHANGE_MAX_KEY_SIZE];
319};
320
321struct hv_kvp_register {
322 __u8 version[HV_KVP_EXCHANGE_MAX_KEY_SIZE];
323};
324
325struct hv_kvp_msg {
326 union {
327 struct hv_kvp_hdr kvp_hdr;
328 int error;
329 };
330 union {
331 struct hv_kvp_msg_get kvp_get;
332 struct hv_kvp_msg_set kvp_set;
333 struct hv_kvp_msg_delete kvp_delete;
334 struct hv_kvp_msg_enumerate kvp_enum_data;
335 struct hv_kvp_ipaddr_value kvp_ip_val;
336 struct hv_kvp_register kvp_register;
337 } body;
338} __attribute__((packed));
339
340struct hv_kvp_ip_msg {
341 __u8 operation;
342 __u8 pool;
343 struct hv_kvp_ipaddr_value kvp_ip_val;
344} __attribute__((packed));
345
346#ifdef __KERNEL__
347#include <linux/scatterlist.h> 31#include <linux/scatterlist.h>
348#include <linux/list.h> 32#include <linux/list.h>
349#include <linux/uuid.h>
350#include <linux/timer.h> 33#include <linux/timer.h>
351#include <linux/workqueue.h> 34#include <linux/workqueue.h>
352#include <linux/completion.h> 35#include <linux/completion.h>
@@ -354,7 +37,7 @@ struct hv_kvp_ip_msg {
354#include <linux/mod_devicetable.h> 37#include <linux/mod_devicetable.h>
355 38
356 39
357#define MAX_PAGE_BUFFER_COUNT 19 40#define MAX_PAGE_BUFFER_COUNT 32
358#define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */ 41#define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */
359 42
360#pragma pack(push, 1) 43#pragma pack(push, 1)
@@ -1043,6 +726,10 @@ struct vmbus_channel {
1043 * This will be NULL for the primary channel. 726 * This will be NULL for the primary channel.
1044 */ 727 */
1045 struct vmbus_channel *primary_channel; 728 struct vmbus_channel *primary_channel;
729 /*
730 * Support per-channel state for use by vmbus drivers.
731 */
732 void *per_channel_state;
1046}; 733};
1047 734
1048static inline void set_channel_read_state(struct vmbus_channel *c, bool state) 735static inline void set_channel_read_state(struct vmbus_channel *c, bool state)
@@ -1050,6 +737,16 @@ static inline void set_channel_read_state(struct vmbus_channel *c, bool state)
1050 c->batched_reading = state; 737 c->batched_reading = state;
1051} 738}
1052 739
740static inline void set_per_channel_state(struct vmbus_channel *c, void *s)
741{
742 c->per_channel_state = s;
743}
744
745static inline void *get_per_channel_state(struct vmbus_channel *c)
746{
747 return c->per_channel_state;
748}
749
1053void vmbus_onmessage(void *context); 750void vmbus_onmessage(void *context);
1054 751
1055int vmbus_request_offers(void); 752int vmbus_request_offers(void);
@@ -1118,7 +815,7 @@ extern int vmbus_open(struct vmbus_channel *channel,
1118extern void vmbus_close(struct vmbus_channel *channel); 815extern void vmbus_close(struct vmbus_channel *channel);
1119 816
1120extern int vmbus_sendpacket(struct vmbus_channel *channel, 817extern int vmbus_sendpacket(struct vmbus_channel *channel,
1121 const void *buffer, 818 void *buffer,
1122 u32 bufferLen, 819 u32 bufferLen,
1123 u64 requestid, 820 u64 requestid,
1124 enum vmbus_packet_type type, 821 enum vmbus_packet_type type,
@@ -1352,6 +1049,17 @@ void vmbus_driver_unregister(struct hv_driver *hv_driver);
1352 } 1049 }
1353 1050
1354/* 1051/*
1052 * Guest File Copy Service
1053 * {34D14BE3-DEE4-41c8-9AE7-6B174977C192}
1054 */
1055
1056#define HV_FCOPY_GUID \
1057 .guid = { \
1058 0xE3, 0x4B, 0xD1, 0x34, 0xE4, 0xDE, 0xC8, 0x41, \
1059 0x9A, 0xE7, 0x6B, 0x17, 0x49, 0x77, 0xC1, 0x92 \
1060 }
1061
1062/*
1355 * Common header for Hyper-V ICs 1063 * Common header for Hyper-V ICs
1356 */ 1064 */
1357 1065
@@ -1459,11 +1167,12 @@ int hv_vss_init(struct hv_util_service *);
1459void hv_vss_deinit(void); 1167void hv_vss_deinit(void);
1460void hv_vss_onchannelcallback(void *); 1168void hv_vss_onchannelcallback(void *);
1461 1169
1170extern struct resource hyperv_mmio;
1171
1462/* 1172/*
1463 * Negotiated version with the Host. 1173 * Negotiated version with the Host.
1464 */ 1174 */
1465 1175
1466extern __u32 vmbus_proto_version; 1176extern __u32 vmbus_proto_version;
1467 1177
1468#endif /* __KERNEL__ */
1469#endif /* _HYPERV_H */ 1178#endif /* _HYPERV_H */
diff --git a/include/linux/mcb.h b/include/linux/mcb.h
new file mode 100644
index 000000000000..2db284d14064
--- /dev/null
+++ b/include/linux/mcb.h
@@ -0,0 +1,119 @@
1/*
2 * MEN Chameleon Bus.
3 *
4 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
5 * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; version 2 of the License.
10 */
11#ifndef _LINUX_MCB_H
12#define _LINUX_MCB_H
13
14#include <linux/mod_devicetable.h>
15#include <linux/device.h>
16#include <linux/irqreturn.h>
17
18struct mcb_driver;
19
20/**
21 * struct mcb_bus - MEN Chameleon Bus
22 *
23 * @dev: pointer to carrier device
24 * @children: the child busses
25 * @bus_nr: mcb bus number
26 */
27struct mcb_bus {
28 struct list_head children;
29 struct device dev;
30 int bus_nr;
31};
32#define to_mcb_bus(b) container_of((b), struct mcb_bus, dev)
33
34/**
35 * struct mcb_device - MEN Chameleon Bus device
36 *
37 * @bus_list: internal list handling for bus code
38 * @dev: device in kernel representation
39 * @bus: mcb bus the device is plugged to
40 * @subordinate: subordinate MCBus in case of bridge
41 * @is_added: flag to check if device is added to bus
42 * @driver: associated mcb_driver
43 * @id: mcb device id
44 * @inst: instance in Chameleon table
45 * @group: group in Chameleon table
46 * @var: variant in Chameleon table
47 * @bar: BAR in Chameleon table
48 * @rev: revision in Chameleon table
49 * @irq: IRQ resource
50 * @memory: memory resource
51 */
52struct mcb_device {
53 struct list_head bus_list;
54 struct device dev;
55 struct mcb_bus *bus;
56 struct mcb_bus *subordinate;
57 bool is_added;
58 struct mcb_driver *driver;
59 u16 id;
60 int inst;
61 int group;
62 int var;
63 int bar;
64 int rev;
65 struct resource irq;
66 struct resource mem;
67};
68#define to_mcb_device(x) container_of((x), struct mcb_device, dev)
69
70/**
71 * struct mcb_driver - MEN Chameleon Bus device driver
72 *
73 * @driver: device_driver
74 * @id_table: mcb id table
75 * @probe: probe callback
76 * @remove: remove callback
77 * @shutdown: shutdown callback
78 */
79struct mcb_driver {
80 struct device_driver driver;
81 const struct mcb_device_id *id_table;
82 int (*probe)(struct mcb_device *mdev, const struct mcb_device_id *id);
83 void (*remove)(struct mcb_device *mdev);
84 void (*shutdown)(struct mcb_device *mdev);
85};
86#define to_mcb_driver(x) container_of((x), struct mcb_driver, driver)
87
88static inline void *mcb_get_drvdata(struct mcb_device *dev)
89{
90 return dev_get_drvdata(&dev->dev);
91}
92
93static inline void mcb_set_drvdata(struct mcb_device *dev, void *data)
94{
95 dev_set_drvdata(&dev->dev, data);
96}
97
98extern int __must_check __mcb_register_driver(struct mcb_driver *drv,
99 struct module *owner,
100 const char *mod_name);
101#define mcb_register_driver(driver) \
102 __mcb_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
103extern void mcb_unregister_driver(struct mcb_driver *driver);
104#define module_mcb_driver(__mcb_driver) \
105 module_driver(__mcb_driver, mcb_register_driver, mcb_unregister_driver);
106extern void mcb_bus_add_devices(const struct mcb_bus *bus);
107extern int mcb_device_register(struct mcb_bus *bus, struct mcb_device *dev);
108extern struct mcb_bus *mcb_alloc_bus(void);
109extern struct mcb_bus *mcb_bus_get(struct mcb_bus *bus);
110extern void mcb_bus_put(struct mcb_bus *bus);
111extern struct mcb_device *mcb_alloc_dev(struct mcb_bus *bus);
112extern void mcb_free_dev(struct mcb_device *dev);
113extern void mcb_release_bus(struct mcb_bus *bus);
114extern struct resource *mcb_request_mem(struct mcb_device *dev,
115 const char *name);
116extern void mcb_release_mem(struct resource *mem);
117extern int mcb_get_irq(struct mcb_device *dev);
118
119#endif /* _LINUX_MCB_H */
diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h
index 3737f7218f51..2cf1547096d9 100644
--- a/include/linux/miscdevice.h
+++ b/include/linux/miscdevice.h
@@ -11,23 +11,23 @@
11 */ 11 */
12 12
13#define PSMOUSE_MINOR 1 13#define PSMOUSE_MINOR 1
14#define MS_BUSMOUSE_MINOR 2 14#define MS_BUSMOUSE_MINOR 2 /* unused */
15#define ATIXL_BUSMOUSE_MINOR 3 15#define ATIXL_BUSMOUSE_MINOR 3 /* unused */
16/*#define AMIGAMOUSE_MINOR 4 FIXME OBSOLETE */ 16/*#define AMIGAMOUSE_MINOR 4 FIXME OBSOLETE */
17#define ATARIMOUSE_MINOR 5 17#define ATARIMOUSE_MINOR 5 /* unused */
18#define SUN_MOUSE_MINOR 6 18#define SUN_MOUSE_MINOR 6 /* unused */
19#define APOLLO_MOUSE_MINOR 7 19#define APOLLO_MOUSE_MINOR 7 /* unused */
20#define PC110PAD_MINOR 9 20#define PC110PAD_MINOR 9 /* unused */
21/*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ 21/*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */
22#define WATCHDOG_MINOR 130 /* Watchdog timer */ 22#define WATCHDOG_MINOR 130 /* Watchdog timer */
23#define TEMP_MINOR 131 /* Temperature Sensor */ 23#define TEMP_MINOR 131 /* Temperature Sensor */
24#define RTC_MINOR 135 24#define RTC_MINOR 135
25#define EFI_RTC_MINOR 136 /* EFI Time services */ 25#define EFI_RTC_MINOR 136 /* EFI Time services */
26#define SUN_OPENPROM_MINOR 139 26#define SUN_OPENPROM_MINOR 139
27#define DMAPI_MINOR 140 /* DMAPI */ 27#define DMAPI_MINOR 140 /* unused */
28#define NVRAM_MINOR 144 28#define NVRAM_MINOR 144
29#define SGI_MMTIMER 153 29#define SGI_MMTIMER 153
30#define STORE_QUEUE_MINOR 155 30#define STORE_QUEUE_MINOR 155 /* unused */
31#define I2O_MINOR 166 31#define I2O_MINOR 166
32#define MICROCODE_MINOR 184 32#define MICROCODE_MINOR 184
33#define VFIO_MINOR 196 33#define VFIO_MINOR 196
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 45e921401b06..50f67eff27ef 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -432,6 +432,14 @@ struct spi_device_id {
432 kernel_ulong_t driver_data; /* Data private to the driver */ 432 kernel_ulong_t driver_data; /* Data private to the driver */
433}; 433};
434 434
435#define SPMI_NAME_SIZE 32
436#define SPMI_MODULE_PREFIX "spmi:"
437
438struct spmi_device_id {
439 char name[SPMI_NAME_SIZE];
440 kernel_ulong_t driver_data; /* Data private to the driver */
441};
442
435/* dmi */ 443/* dmi */
436enum dmi_field { 444enum dmi_field {
437 DMI_NONE, 445 DMI_NONE,
@@ -599,4 +607,9 @@ struct rio_device_id {
599 __u16 asm_did, asm_vid; 607 __u16 asm_did, asm_vid;
600}; 608};
601 609
610struct mcb_device_id {
611 __u16 device;
612 kernel_ulong_t driver_data;
613};
614
602#endif /* LINUX_MOD_DEVICETABLE_H */ 615#endif /* LINUX_MOD_DEVICETABLE_H */
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 5ad86eacef0d..85691b9b4fa7 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -327,8 +327,10 @@ struct regmap *regmap_init_i2c(struct i2c_client *i2c,
327 const struct regmap_config *config); 327 const struct regmap_config *config);
328struct regmap *regmap_init_spi(struct spi_device *dev, 328struct regmap *regmap_init_spi(struct spi_device *dev,
329 const struct regmap_config *config); 329 const struct regmap_config *config);
330struct regmap *regmap_init_spmi(struct spmi_device *dev, 330struct regmap *regmap_init_spmi_base(struct spmi_device *dev,
331 const struct regmap_config *config); 331 const struct regmap_config *config);
332struct regmap *regmap_init_spmi_ext(struct spmi_device *dev,
333 const struct regmap_config *config);
332struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id, 334struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
333 void __iomem *regs, 335 void __iomem *regs,
334 const struct regmap_config *config); 336 const struct regmap_config *config);
@@ -341,8 +343,10 @@ struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c,
341 const struct regmap_config *config); 343 const struct regmap_config *config);
342struct regmap *devm_regmap_init_spi(struct spi_device *dev, 344struct regmap *devm_regmap_init_spi(struct spi_device *dev,
343 const struct regmap_config *config); 345 const struct regmap_config *config);
344struct regmap *devm_regmap_init_spmi(struct spmi_device *dev, 346struct regmap *devm_regmap_init_spmi_base(struct spmi_device *dev,
345 const struct regmap_config *config); 347 const struct regmap_config *config);
348struct regmap *devm_regmap_init_spmi_ext(struct spmi_device *dev,
349 const struct regmap_config *config);
346struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id, 350struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
347 void __iomem *regs, 351 void __iomem *regs,
348 const struct regmap_config *config); 352 const struct regmap_config *config);
diff --git a/include/linux/spmi.h b/include/linux/spmi.h
new file mode 100644
index 000000000000..91f5eab9e428
--- /dev/null
+++ b/include/linux/spmi.h
@@ -0,0 +1,191 @@
1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef _LINUX_SPMI_H
13#define _LINUX_SPMI_H
14
15#include <linux/types.h>
16#include <linux/device.h>
17#include <linux/mod_devicetable.h>
18
19/* Maximum slave identifier */
20#define SPMI_MAX_SLAVE_ID 16
21
22/* SPMI Commands */
23#define SPMI_CMD_EXT_WRITE 0x00
24#define SPMI_CMD_RESET 0x10
25#define SPMI_CMD_SLEEP 0x11
26#define SPMI_CMD_SHUTDOWN 0x12
27#define SPMI_CMD_WAKEUP 0x13
28#define SPMI_CMD_AUTHENTICATE 0x14
29#define SPMI_CMD_MSTR_READ 0x15
30#define SPMI_CMD_MSTR_WRITE 0x16
31#define SPMI_CMD_TRANSFER_BUS_OWNERSHIP 0x1A
32#define SPMI_CMD_DDB_MASTER_READ 0x1B
33#define SPMI_CMD_DDB_SLAVE_READ 0x1C
34#define SPMI_CMD_EXT_READ 0x20
35#define SPMI_CMD_EXT_WRITEL 0x30
36#define SPMI_CMD_EXT_READL 0x38
37#define SPMI_CMD_WRITE 0x40
38#define SPMI_CMD_READ 0x60
39#define SPMI_CMD_ZERO_WRITE 0x80
40
41/**
42 * struct spmi_device - Basic representation of an SPMI device
43 * @dev: Driver model representation of the device.
44 * @ctrl: SPMI controller managing the bus hosting this device.
45 * @usid: This devices' Unique Slave IDentifier.
46 */
47struct spmi_device {
48 struct device dev;
49 struct spmi_controller *ctrl;
50 u8 usid;
51};
52
53static inline struct spmi_device *to_spmi_device(struct device *d)
54{
55 return container_of(d, struct spmi_device, dev);
56}
57
58static inline void *spmi_device_get_drvdata(const struct spmi_device *sdev)
59{
60 return dev_get_drvdata(&sdev->dev);
61}
62
63static inline void spmi_device_set_drvdata(struct spmi_device *sdev, void *data)
64{
65 dev_set_drvdata(&sdev->dev, data);
66}
67
68struct spmi_device *spmi_device_alloc(struct spmi_controller *ctrl);
69
70static inline void spmi_device_put(struct spmi_device *sdev)
71{
72 if (sdev)
73 put_device(&sdev->dev);
74}
75
76int spmi_device_add(struct spmi_device *sdev);
77
78void spmi_device_remove(struct spmi_device *sdev);
79
80/**
81 * struct spmi_controller - interface to the SPMI master controller
82 * @dev: Driver model representation of the device.
83 * @nr: board-specific number identifier for this controller/bus
84 * @cmd: sends a non-data command sequence on the SPMI bus.
85 * @read_cmd: sends a register read command sequence on the SPMI bus.
86 * @write_cmd: sends a register write command sequence on the SPMI bus.
87 */
88struct spmi_controller {
89 struct device dev;
90 unsigned int nr;
91 int (*cmd)(struct spmi_controller *ctrl, u8 opcode, u8 sid);
92 int (*read_cmd)(struct spmi_controller *ctrl, u8 opcode,
93 u8 sid, u16 addr, u8 *buf, size_t len);
94 int (*write_cmd)(struct spmi_controller *ctrl, u8 opcode,
95 u8 sid, u16 addr, const u8 *buf, size_t len);
96};
97
98static inline struct spmi_controller *to_spmi_controller(struct device *d)
99{
100 return container_of(d, struct spmi_controller, dev);
101}
102
103static inline
104void *spmi_controller_get_drvdata(const struct spmi_controller *ctrl)
105{
106 return dev_get_drvdata(&ctrl->dev);
107}
108
109static inline void spmi_controller_set_drvdata(struct spmi_controller *ctrl,
110 void *data)
111{
112 dev_set_drvdata(&ctrl->dev, data);
113}
114
115struct spmi_controller *spmi_controller_alloc(struct device *parent,
116 size_t size);
117
118/**
119 * spmi_controller_put() - decrement controller refcount
120 * @ctrl SPMI controller.
121 */
122static inline void spmi_controller_put(struct spmi_controller *ctrl)
123{
124 if (ctrl)
125 put_device(&ctrl->dev);
126}
127
128int spmi_controller_add(struct spmi_controller *ctrl);
129void spmi_controller_remove(struct spmi_controller *ctrl);
130
131/**
132 * struct spmi_driver - SPMI slave device driver
133 * @driver: SPMI device drivers should initialize name and owner field of
134 * this structure.
135 * @probe: binds this driver to a SPMI device.
136 * @remove: unbinds this driver from the SPMI device.
137 * @shutdown: standard shutdown callback used during powerdown/halt.
138 * @suspend: standard suspend callback used during system suspend.
139 * @resume: standard resume callback used during system resume.
140 *
141 * If PM runtime support is desired for a slave, a device driver can call
142 * pm_runtime_put() from their probe() routine (and a balancing
143 * pm_runtime_get() in remove()). PM runtime support for a slave is
144 * implemented by issuing a SLEEP command to the slave on runtime_suspend(),
145 * transitioning the slave into the SLEEP state. On runtime_resume(), a WAKEUP
146 * command is sent to the slave to bring it back to ACTIVE.
147 */
148struct spmi_driver {
149 struct device_driver driver;
150 int (*probe)(struct spmi_device *sdev);
151 void (*remove)(struct spmi_device *sdev);
152};
153
154static inline struct spmi_driver *to_spmi_driver(struct device_driver *d)
155{
156 return container_of(d, struct spmi_driver, driver);
157}
158
159int spmi_driver_register(struct spmi_driver *sdrv);
160
161/**
162 * spmi_driver_unregister() - unregister an SPMI client driver
163 * @sdrv: the driver to unregister
164 */
165static inline void spmi_driver_unregister(struct spmi_driver *sdrv)
166{
167 if (sdrv)
168 driver_unregister(&sdrv->driver);
169}
170
171#define module_spmi_driver(__spmi_driver) \
172 module_driver(__spmi_driver, spmi_driver_register, \
173 spmi_driver_unregister)
174
175int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf);
176int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf,
177 size_t len);
178int spmi_ext_register_readl(struct spmi_device *sdev, u16 addr, u8 *buf,
179 size_t len);
180int spmi_register_write(struct spmi_device *sdev, u8 addr, u8 data);
181int spmi_register_zero_write(struct spmi_device *sdev, u8 data);
182int spmi_ext_register_write(struct spmi_device *sdev, u8 addr,
183 const u8 *buf, size_t len);
184int spmi_ext_register_writel(struct spmi_device *sdev, u16 addr,
185 const u8 *buf, size_t len);
186int spmi_command_reset(struct spmi_device *sdev);
187int spmi_command_sleep(struct spmi_device *sdev);
188int spmi_command_wakeup(struct spmi_device *sdev);
189int spmi_command_shutdown(struct spmi_device *sdev);
190
191#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-20 22:38:38 -0500