mfd: rtsx: Add support for rts524A

add support for new chip rts524A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

1 files changed, 130 insertions, 2 deletions

diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 33cc63ced99e..754a18d4203a 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -577,8 +577,16 @@
 
 #define CDRESUMECTL                     0xFE52
 #define WAKE_SEL_CTL                    0xFE54
+#define PCLK_CTL                        0xFE55
+#define   PCLK_MODE_SEL                 0x20
 #define PME_FORCE_CTL                   0xFE56
+
 #define ASPM_FORCE_CTL                  0xFE57
+#define   FORCE_ASPM_CTL0               0x10
+#define   FORCE_ASPM_VAL_MASK           0x03
+#define   FORCE_ASPM_L1_EN              0x02
+#define   FORCE_ASPM_L0_EN              0x01
+#define   FORCE_ASPM_NO_ASPM            0x00
 #define PM_CLK_FORCE_CTL                0xFE58
 #define FUNC_FORCE_CTL                  0xFE59
 #define PERST_GLITCH_WIDTH              0xFE5C
@@ -590,7 +598,8 @@
 #define   HOST_ENTER_S3                 2
 
 #define SDIO_CFG                        0xFE70
-
+#define PM_EVENT_DEBUG                  0xFE71
+#define   PME_DEBUG_0                   0x08
 #define NFTS_TX_CTRL                    0xFE72
 
 #define PWR_GATE_CTRL                   0xFE75
@@ -602,12 +611,19 @@
 #define PWD_SUSPEND_EN                  0xFE76
 #define LDO_PWR_SEL                     0xFE78
 
+#define L1SUB_CONFIG1                   0xFE8D
+#define L1SUB_CONFIG2                   0xFE8E
+#define   L1SUB_AUTO_CFG                0x02
+#define L1SUB_CONFIG3                   0xFE8F
+
 #define DUMMY_REG_RESET_0               0xFE90
 
 #define AUTOLOAD_CFG_BASE               0xFF00
 #define PETXCFG                         0xFF03
 
 #define PM_CTRL1                        0xFF44
+#define   CD_RESUME_EN_MASK             0xF0
+
 #define PM_CTRL2                        0xFF45
 #define PM_CTRL3                        0xFF46
 #define   SDIO_SEND_PME_EN              0x80
@@ -628,6 +644,61 @@
 #define IMAGE_FLAG_ADDR0                0xCE80
 #define IMAGE_FLAG_ADDR1                0xCE81
 
+#define RREF_CFG                        0xFF6C
+#define   RREF_VBGSEL_MASK              0x38
+#define   RREF_VBGSEL_1V25              0x28
+
+#define OOBS_CONFIG                     0xFF6E
+#define   OOBS_AUTOK_DIS                0x80
+#define   OOBS_VAL_MASK                 0x1F
+
+#define LDO_DV18_CFG                    0xFF70
+#define   LDO_DV18_SR_MASK              0xC0
+#define   LDO_DV18_SR_DF                0x40
+
+#define LDO_CONFIG2                     0xFF71
+#define   LDO_D3318_MASK                0x07
+#define   LDO_D3318_33V                 0x07
+#define   LDO_D3318_18V                 0x02
+
+#define LDO_VCC_CFG0                    0xFF72
+#define   LDO_VCC_LMTVTH_MASK           0x30
+#define   LDO_VCC_LMTVTH_2A             0x10
+
+#define LDO_VCC_CFG1                    0xFF73
+#define   LDO_VCC_REF_TUNE_MASK         0x30
+#define   LDO_VCC_REF_1V2               0x20
+#define   LDO_VCC_TUNE_MASK             0x07
+#define   LDO_VCC_1V8                   0x04
+#define   LDO_VCC_3V3                   0x07
+#define   LDO_VCC_LMT_EN                0x08
+
+#define LDO_VIO_CFG                     0xFF75
+#define   LDO_VIO_SR_MASK               0xC0
+#define   LDO_VIO_SR_DF                 0x40
+#define   LDO_VIO_REF_TUNE_MASK         0x30
+#define   LDO_VIO_REF_1V2               0x20
+#define   LDO_VIO_TUNE_MASK             0x07
+#define   LDO_VIO_1V7                   0x03
+#define   LDO_VIO_1V8                   0x04
+#define   LDO_VIO_3V3                   0x07
+
+#define LDO_DV12S_CFG                   0xFF76
+#define   LDO_REF12_TUNE_MASK           0x18
+#define   LDO_REF12_TUNE_DF             0x10
+#define   LDO_D12_TUNE_MASK             0x07
+#define   LDO_D12_TUNE_DF               0x04
+
+#define LDO_AV12S_CFG                   0xFF77
+#define   LDO_AV12S_TUNE_MASK           0x07
+#define   LDO_AV12S_TUNE_DF             0x04
+
+#define SD40_LDO_CTL1                   0xFE7D
+#define   SD40_VIO_TUNE_MASK            0x70
+#define   SD40_VIO_TUNE_1V7             0x30
+#define   SD_VIO_LDO_1V8                0x40
+#define   SD_VIO_LDO_3V3                0x70
+
 /* Phy register */
 #define PHY_PCR                         0x00
 #define   PHY_PCR_FORCE_CODE            0xB000
@@ -641,6 +712,10 @@
 #define PHY_RCR1                        0x02
 #define   PHY_RCR1_ADP_TIME_4           0x0400
 #define   PHY_RCR1_VCO_COARSE           0x001F
+#define PHY_SSCCR2                      0x02
+#define   PHY_SSCCR2_PLL_NCODE          0x0A00
+#define   PHY_SSCCR2_TIME0              0x001C
+#define   PHY_SSCCR2_TIME2_WIDTH        0x0003
 
 #define PHY_RCR2                        0x03
 #define   PHY_RCR2_EMPHASE_EN           0x8000
@@ -649,6 +724,9 @@
 #define   PHY_RCR2_FREQSEL_12           0x0040
 #define   PHY_RCR2_CDR_SC_12P           0x0010
 #define   PHY_RCR2_CALIB_LATE           0x0002
+#define PHY_SSCCR3                      0x03
+#define   PHY_SSCCR3_STEP_IN            0x2740
+#define   PHY_SSCCR3_CHECK_DELAY        0x0008
 
 #define PHY_RTCR                        0x04
 #define PHY_RDR                         0x05
@@ -663,6 +741,16 @@
 #define   PHY_TUNE_TUNED18              0x01C0
 #define   PHY_TUNE_TUNED12              0X0020
 #define   PHY_TUNE_TUNEA12              0x0004
+#define   PHY_TUNE_VOLTAGE_MASK         0xFC3F
+#define   PHY_TUNE_VOLTAGE_3V3          0x03C0
+#define   PHY_TUNE_D18_1V8              0x0100
+#define   PHY_TUNE_D18_1V7              0x0080
+#define PHY_ANA08                       0x08
+#define   PHY_ANA08_RX_EQ_DCGAIN        0x5000
+#define   PHY_ANA08_SEL_RX_EN           0x0400
+#define   PHY_ANA08_RX_EQ_VAL           0x03C0
+#define   PHY_ANA08_SCP                 0x0020
+#define   PHY_ANA08_SEL_IPI             0x0004
 
 #define PHY_IMR                         0x09
 #define PHY_BPCR                        0x0A
@@ -678,6 +766,7 @@
 #define PHY_HOST_CLK_CTRL               0x0F
 #define PHY_DMR                         0x10
 #define PHY_BACR                        0x11
+#define   PHY_BACR_BASIC_MASK           0xFFF3
 #define PHY_IER                         0x12
 #define PHY_BCSR                        0x13
 #define PHY_BPR                         0x14
@@ -698,12 +787,19 @@
 #define   PHY_REV_STOP_CLKWR            0x0004
 
 #define PHY_FLD0                        0x1A
+#define PHY_ANA1A                       0x1A
+#define   PHY_ANA1A_TXR_LOOPBACK        0x2000
+#define   PHY_ANA1A_RXT_BIST            0x0500
+#define   PHY_ANA1A_TXR_BIST            0x0040
+#define   PHY_ANA1A_REV                 0x0006
 #define PHY_FLD1                        0x1B
 #define PHY_FLD2                        0x1C
 #define PHY_FLD3                        0x1D
 #define   PHY_FLD3_TIMER_4              0x0800
 #define   PHY_FLD3_TIMER_6              0x0020
 #define   PHY_FLD3_RXDELINK             0x0004
+#define PHY_ANA1D                       0x1D
+#define   PHY_ANA1D_DEBUG_ADDR          0x0004
 
 #define PHY_FLD4                        0x1E
 #define   PHY_FLD4_FLDEN_SEL            0x4000
@@ -713,7 +809,18 @@
 #define   PHY_FLD4_BER_COUNT            0x00E0
 #define   PHY_FLD4_BER_TIMER            0x000A
 #define   PHY_FLD4_BER_CHK_EN           0x0001
-
+#define PHY_DIG1E                       0x1E
+#define   PHY_DIG1E_REV                 0x4000
+#define   PHY_DIG1E_D0_X_D1             0x1000
+#define   PHY_DIG1E_RX_ON_HOST          0x0800
+#define   PHY_DIG1E_RCLK_REF_HOST       0x0400
+#define   PHY_DIG1E_RCLK_TX_EN_KEEP     0x0040
+#define   PHY_DIG1E_RCLK_TX_TERM_KEEP   0x0020
+#define   PHY_DIG1E_RCLK_RX_EIDLE_ON    0x0010
+#define   PHY_DIG1E_TX_TERM_KEEP        0x0008
+#define   PHY_DIG1E_RX_TERM_KEEP        0x0004
+#define   PHY_DIG1E_TX_EN_KEEP          0x0002
+#define   PHY_DIG1E_RX_EN_KEEP          0x0001
 #define PHY_DUM_REG                     0x1F
 
 #define PCR_SETTING_REG1                0x724
@@ -729,6 +836,8 @@ struct pcr_handle {
 };
 
 struct pcr_ops {
+        int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
+        int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
         int             (*extra_init_hw)(struct rtsx_pcr *pcr);
         int             (*optimize_phy)(struct rtsx_pcr *pcr);
         int             (*turn_on_led)(struct rtsx_pcr *pcr);
@@ -823,6 +932,8 @@ struct rtsx_pcr {
         const struct pcr_ops            *ops;
         enum PDEV_STAT                  state;
 
+        u16                             reg_pm_ctrl3;
+
         int                             num_slots;
         struct rtsx_slot                *slots;
 };
@@ -830,6 +941,10 @@ struct rtsx_pcr {
 #define CHK_PCI_PID(pcr, pid)           ((pcr)->pci->device == (pid))
 #define PCI_VID(pcr)                    ((pcr)->pci->vendor)
 #define PCI_PID(pcr)                    ((pcr)->pci->device)
+#define is_version(pcr, pid, ver)                               \
+        (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
+#define pcr_dbg(pcr, fmt, arg...)                               \
+        dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
 
 #define SDR104_PHASE(val)               ((val) & 0xFF)
 #define SDR50_PHASE(val)                (((val) >> 8) & 0xFF)
@@ -899,4 +1014,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
 }
 
+static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
+        u16 mask, u16 append)
+{
+        int err;
+        u16 val;
+
+        err = rtsx_pci_read_phy_register(pcr, addr, &val);
+        if (err < 0)
+                return err;
+
+        return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
+}
+
 #endif