Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:
 "This is fairly big pull by my standards as I had missed last merge
  window.  So we have the support for device tree for slave-dmaengine,
  large updates to dw_dmac driver from Andy for reusing on different
  architectures.  Along with this we have fixes on bunch of the drivers"

Fix up trivial conflicts, usually due to #include line movement next to
each other.

* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (111 commits)
  Revert "ARM: SPEAr13xx: Pass DW DMAC platform data from DT"
  ARM: dts: pl330: Add #dma-cells for generic dma binding support
  DMA: PL330: Register the DMA controller with the generic DMA helpers
  DMA: PL330: Add xlate function
  DMA: PL330: Add new pl330 filter for DT case.
  dma: tegra20-apb-dma: remove unnecessary assignment
  edma: do not waste memory for dma_mask
  dma: coh901318: set residue only if dma is in progress
  dma: coh901318: avoid unbalanced locking
  dmaengine.h: remove redundant else keyword
  dma: of-dma: protect list write operation by spin_lock
  dmaengine: ste_dma40: do not remove descriptors for cyclic transfers
  dma: of-dma.c: fix memory leakage
  dw_dmac: apply default dma_mask if needed
  dmaengine: ioat - fix spare sparse complain
  dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c
  ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDING
  dw_dmac: add support for Lynxpoint DMA controllers
  dw_dmac: return proper residue value
  dw_dmac: fill individual length of descriptor
  ...

5 files changed, 285 insertions, 41 deletions

diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
new file mode 100644
index 000000000000..3e7b62fbefbd
--- /dev/null
+++ b/include/linux/amba/pl080.h
@@ -0,0 +1,146 @@
+/* include/linux/amba/pl080.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ARM PrimeCell PL080 DMA controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Note, there are some Samsung updates to this controller block which
+ * make it not entierly compatible with the PL080 specification from
+ * ARM. When in doubt, check the Samsung documentation first.
+ *
+ * The Samsung defines are PL080S, and add an extra control register,
+ * the ability to move more than 2^11 counts of data and some extra
+ * OneNAND features.
+*/
+
+#ifndef ASM_PL080_H
+#define ASM_PL080_H
+
+#define PL080_INT_STATUS                        (0x00)
+#define PL080_TC_STATUS                         (0x04)
+#define PL080_TC_CLEAR                          (0x08)
+#define PL080_ERR_STATUS                        (0x0C)
+#define PL080_ERR_CLEAR                         (0x10)
+#define PL080_RAW_TC_STATUS                     (0x14)
+#define PL080_RAW_ERR_STATUS                    (0x18)
+#define PL080_EN_CHAN                           (0x1c)
+#define PL080_SOFT_BREQ                         (0x20)
+#define PL080_SOFT_SREQ                         (0x24)
+#define PL080_SOFT_LBREQ                        (0x28)
+#define PL080_SOFT_LSREQ                        (0x2C)
+
+#define PL080_CONFIG                            (0x30)
+#define PL080_CONFIG_M2_BE                      (1 << 2)
+#define PL080_CONFIG_M1_BE                      (1 << 1)
+#define PL080_CONFIG_ENABLE                     (1 << 0)
+
+#define PL080_SYNC                              (0x34)
+
+/* Per channel configuration registers */
+
+#define PL080_Cx_STRIDE                         (0x20)
+#define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
+#define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
+#define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
+#define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
+#define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
+#define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
+
+#define PL080_CH_SRC_ADDR                       (0x00)
+#define PL080_CH_DST_ADDR                       (0x04)
+#define PL080_CH_LLI                            (0x08)
+#define PL080_CH_CONTROL                        (0x0C)
+#define PL080_CH_CONFIG                         (0x10)
+#define PL080S_CH_CONTROL2                      (0x10)
+#define PL080S_CH_CONFIG                        (0x14)
+
+#define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
+#define PL080_LLI_ADDR_SHIFT                    (2)
+#define PL080_LLI_LM_AHB2                       (1 << 0)
+
+#define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
+#define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
+#define PL080_CONTROL_PROT_SHIFT                (28)
+#define PL080_CONTROL_PROT_CACHE                (1 << 30)
+#define PL080_CONTROL_PROT_BUFF                 (1 << 29)
+#define PL080_CONTROL_PROT_SYS                  (1 << 28)
+#define PL080_CONTROL_DST_INCR                  (1 << 27)
+#define PL080_CONTROL_SRC_INCR                  (1 << 26)
+#define PL080_CONTROL_DST_AHB2                  (1 << 25)
+#define PL080_CONTROL_SRC_AHB2                  (1 << 24)
+#define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
+#define PL080_CONTROL_DWIDTH_SHIFT              (21)
+#define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
+#define PL080_CONTROL_SWIDTH_SHIFT              (18)
+#define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
+#define PL080_CONTROL_DB_SIZE_SHIFT             (15)
+#define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
+#define PL080_CONTROL_SB_SIZE_SHIFT             (12)
+#define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
+#define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
+
+#define PL080_BSIZE_1                           (0x0)
+#define PL080_BSIZE_4                           (0x1)
+#define PL080_BSIZE_8                           (0x2)
+#define PL080_BSIZE_16                          (0x3)
+#define PL080_BSIZE_32                          (0x4)
+#define PL080_BSIZE_64                          (0x5)
+#define PL080_BSIZE_128                         (0x6)
+#define PL080_BSIZE_256                         (0x7)
+
+#define PL080_WIDTH_8BIT                        (0x0)
+#define PL080_WIDTH_16BIT                       (0x1)
+#define PL080_WIDTH_32BIT                       (0x2)
+
+#define PL080N_CONFIG_ITPROT                    (1 << 20)
+#define PL080N_CONFIG_SECPROT                   (1 << 19)
+#define PL080_CONFIG_HALT                       (1 << 18)
+#define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
+#define PL080_CONFIG_LOCK                       (1 << 16)
+#define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
+#define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
+#define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
+#define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
+#define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
+#define PL080_CONFIG_DST_SEL_SHIFT              (6)
+#define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
+#define PL080_CONFIG_SRC_SEL_SHIFT              (1)
+#define PL080_CONFIG_ENABLE                     (1 << 0)
+
+#define PL080_FLOW_MEM2MEM                      (0x0)
+#define PL080_FLOW_MEM2PER                      (0x1)
+#define PL080_FLOW_PER2MEM                      (0x2)
+#define PL080_FLOW_SRC2DST                      (0x3)
+#define PL080_FLOW_SRC2DST_DST                  (0x4)
+#define PL080_FLOW_MEM2PER_PER                  (0x5)
+#define PL080_FLOW_PER2MEM_PER                  (0x6)
+#define PL080_FLOW_SRC2DST_SRC                  (0x7)
+
+/* DMA linked list chain structure */
+
+struct pl080_lli {
+        u32     src_addr;
+        u32     dst_addr;
+        u32     next_lli;
+        u32     control0;
+};
+
+struct pl080s_lli {
+        u32     src_addr;
+        u32     dst_addr;
+        u32     next_lli;
+        u32     control0;
+        u32     control1;
+};
+
+#endif /* ASM_PL080_H */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index d3201e438d16..f5939999cb65 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -608,7 +608,10 @@ static inline int dmaengine_device_control(struct dma_chan *chan,
                                            enum dma_ctrl_cmd cmd,
                                            unsigned long arg)
 {
-        return chan->device->device_control(chan, cmd, arg);
+        if (chan->device->device_control)
+                return chan->device->device_control(chan, cmd, arg);
+
+        return -ENOSYS;
 }
 
 static inline int dmaengine_slave_config(struct dma_chan *chan,
@@ -618,6 +621,11 @@ static inline int dmaengine_slave_config(struct dma_chan *chan,
                         (unsigned long)config);
 }
 
+static inline bool is_slave_direction(enum dma_transfer_direction direction)
+{
+        return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
+}
+
 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
         struct dma_chan *chan, dma_addr_t buf, size_t len,
         enum dma_transfer_direction dir, unsigned long flags)
@@ -660,6 +668,13 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
                                                 period_len, dir, flags, NULL);
 }
 
+static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
+                struct dma_chan *chan, struct dma_interleaved_template *xt,
+                unsigned long flags)
+{
+        return chan->device->device_prep_interleaved_dma(chan, xt, flags);
+}
+
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
         return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
@@ -849,20 +864,6 @@ static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
 }
 
-#define first_dma_cap(mask) __first_dma_cap(&(mask))
-static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
-{
-        return min_t(int, DMA_TX_TYPE_END,
-                find_first_bit(srcp->bits, DMA_TX_TYPE_END));
-}
-
-#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
-static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
-{
-        return min_t(int, DMA_TX_TYPE_END,
-                find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
-}
-
 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
 static inline void
 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
@@ -891,9 +892,7 @@ __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
 }
 
 #define for_each_dma_cap_mask(cap, mask) \
-        for ((cap) = first_dma_cap(mask);       \
-                (cap) < DMA_TX_TYPE_END;        \
-                (cap) = next_dma_cap((cap), (mask)))
+        for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
 
 /**
  * dma_async_issue_pending - flush pending transactions to HW
@@ -907,8 +906,6 @@ static inline void dma_async_issue_pending(struct dma_chan *chan)
         chan->device->device_issue_pending(chan);
 }
 
-#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
-
 /**
  * dma_async_is_tx_complete - poll for transaction completion
  * @chan: DMA channel
@@ -934,16 +931,13 @@ static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
         return status;
 }
 
-#define dma_async_memcpy_complete(chan, cookie, last, used)\
-        dma_async_is_tx_complete(chan, cookie, last, used)
-
 /**
  * dma_async_is_complete - test a cookie against chan state
  * @cookie: transaction identifier to test status of
  * @last_complete: last know completed transaction
  * @last_used: last cookie value handed out
  *
- * dma_async_is_complete() is used in dma_async_memcpy_complete()
+ * dma_async_is_complete() is used in dma_async_is_tx_complete()
  * the test logic is separated for lightweight testing of multiple cookies
  */
 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
@@ -974,6 +968,7 @@ enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
 void dma_issue_pending_all(void);
 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
+struct dma_chan *dma_request_slave_channel(struct device *dev, char *name);
 void dma_release_channel(struct dma_chan *chan);
 #else
 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
@@ -988,6 +983,11 @@ static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
 {
         return NULL;
 }
+static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
+                                                         char *name)
+{
+        return NULL;
+}
 static inline void dma_release_channel(struct dma_chan *chan)
 {
 }
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index e1c8c9e919ac..41766de66e33 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -15,14 +15,38 @@
 #include <linux/dmaengine.h>
 
 /**
+ * struct dw_dma_slave - Controller-specific information about a slave
+ *
+ * @dma_dev: required DMA master device. Depricated.
+ * @bus_id: name of this device channel, not just a device name since
+ *          devices may have more than one channel e.g. "foo_tx"
+ * @cfg_hi: Platform-specific initializer for the CFG_HI register
+ * @cfg_lo: Platform-specific initializer for the CFG_LO register
+ * @src_master: src master for transfers on allocated channel.
+ * @dst_master: dest master for transfers on allocated channel.
+ */
+struct dw_dma_slave {
+        struct device           *dma_dev;
+        const char              *bus_id;
+        u32                     cfg_hi;
+        u32                     cfg_lo;
+        u8                      src_master;
+        u8                      dst_master;
+};
+
+/**
  * struct dw_dma_platform_data - Controller configuration parameters
  * @nr_channels: Number of channels supported by hardware (max 8)
  * @is_private: The device channels should be marked as private and not for
  *      by the general purpose DMA channel allocator.
+ * @chan_allocation_order: Allocate channels starting from 0 or 7
+ * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  * @block_size: Maximum block size supported by the controller
  * @nr_masters: Number of AHB masters supported by the controller
  * @data_width: Maximum data width supported by hardware per AHB master
  *              (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+ * @sd: slave specific data. Used for configuring channels
+ * @sd_count: count of slave data structures passed.
  */
 struct dw_dma_platform_data {
         unsigned int    nr_channels;
@@ -36,6 +60,9 @@ struct dw_dma_platform_data {
         unsigned short  block_size;
         unsigned char   nr_masters;
         unsigned char   data_width[4];
+
+        struct dw_dma_slave *sd;
+        unsigned int sd_count;
 };
 
 /* bursts size */
@@ -50,23 +77,6 @@ enum dw_dma_msize {
         DW_DMA_MSIZE_256,
 };
 
-/**
- * struct dw_dma_slave - Controller-specific information about a slave
- *
- * @dma_dev: required DMA master device
- * @cfg_hi: Platform-specific initializer for the CFG_HI register
- * @cfg_lo: Platform-specific initializer for the CFG_LO register
- * @src_master: src master for transfers on allocated channel.
- * @dst_master: dest master for transfers on allocated channel.
- */
-struct dw_dma_slave {
-        struct device           *dma_dev;
-        u32                     cfg_hi;
-        u32                     cfg_lo;
-        u8                      src_master;
-        u8                      dst_master;
-};
-
 /* Platform-configurable bits in CFG_HI */
 #define DWC_CFGH_FCMODE         (1 << 0)
 #define DWC_CFGH_FIFO_MODE      (1 << 1)
@@ -104,5 +114,6 @@ void dw_dma_cyclic_stop(struct dma_chan *chan);
 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
 
 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
+bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
 
 #endif /* DW_DMAC_H */
diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
new file mode 100644
index 000000000000..d15073e080dd
--- /dev/null
+++ b/include/linux/of_dma.h
@@ -0,0 +1,74 @@
+/*
+ * OF helpers for DMA request / controller
+ *
+ * Based on of_gpio.h
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_OF_DMA_H
+#define __LINUX_OF_DMA_H
+
+#include <linux/of.h>
+#include <linux/dmaengine.h>
+
+struct device_node;
+
+struct of_dma {
+        struct list_head        of_dma_controllers;
+        struct device_node      *of_node;
+        int                     of_dma_nbcells;
+        struct dma_chan         *(*of_dma_xlate)
+                                (struct of_phandle_args *, struct of_dma *);
+        void                    *of_dma_data;
+        int                     use_count;
+};
+
+struct of_dma_filter_info {
+        dma_cap_mask_t  dma_cap;
+        dma_filter_fn   filter_fn;
+};
+
+#ifdef CONFIG_OF
+extern int of_dma_controller_register(struct device_node *np,
+                struct dma_chan *(*of_dma_xlate)
+                (struct of_phandle_args *, struct of_dma *),
+                void *data);
+extern int of_dma_controller_free(struct device_node *np);
+extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
+                                                     char *name);
+extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
+                struct of_dma *ofdma);
+#else
+static inline int of_dma_controller_register(struct device_node *np,
+                struct dma_chan *(*of_dma_xlate)
+                (struct of_phandle_args *, struct of_dma *),
+                void *data)
+{
+        return -ENODEV;
+}
+
+static inline int of_dma_controller_free(struct device_node *np)
+{
+        return -ENODEV;
+}
+
+static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
+                                                     char *name)
+{
+        return NULL;
+}
+
+static inline struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
+                struct of_dma *ofdma)
+{
+        return NULL;
+}
+
+#endif
+
+#endif /* __LINUX_OF_DMA_H */
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 9ff93b065686..4b781014b0a0 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -147,6 +147,16 @@ struct stedma40_chan_cfg {
  * @memcpy_conf_log: default configuration of logical channel memcpy
  * @disabled_channels: A vector, ending with -1, that marks physical channels
  * that are for different reasons not available for the driver.
+ * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
+ * which avoids HW bug that exists in some versions of the controller.
+ * SoftLLI introduces relink overhead that could impact performace for
+ * certain use cases.
+ * @num_of_soft_lli_chans: The number of channels that needs to be configured
+ * to use SoftLLI.
+ * @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_phy_chans: The number of physical channels implemented in HW.
+ * 0 means reading the number of channels from DMA HW but this is only valid
+ * for 'multiple of 4' channels, like 8.
  */
 struct stedma40_platform_data {
         u32                              dev_len;
@@ -157,7 +167,10 @@ struct stedma40_platform_data {
         struct stedma40_chan_cfg        *memcpy_conf_phy;
         struct stedma40_chan_cfg        *memcpy_conf_log;
         int                              disabled_channels[STEDMA40_MAX_PHYS];
+        int                             *soft_lli_chans;
+        int                              num_of_soft_lli_chans;
         bool                             use_esram_lcla;
+        int                              num_of_phy_chans;
 };
 
 #ifdef CONFIG_STE_DMA40