diff options
| author | Jim Lin <jilin@nvidia.com> | 2012-09-18 04:42:17 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-09-18 12:40:56 -0400 |
| commit | 45c2da62199bcea380273b2fba7fa16c1ff27a30 (patch) | |
| tree | ccd818cee315c8fd64a7c3c536be9cb4e5dcfafc /include/linux | |
| parent | 8d733e26c076f47e7774c0e5baa74c9b1c01199a (diff) | |
USB: EHCI: Tegra: Fix wrong register definition
Fix the issue that EHCI registers, hostpc[0] and usbmode_ex,
are not correctly accessed on Tegra3 platform.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/usb/ehci_def.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h index 9a446302b658..daec99af5d54 100644 --- a/include/linux/usb/ehci_def.h +++ b/include/linux/usb/ehci_def.h | |||
| @@ -171,18 +171,18 @@ struct ehci_regs { | |||
| 171 | #define USBMODE_CM_HC (3<<0) /* host controller mode */ | 171 | #define USBMODE_CM_HC (3<<0) /* host controller mode */ |
| 172 | #define USBMODE_CM_IDLE (0<<0) /* idle state */ | 172 | #define USBMODE_CM_IDLE (0<<0) /* idle state */ |
| 173 | 173 | ||
| 174 | u32 reserved4[7]; | 174 | u32 reserved4[6]; |
| 175 | 175 | ||
| 176 | /* Moorestown has some non-standard registers, partially due to the fact that | 176 | /* Moorestown has some non-standard registers, partially due to the fact that |
| 177 | * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to | 177 | * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to |
| 178 | * PORTSCx | 178 | * PORTSCx |
| 179 | */ | 179 | */ |
| 180 | /* HOSTPC: offset 0x84 */ | 180 | /* HOSTPC: offset 0x84 */ |
| 181 | u32 hostpc[0]; /* HOSTPC extension */ | 181 | u32 hostpc[1]; /* HOSTPC extension */ |
| 182 | #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ | 182 | #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ |
| 183 | #define HOSTPC_PSPD (3<<25) /* Port speed detection */ | 183 | #define HOSTPC_PSPD (3<<25) /* Port speed detection */ |
| 184 | 184 | ||
| 185 | u32 reserved5[17]; | 185 | u32 reserved5[16]; |
| 186 | 186 | ||
| 187 | /* USBMODE_EX: offset 0xc8 */ | 187 | /* USBMODE_EX: offset 0xc8 */ |
| 188 | u32 usbmode_ex; /* USB Device mode extension */ | 188 | u32 usbmode_ex; /* USB Device mode extension */ |
