Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
  [ARM] Update mach-types
  ARM: 5636/1: Move vendor enum to AMBA include
  ARM: Fix pfn_valid() for sparse memory
  [ARM] orion5x: Add LaCie NAS 2Big Network support
  [ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
  ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
  ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
  ARM: 5689/1: Update default config of HP Jornada 700-series machines
  ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
  ARM: 5688/1: ks8695_serial: disable_irq() lockup
  ARM: 5687/1: fix an oops with highmem
  ARM: 5684/1: Add nuc960 platform to w90x900
  ARM: 5683/1: Add nuc950 platform to w90x900
  ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
  ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
  ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
  MMC: MMCI: convert realview MMC to use gpiolib
  ARM: 5685/1: Make MMCI driver compile without gpiolib
  ARM: implement highpte
  ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
  ...

Fix up trivial conflict in arch/arm/kernel/signal.c.

It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.

2 files changed, 85 insertions, 0 deletions

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 9b93cafa82a0..ab94335b4bb9 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -36,6 +36,11 @@ struct amba_driver {
         struct amba_id          *id_table;
 };
 
+enum amba_vendor {
+        AMBA_VENDOR_ARM = 0x41,
+        AMBA_VENDOR_ST = 0x80,
+};
+
 #define amba_get_drvdata(d)     dev_get_drvdata(&d->dev)
 #define amba_set_drvdata(d,p)   dev_set_drvdata(&d->dev, p)
 
diff --git a/include/linux/amba/pl093.h b/include/linux/amba/pl093.h
new file mode 100644
index 000000000000..2983e3671adb
--- /dev/null
+++ b/include/linux/amba/pl093.h
@@ -0,0 +1,80 @@
+/* linux/amba/pl093.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * AMBA PL093 SSMC (synchronous static memory controller)
+ *  See DDI0236.pdf (r0p4) for more details
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define SMB_BANK(x)     ((x) * 0x20) /* each bank control set is 0x20 apart */
+
+/* Offsets for SMBxxxxRy registers */
+
+#define SMBIDCYR        (0x00)
+#define SMBWSTRDR       (0x04)
+#define SMBWSTWRR       (0x08)
+#define SMBWSTOENR      (0x0C)
+#define SMBWSTWENR      (0x10)
+#define SMBCR           (0x14)
+#define SMBSR           (0x18)
+#define SMBWSTBRDR      (0x1C)
+
+/* Masks for SMB registers */
+#define IDCY_MASK       (0xf)
+#define WSTRD_MASK      (0xf)
+#define WSTWR_MASK      (0xf)
+#define WSTOEN_MASK     (0xf)
+#define WSTWEN_MASK     (0xf)
+
+/* Notes from datasheet:
+ *      WSTOEN <= WSTRD
+ *      WSTWEN <= WSTWR
+ *
+ * WSTOEN is not used with nWAIT
+ */
+
+/* SMBCR bit definitions */
+#define SMBCR_BIWRITEEN         (1 << 21)
+#define SMBCR_ADDRVALIDWRITEEN  (1 << 20)
+#define SMBCR_SYNCWRITE         (1 << 17)
+#define SMBCR_BMWRITE           (1 << 16)
+#define SMBCR_WRAPREAD          (1 << 14)
+#define SMBCR_BIREADEN          (1 << 13)
+#define SMBCR_ADDRVALIDREADEN   (1 << 12)
+#define SMBCR_SYNCREAD          (1 << 9)
+#define SMBCR_BMREAD            (1 << 8)
+#define SMBCR_SMBLSPOL          (1 << 6)
+#define SMBCR_WP                (1 << 3)
+#define SMBCR_WAITEN            (1 << 2)
+#define SMBCR_WAITPOL           (1 << 1)
+#define SMBCR_RBLE              (1 << 0)
+
+#define SMBCR_BURSTLENWRITE_MASK        (3 << 18)
+#define SMBCR_BURSTLENWRITE_4           (0 << 18)
+#define SMBCR_BURSTLENWRITE_8           (1 << 18)
+#define SMBCR_BURSTLENWRITE_RESERVED    (2 << 18)
+#define SMBCR_BURSTLENWRITE_CONTINUOUS  (3 << 18)
+
+#define SMBCR_BURSTLENREAD_MASK         (3 << 10)
+#define SMBCR_BURSTLENREAD_4            (0 << 10)
+#define SMBCR_BURSTLENREAD_8            (1 << 10)
+#define SMBCR_BURSTLENREAD_16           (2 << 10)
+#define SMBCR_BURSTLENREAD_CONTINUOUS   (3 << 10)
+
+#define SMBCR_MW_MASK                   (3 << 4)
+#define SMBCR_MW_8BIT                   (0 << 4)
+#define SMBCR_MW_16BIT                  (1 << 4)
+#define SMBCR_MW_M32BIT                 (2 << 4)
+
+/* SSMC status registers */
+#define SSMCCSR         (0x200)
+#define SSMCCR          (0x204)
+#define SSMCITCR        (0x208)
+#define SSMCITIP        (0x20C)
+#define SSMCITIOP       (0x210)